CN103094244B - 嵌埋穿孔中介层的封装基板及其制法 - Google Patents

嵌埋穿孔中介层的封装基板及其制法 Download PDF

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CN103094244B
CN103094244B CN201110427233.6A CN201110427233A CN103094244B CN 103094244 B CN103094244 B CN 103094244B CN 201110427233 A CN201110427233 A CN 201110427233A CN 103094244 B CN103094244 B CN 103094244B
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conductive
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embedded
perforation intermediary
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CN103094244A (zh
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胡迪群
曾子章
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Unimicron Technology Suzhou Corp
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Unimicron Technology Corp
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Abstract

一种嵌埋穿孔中介层的封装基板及其制法，该嵌埋穿孔中介层的封装基板包括：模封层、嵌埋于该模封层中且具有多个导电穿孔的穿孔中介层、嵌埋于该模封层中且设于该穿孔中介层上并电性连接该导电穿孔的其中一端面的线路重布层、以及设于该模封层与穿孔中介层上并电性连接该导电穿孔的另一端面的增层结构。借由嵌埋该穿孔中介层，使该线路重布层以电性结合间距较小的半导体芯片的电极垫，而另一端电性连接间距较大的增层结构的导电盲孔，令该封装基板可结合具有高布线密度的半导体芯片。

Description

嵌埋穿孔中介层的封装基板及其制法
技术领域
本发明涉及一种封装基板及其制法，尤指一种承载半导体芯片用的嵌埋穿孔中介层的封装基板及其制法。
背景技术
如图1所示，其为现有倒装芯片封装结构的剖视示意图，该封装结构的工艺先提供一具有核心板102、第一表面10a及第二表面10b的双马来酰亚胺-三氮杂苯(Bismaleimide-Triazine，BT)封装基板10，且于该封装基板10的第一表面10a形成有倒装芯片焊垫100；再借由焊锡凸块11电性连接半导体芯片12的电性连接垫120；接着，于该封装基板10的第一表面10a与该半导体芯片12之间形成底胶17，以包覆该焊锡凸块11；又于该封装基板10的第二表面10b具有植球垫101，以借由焊球13电性连接例如为印刷电路板的另一电子装置(未表示于图中)。
然而，为了增进该半导体芯片12的电性效能，所以于该半导体芯片12的后端工艺(Back-End Of Line，BEOL)中通常将采用超低介电系数(Extreme low-k dielectric，ELK)或超低介电常数(Ultra low-k，ULK)的介电材料，但该低k的介电材料为多孔且易脆的特性，以致于当进行倒装芯片封装后，在信赖度热循环测试时，将因该封装基板10与该半导体芯片12之间的热膨胀系数(thermal expansion coefficient，CTE)差异过大，导致该焊锡凸块11易因热应力不均而产生破裂，使该半导体芯片12产生破裂，造成产品可靠度不佳。
此外，随着电子产品更趋于轻薄短小及功能不断提升的需求，该半导体芯片12的布线密度愈来愈高，以纳米尺寸作单位，因而各该电性连接垫120之间的间距更小；然而，现有封装基板10的倒装芯片焊垫100的间距以微米尺寸作单位，而无法有效缩小至对应该电性连接垫120的间距的大小，导致虽有高线路密度的半导体芯片12，却未有可配合的封装基板，以致于无法有效生产电子产品。
因此，如何克服现有技术中的种种问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺失，本发明的主要目的在于提供一种嵌埋穿孔中介层的封装基板及其制法，使封装基板可结合具有高布线密度的半导体芯片，而达到整合高布线密度的半导体芯片的目的。
本发明的另一目的在于提供一种嵌埋穿孔中介层的封装基板及其制法，可避免该半导体芯片与该穿孔中介层之间的焊锡凸块破裂，有效使产品的可靠度提升。
本发明所提供的嵌埋穿孔中介层的封装基板包括：模封层；嵌埋于该模封层中的穿孔中介层，其具有多个导电穿孔，该导电穿孔的相对两端面均外露于该穿孔中介层；嵌埋于该模封层中且设于该穿孔中介层上的线路重布层，其电性连接该导电穿孔的其中一端面；以及设于该模封层与穿孔中介层上的增层结构，其电性连接该导电穿孔的另一端面。
本发明还提供一种嵌埋穿孔中介层的封装基板的制法，其包括：提供一具有多个导电穿孔的穿孔中介层，该导电穿孔的相对两端面均外露于该穿孔中介层，又于该穿孔中介层上形成电性连接该导电穿孔一端面的线路重布层；将一模封层包覆该穿孔中介层，使该穿孔中介层与线路重布层嵌埋于该模封层中；以及于该模封层、该穿孔中介层上形成电性连接该导电穿孔另一端面的增层结构。
前述的嵌埋穿孔中介层的封装基板及其制法中，该导电穿孔的另一端面可凸出该穿孔中介层，以作为导电凸块，以供电性连接该增层结构。
由上可知，本发明嵌埋穿孔中介层的封装基板及其制法中，其借由嵌埋该穿孔中介层，使该导电穿孔的其中一端电性连接该线路重布层以电性结合间距较小的半导体芯片的电性连接垫，而另一端电性连接间距较大的增层结构的导电盲孔，使该封装基板可结合具有高布线密度的半导体芯片，而达到整合高布线密度的半导体芯片的目的。所以借由该中介层，不仅可解决缺乏可配合的封装基板的问题，且不会改变IC产业原本的供应链(supply chain)及基础设备(infrastructure)。
此外，若将半导体芯片设于该穿孔中介层上，因该穿孔中介层的热膨胀系数与半导体芯片的热膨胀系数相近，所以可避免该半导体芯片与该穿孔中介层之间的焊锡凸块破裂，有效使产品的可靠度提升。
再者，借由将该穿孔中介层嵌埋于该模封层中，可降低整体结构的厚度，且借由于该模封层的第二表面上形成增层结构，所以无需使用现有技术的核心板，也可降低整体结构的厚度。
附图说明
图1为现有倒装芯片封装结构的剖视示意图；
图2A至图2J为本发明嵌埋穿孔中介层的封装基板的制法的第一实施例的剖视示意图；图2I’、图2I”为图2I的其它实施例，图2J’、图2J”、图2K为图2J的其它实施例；
图3A至图3E为本发明嵌埋穿孔中介层的封装基板的制法的第二实施例的剖视示意图；图3D’、图3D”为图3D的其它实施例，图3E’、图3E”为图3E的其它实施例；以及
图4A、图4A’及图4A”为本发明嵌埋穿孔中介层的封装基板的第三实施例的剖视示意图。
主要组件符号说明
10，3，3’，3”，4，4’，4”     封装基板
10a，22a，22a’，22a”           第一表面
10b，22b                         第二表面
100                              倒装芯片焊垫
101                              植球垫
102                              核心板
11                               焊锡凸块
12                               半导体芯片
120                              电性连接垫
13，25                           焊球
17                    底胶
2，2’，2”，5        封装基板
20，30                穿孔中介层
20’                  中介层
20a，30a              第一侧
20b，20b’，30b       第二侧
200，300              导电穿孔
200’                 穿孔
200a，300a            第一端面
200b，300b            第二端面
201                   绝缘层
21                    线路重布层
210                   电极垫
22                    模封层
220，240              开孔
23                    增层结构
230                   介电层
230a                  线路槽
231，231’            线路层
232，232’            导电盲孔
233                   电性接触垫
24                    绝缘保护层
301                   导电凸块
K，L                  假想线。
具体实施方式
以下借由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，所以不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”及“一”等用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，也当视为本发明可实施的范畴。
请参阅图2A至图2J，其为本发明嵌埋穿孔中介层的封装基板的制法的第一实施例的剖视示意图。
如图2A所示，提供一中介层20’，该中介层20’具有相对的第一侧20a与第二侧20b’，再于该中介层20’的第一侧20a形成多个穿孔200’。
于本实施例中，该中介层20’的材质为硅。
如图2B所示，于该穿孔200’的侧壁与底部上形成绝缘层201，再于该穿孔200’中形成铜材，以形成导电穿孔200，该导电穿孔200具有对应该中介层20’的第一侧20a与第二侧20b’的第一端面200a与第二端面200b。
于本实施例中，形成该导电穿孔200的材质也可为镍、金、钨、铝或导电膏，而该绝缘层201的材质可为SiO2、Si3N4或Polymer，又该导电穿孔200的第一端面200a与该中介层20’的第一侧20a齐平。
另外，要补充说明的是，本发明的中介层20’除了如前述图2B的实施例之外，也可为不具有该绝缘层201的实施例，也就是该中介层20’的材质可为玻璃、或例如为Al2O3或AlN的陶瓷等绝缘材料，并在该中介层20’中直接形成贯穿的导电穿孔200，由于此实施例所属技术领域的通常知识者所能了解，所以不在此加以赘述与图标。
如图2C所示，于该中介层20’的第一侧20a与该导电穿孔200的第一端面200a上形成线路重布层(Redistribution layer，RDL)21，该线路重布层21电性连接该导电穿孔200的第一端面200a，且该线路重布层21的最外层具有多个电极垫210。
如图2D所示，将该中介层20’的第一侧20a与该线路重布层21结合至一载板(图未示)上，再经研磨该中介层20’的第二侧20b’，使该导电穿孔200的第二端面200b外露于该穿孔中介层20的第二侧20b，再移除该载板，以完成该穿孔中介层20的制作。
于本实施例中，该导电穿孔200的第二端面200b与该穿孔中介层20的第二侧20b齐平，且该导电穿孔200连通该穿孔中介层20的第一侧20a与第二侧20b，又该导电穿孔200仅于侧壁上具有绝缘层201。
此外，所述的载板的材质选用与该中介层20’相同或相近的材质，以利于结合该中介层20’，所以该载板的材质可例如为硅、玻璃、或Al2O3、AlN的陶瓷等绝缘材料，而于本实施例中，该载板的材质选用玻璃。
再者，该载板与该中介层20’的结合方式可为粘贴式。
如图2E所示，于如图2D所示的切割假想线K处进行切单后，得到多个穿孔中介层20。
如图2F所示，于一玻璃载板(图未示)上重新排列该些穿孔中介层20，使该些穿孔中介层20的第二侧20b与该导电穿孔200的第二端面200b结合至该玻璃载板上，再将一模封层22包覆该些穿孔中介层20，使该些穿孔中介层20嵌埋于该模封层22中，再移除该玻璃载板。
于本实施例中，该模封层22具有相对的第一表面22a及第二表面22b，以令该穿孔中介层20的第二侧20b与该导电穿孔200的第二端面200b与该模封层22的第二表面22b齐平，且该模封层22覆盖该线路重布层21与该些电极垫210。
如图2G至图2I所示，于该模封层22的第二表面22b、该穿孔中介层20的第二侧20b与该导电穿孔200的第二端面200b上形成增层结构23。
如图2G所示，先形成一如ABF(Ajinomoto Build-up Film)的介电层230，再于该介电层230上以激光方式形成多个线路槽(包含盲孔)230a，以外露出该导电穿孔200的第二端面200b。于本实施例中，形成该介电层230的方式可为涂布或压合工艺，而形成该介电层230的材料亦可为PI(Polyimide)、PP(prepreg)或苯环丁烯(Benzocyclobutene，BCB)。
如图2H所示，于该线路槽230a中电镀形成线路层231与多个导电盲孔232’，使该线路层231嵌埋于该介电层230中，且该些导电盲孔232’对应电性连接该导电穿孔200的第二端面200b。于本实施例中，先于该线路槽230a中与介电层230上形成铜材以作为导电层(图未示)，再于该线路槽230a中与介电层230上电镀金属材，以形成该线路层231与该些导电盲孔232’，最后移除该介电层230底面上的金属材与导电层。
因此，本发明的嵌埋式线路层231的工艺，可免用蚀刻方式，因而可克服线路因蚀刻液的侧蚀而损坏线路尺寸，进而导致线路需作成较大的尺寸的缺失。所以当使用体积较小的穿孔中介层20时，仍可制作出更精密的线路，以对应连接较微小的导电穿孔200。
如图2I所示，依实际层数需求，可制作多层线路结构。于本实施例中，该增层结构23具有至少一介电层230、嵌埋于该介电层230中的线路层231、及设于该介电层230中并电性连接该线路层231的多个导电盲孔232，而部分的导电盲孔232’对应电性连接该导电穿孔200的第二端面200b。
接着，于该增层结构23上形成绝缘保护层24，且该绝缘保护层24形成有多个开孔240，以外露部份的线路层231，以供作为电性接触垫233。
于其它实施例中，也可移除该模封层22的第一表面22a的部分材质，令该电极垫210外露于该模封层22的第一表面22a’，22a”，以供接置半导体芯片(图未示)。如图2I’所示，于该模封层22的第一表面22a’形成多个开孔220，令该电极垫210对应外露于该开孔220。或者，如图2I”所示，使该模封层22的第一表面22a”的高度齐平或低于该电极垫210的高度，令该电极垫210外露于该模封层22的第一表面22a”。
如图2J、图2J’、图2J”所示，于如图2I所示的切割假想线L处将图2I、图2I’、图2I”的结构进行切单后，可取得多个嵌埋穿孔中介层20的封装基板2，2’，2”。
于切单工艺前或于后续工艺中，可于该些电性接触垫233上结合焊球25，以接置其它电子装置，如电路板或封装件。
另外，如图2K所示，于其它实施例的封装基板5中，该增层结构23的线路层231’也可形成于该介电层230的表面上，而非嵌埋型式。
本发明还提供一种嵌埋穿孔中介层20的封装基板2，2’，2”，包括：具有相对的第一表面22a，22a’，22a”及第二表面22b的模封层22、嵌埋于该模封层22中的穿孔中介层20、嵌埋于该模封层22中且设于该穿孔中介层20上的线路重布层21、设于该模封层22的第二表面22b上的增层结构23、以及设于该增层结构23上的绝缘保护层24。
所述的穿孔中介层20具有相对的第一侧20a与第二侧20b、及连通该第一侧20a与第二侧20b的多个导电穿孔200，该导电穿孔200于该第一侧20a与第二侧20b上分别具有第一端面200a与第二端面200b，且该导电穿孔200的侧壁上可具有绝缘层201，又该穿孔中介层20的第二侧20b与该导电穿孔200的第二端面200b与该模封层22的第二表面22b齐平。
所述的线路重布层21设于该穿孔中介层20的第一侧20a与该导电穿孔200的第一端面200a上，并电性连接该导电穿孔200的第一端面200a，而该线路重布层21的最外层具有多个电极垫210。
所述的模封层22可覆盖该些电极垫210，如图2J所示；也可令该些电极垫210外露于该模封层22的第一表面22a’，22a”，如图2J’、图2J”所示。
所述的增层结构23还设于该穿孔中介层20的第二侧20b与该导电穿孔200的第二端面200b上，且具有至少一介电层230、嵌埋于该介电层230中的线路层231、及设于该介电层230中并电性连接该线路层231的多个导电盲孔232，而部分的导电盲孔232’对应电性连接该导电穿孔200的第二端面200b。
所述的绝缘保护层24形成有多个开孔240，以外露部分的线路层231，以供作为电性接触垫233。
本发明的嵌埋穿孔中介层20的封装基板2，2’，2”及其制法，主要借由嵌埋该穿孔中介层20，使该导电穿孔200的第一端面200a电性连接该线路重布层21以电性结合间距较小的半导体芯片(图未示)的电性连接垫(如图2J’、图2J”所示)，而第二端面200b电性连接间距较大的增层结构23的导电盲孔232’，使该封装基板2，2’，2”可结合具有高布线密度的半导体芯片，而达到整合高布线密度的半导体芯片的目的。
此外，若将半导体芯片设于该穿孔中介层20上，且该穿孔中介层20的热膨胀系数与半导体芯片的热膨胀系数相近(CET均约为2.6ppm)，所以可避免该半导体芯片与该穿孔中介层20之间的焊锡凸块破裂，因而有效使产品的可靠度提升。
再者，将该穿孔中介层20嵌埋于该模封层22中，可降低整体结构的厚度，且于该模封层22的第二表面22b上形成增层结构23，所以无需使用现有技术的核心板，也可降低整体结构的厚度。
请参阅图3A至图3E，其为本发明嵌埋穿孔中介层30的封装基板3的制法的第二实施例的剖视示意图。本实施例与第一实施例的差异仅在于该穿孔中介层30具有导电凸块301，其它相关工艺大致相同。
如图3A所示，提供一图2D所示的穿孔中介层20。
如图3B所示，蚀刻移除该穿孔中介层20的第二侧20b的部分材质，使该导电穿孔300的第二端面300b凸出该穿孔中介层30的第二侧30b，令该导电穿孔300的凸出部分作为导电凸块301(可包含该绝缘层201)。
如图3C所示，于如图3B所示的切割假想线K处切单后，取得多个穿孔中介层30。
接着，将一具有相对的第一表面22a及第二表面22b的模封层22包覆该些穿孔中介层30，使该穿孔中介层30嵌埋于该模封层22中，且该穿孔中介层30的第二侧30b外露于该模封层22的第二表面22b，而该导电凸块301凸出该模封层22的第二表面22b，又该模封层22覆盖该线路重布层21与该些电极垫210。
如图3D所示，于该模封层22的第二表面22b、该穿孔中介层30的第二侧30b与该导电凸块301上形成增层结构23，该增层结构23具有至少一介电层230、嵌埋于该介电层230中的线路层231、及设于该介电层230中并电性连接该线路层231的多个导电盲孔232，而部分的导电盲孔232’对应电性连接该导电凸块301。
接着，于该增层结构23上形成绝缘保护层24，且该绝缘保护层24形成有多个开孔240，以外露部份的线路层231，以供作为电性接触垫233。
于其它实施例中，也可移除该模封层22的第一表面22a的部分材质，令该电极垫210外露于该模封层22的第一表面22a’，22a”。如图3D’所示，于该模封层22的第一表面22a’形成多个开孔220，令该电极垫210对应外露于该开孔220。或者，如图3D”所示，使该模封层22的第一表面22a”的高度齐平或低于该电极垫210的高度，令该电极垫210外露于该模封层22的第一表面22a”。
如图3E、图3E’、图3E”所示，于如图3D所示的切割假想线L处将图3D、图3D’、图3D”的结构进行切单后，可取得多个嵌埋穿孔中介层30的封装基板3，3’，3”。
于切单工艺前或于后续工艺中，可于该些电性接触垫233上结合焊球25，以接置其它电子装置，如电路板或封装件。
本发明的制法中，借由该导电穿孔300的第二端面300b凸出该穿孔中介层30的第二侧30b以作为导电凸块301，当制作该增层结构23以激光形成该线路槽230a时，激光产生的高温及压力将被硬质材的该导电凸块301吸收，以避免破坏由脆弱材质所制成的穿孔中介层30。
此外，若该导电穿孔200的第二端面200b与该穿孔中介层20的第二侧20b齐平时，如图3A所示，为了避免激光形成该线路槽230a时而破坏该穿孔中介层20，虽可直接于该导电穿孔200的第二端面200b上结合凸块(图未示)，以代替蚀刻移除该穿孔中介层20的第二侧20b的部分材质而形成导电凸块301的工艺，但此方式所形成的凸块的高度至少需30μm，因而不利于微小化的穿孔中介层30。
再者，若该导电穿孔200的第二端面200b与该穿孔中介层20的第二侧20b齐平时，如图3A所示，为了避免激光形成该线路槽230a时而破坏该穿孔中介层20，也可于该导电穿孔200的第二端面200b上进行化镍金工艺以吸收激光，而不需形成该导电凸块301，但此方式将导致成本提高，且工艺温度高，药水攻击性强。
请参阅图4A、图4A’及图4A”，其为本发明嵌埋穿孔中介层30的封装基板4，4’，4”的第三实施例的剖视示意图。本实施例与第二实施例的差异仅在于线路层形成于该介电层上，其它相关工艺均相同。
如图4A、图4A’及图4A”所示，该增层结构23的线路层231’设于该介电层230的表面上。
本发明还提供一种嵌埋穿孔中介层30的封装基板3，3’，3”，4，4’，4”，包括：具有相对的第一表面22a，22a’，22a”及第二表面22b的模封层22、嵌埋于该模封层22中的穿孔中介层30、嵌埋于该模封层22中且设于该穿孔中介层30上的线路重布层21、设于该模封层22的第二表面22b上的增层结构23、以及设于该增层结构23上的绝缘保护层24。
所述的穿孔中介层30具有相对的第一侧30a与第二侧30b、及连通该第一侧30a与第二侧30b的多个导电穿孔300，该导电穿孔300于该第一侧30a与第二侧30b上分别具有第一端面300a与第二端面300b，且该导电穿孔300的侧壁上可具有绝缘层201，而该第二侧30b外露于该模封层22的第二表面22b，又该导电穿孔300的第二端面300b凸出该穿孔中介层30的第二侧30b与该模封层22的第二表面22b，以作为导电凸块301。
所述的线路重布层21设于该穿孔中介层30的第一侧30a与该导电穿孔300的第一端面300a上，并电性连接该导电穿孔300的第一端面300a，而该线路重布层21的最外层具有多个电极垫210。
所述的模封层22可覆盖该些电极垫210，如图3E所示；也可令该些电极垫210外露于该模封层22的第一表面22a’，22a”，如图3E’、图3E”所示。
所述的增层结构23还设于该穿孔中介层30的第二侧30b与该导电穿孔300的第二端面300b上，且具有至少一介电层230、嵌埋于该介电层230中的线路层231(如图3E、图3E’、图3E”所示)、及设于该介电层230中并电性连接该线路层231的多个导电盲孔232，而部分的导电盲孔232’对应电性连接该导电凸块301。此外，该线路层231’也可设于该介电层230上，如图4A、图4A’及图4A”所示。
所述的绝缘保护层24形成有多个开孔240，以外露部分的线路层231，以供作为电性接触垫233。
综上所述，本发明的嵌埋穿孔中介层的封装基板及其制法，借由将中介层嵌埋于模封层中，不仅可解决缺乏可配合的封装基板的问题，且不会改变IC产业原本的供应链(supply chain)及基础设备(infrastructure)，以符合微小化与低成本的需求。
上述实施例用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (21)

1.一种嵌埋穿孔中介层的封装基板，其包括：
模封层，其具有相对的第一表面及第二表面；
穿孔中介层，其嵌埋于该模封层中，且具有相对的第一侧与第二侧、及连通该第一侧与第二侧的多个导电穿孔，该导电穿孔于该第一侧与第二侧上分别具有第一端面与第二端面，且该穿孔中介层的第二侧与该导电穿孔的第二端面与该模封层的第二表面齐平；
线路重布层，其嵌埋于该模封层中且设于该穿孔中介层的第一侧与该导电穿孔的第一端面上，并电性连接该导电穿孔的第一端面，而该线路重布层的最外层具有电极垫；以及
增层结构，其设于该模封层的第二表面、该穿孔中介层的第二侧与该导电穿孔的第二端面上，且具有至少一介电层、嵌埋于该介电层中的线路层、及设于该介电层中并电性连接该线路层的多个导电盲孔，而部分的导电盲孔对应电性连接该导电穿孔的第二端面。
2.根据权利要求1所述的嵌埋穿孔中介层的封装基板，其特征在于，该导电穿孔的侧壁上具有绝缘层。
3.根据权利要求1所述的嵌埋穿孔中介层的封装基板，其特征在于，该封装基板还包括绝缘保护层，其设于该增层结构上，且具有多个开孔，以外露部分的线路层，以供作为电性接触垫。
4.根据权利要求1所述的嵌埋穿孔中介层的封装基板，其特征在于，该模封层覆盖该电极垫。
5.根据权利要求1所述的嵌埋穿孔中介层的封装基板，其特征在于，该电极垫外露于该模封层的第一表面。
6.一种嵌埋穿孔中介层的封装基板，其包括：
模封层，其具有相对的第一表面及第二表面；
穿孔中介层，其嵌埋于该模封层中，且具有相对的第一侧与第二侧、及连通该第一侧与第二侧的多个导电穿孔，该导电穿孔于该第一侧与第二侧上分别具有第一端面与第二端面，且该第二侧外露且齐平于该模封层的第二表面，又该导电穿孔的第二端面凸出该穿孔中介层的第二侧与该模封层的第二表面，以作为导电凸块；
线路重布层，其嵌埋于该模封层中且设于该穿孔中介层的第一侧与该导电穿孔的第一端面上，并电性连接该导电穿孔的第一端面，而该线路重布层的最外层具有电极垫；以及
增层结构，其设于该模封层的第二表面、该穿孔中介层的第二侧与该导电凸块上，且具有至少一介电层、设于该介电层上的线路层、及设于该介电层中并电性连接该线路层的多个导电盲孔，而部分的导电盲孔对应电性连接该导电凸块。
7.根据权利要求6所述的嵌埋穿孔中介层的封装基板，其特征在于，该导电穿孔的侧壁上具有绝缘层。
8.根据权利要求6所述的嵌埋穿孔中介层的封装基板，其特征在于，该封装基板还包括绝缘保护层，其设于该增层结构上，且具有多个开孔，以外露部分的线路层，以供作为电性接触垫。
9.根据权利要求6所述的嵌埋穿孔中介层的封装基板，其特征在于，该线路层嵌埋于该介电层中。
10.根据权利要求6所述的嵌埋穿孔中介层的封装基板，其特征在于，该模封层覆盖该电极垫。
11.根据权利要求6所述的嵌埋穿孔中介层的封装基板，其特征在于，该电极垫外露于该模封层的第一表面。
12.一种嵌埋穿孔中介层的封装基板的制法，其包括：
提供一穿孔中介层，该穿孔中介层具有相对的第一侧与第二侧、及连通该第一侧与第二侧的多个导电穿孔，该导电穿孔于该第一侧与第二侧上分别具有第一端面与第二端面，而该导电穿孔的第二端面与该穿孔中介层的第二侧齐平，又于该穿孔中介层的第一侧与该导电穿孔的第一端面上形成线路重布层，该线路重布层电性连接该导电穿孔的第一端面，且该线路重布层的最外层具有电极垫；
将一模封层包覆该穿孔中介层，使该穿孔中介层嵌埋于该模封层中，且该模封层具有相对的第一表面及第二表面，以令该穿孔中介层的第二侧与该导电穿孔的第二端面与该模封层的第二表面齐平，且该模封层覆盖该线路重布层与该电极垫；以及
于该模封层的第二表面、该穿孔中介层的第二侧与该导电穿孔的第二端面上形成增层结构，该增层结构具有至少一介电层、嵌埋于该介电层中的线路层、及设于该介电层中并电性连接该线路层的多个导电盲孔，而部分的导电盲孔对应电性连接该导电穿孔的第二端面。
13.根据权利要求12所述的嵌埋穿孔中介层的封装基板的制法，其特征在于，该导电穿孔的侧壁上具有绝缘层。
14.根据权利要求12所述的嵌埋穿孔中介层的封装基板的制法，其特征在于，该线路层的工艺包括：
形成该介电层；
于该介电层上形成线路槽；以及
于该线路槽中形成该线路层。
15.根据权利要求12所述的嵌埋穿孔中介层的封装基板的制法，其特征在于，该制法还包括于该增层结构上形成绝缘保护层，且该绝缘保护层具有多个开孔，以外露部份的线路层，以供作为电性接触垫。
16.根据权利要求12所述的嵌埋穿孔中介层的封装基板的制法，其特征在于，该制法还包括移除该模封层的第一表面的部分材质，令该电极垫外露于该模封层的第一表面。
17.一种嵌埋穿孔中介层的封装基板的制法，其包括：
提供一穿孔中介层，该穿孔中介层具有相对的第一侧与第二侧、及连通该第一侧与第二侧的多个导电穿孔，该导电穿孔于该第一侧与第二侧上分别具有第一端面与第二端面，而该导电穿孔的第二端面凸出该穿孔中介层的第二侧，以作为导电凸块，又于该穿孔中介层的第一侧与该导电穿孔的第一端面上形成线路重布层，该线路重布层电性连接该导电穿孔的第一端面，且该线路重布层的最外层具有电极垫；
将一模封层包覆该穿孔中介层，使该穿孔中介层嵌埋于该模封层中，且该模封层具有相对的第一表面及第二表面，令该穿孔中介层的第二侧外露且齐平于该模封层的第二表面，且该导电凸块凸出该模封层的第二表面，而该模封层覆盖该线路重布层与该电极垫；以及
于该模封层的第二表面、该穿孔中介层的第二侧与该导电凸块上形成增层结构，该增层结构具有至少一介电层、设于该介电层上的线路层、及设于该介电层中并电性连接该线路层的多个导电盲孔，而部分的导电盲孔对应电性连接该导电凸块。
18.根据权利要求17所述的嵌埋穿孔中介层的封装基板的制法，其特征在于，该导电穿孔的侧壁上具有绝缘层。
19.根据权利要求17所述的嵌埋穿孔中介层的封装基板的制法，其特征在于，该制法还包括于该增层结构上形成绝缘保护层，且该绝缘保护层具有多个开孔，以外露部份的线路层，以供作为电性接触垫。
20.根据权利要求17所述的嵌埋穿孔中介层的封装基板的制法，其特征在于，该线路层嵌埋于该介电层中。
21.根据权利要求17所述的嵌埋穿孔中介层的封装基板的制法，其特征在于，该制法还包括移除该模封层的第一表面的部分材质，令该电极垫外露于该模封层的第一表面。
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