CN102376667A - 封装装置及其制造方法 - Google Patents
封装装置及其制造方法 Download PDFInfo
- Publication number
- CN102376667A CN102376667A CN2011100585204A CN201110058520A CN102376667A CN 102376667 A CN102376667 A CN 102376667A CN 2011100585204 A CN2011100585204 A CN 2011100585204A CN 201110058520 A CN201110058520 A CN 201110058520A CN 102376667 A CN102376667 A CN 102376667A
- Authority
- CN
- China
- Prior art keywords
- dielectric layer
- openings
- conductive
- substrate
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/099—Coating over pads, e.g. solder resist partly over pads
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
Abstract
本发明提供一用以封装衬底及用于倒装芯片集成电路组成的封装装置及方法。该封装装置提供一衬底,其具有一阻焊层,在阻焊层中具有暴露导电凸块焊盘的开口,及在导电凸块焊盘之间暴露阻焊层底下的介电层的开口。倒装芯片集成电路使用热回焊连接至衬底,将集成电路上的导电焊料凸块回焊至导电凸块焊盘上。涂布底部填充材料至集成电路下方并与其与衬底的介电层物理接触。在其他实施例中,一或多个集成电路以倒装芯片方式粘着于衬底上。依上述方法所形成的结构相较于公知技术的结构具有较佳的热效能。
Description
技术领域
本发明涉及封装装置,且特别涉及一种具有较佳的热效能的封装装置及其制造方法。
背景技术
现今对于先进电路的一般性需求,且特别是对于在半导体工艺中制造的集成电路(IC),为使用衬底或转接板,以安装于终端上具有凸块或用于集成体电路连接的“倒装芯片”集成电路。在倒装芯片封装中,焊料凸块包括含铅或无铅的焊料组成物,其设置于集成电路上并朝下面对衬底,以及使用热回焊工艺来完成焊料连接。这些集成电路装置可具有数十或数百个输入或输出终端,用以接收或送出信号及/或用以连接至电源供应器。
在倒装芯片封装的应用中,集成电路设置于朝下面对(flipped)所对应的衬底。集成电路设置为朝下面对封装衬底。衬底具有一芯部(core),其镀有自管芯侧(die side)延伸至电路板侧的贯穿孔连接。衬底包含介电层及同时在上侧及下侧有多层金属连线。介电层可由绝缘材料形成,例如包含聚酰亚胺、有机物、无机物、树脂、环氧化物及其类似物。
设置于衬底的管芯侧的导电凸块焊盘称为“凸块焊盘(bump pads)”。这些凸块焊盘与位于导电凸块焊盘上的预焊材料(pre-solder material)电性连接。预焊材料设置于形成于阻焊材料中的开口中,这些区域称为防焊开口(solder resist openings,SROs)。自衬底的管芯侧上的多层金属图案穿过芯部至衬底的电路板侧,形成连线。这些连线可由例如填入导电插塞至电镀的贯穿孔中形成。衬底的金属层可使用镀铜技术形成,可无电电镀籽晶层至衬底的额外的堆叠层或其他介电层上。
倒装芯片集成电路可面朝下的设置,并使集成电路上的焊料凸块或焊条沿着所对应的凸块焊盘对齐,以使焊料及预焊材料相接触。使用热回焊来进行管芯连接工艺,融解焊料及预焊材料并接着让其冷却。在回焊时,焊料及预焊材料在集成电路管芯及衬底之间形成电性及机械连接。
在管芯连接之后,于集成电路底下涂布(dispense)底部填充材料。在公知技术中,底部填充材料与集成电路、焊料凸块及阻焊材料的表面接触。
如本领域所熟知,热失配(thermal mismatch)通常发生在集成电路封装中的不同材料之间。例如,热失配会在集成电路、半导体及衬底之间发生。材料具有不同的热膨胀系数(coefficient of thermal expansion,CTE)时,会在操作装置及材料温度变化时导致机械应力。通常,底部填充材料为在热回焊工艺后涂布于集成电路及衬底之间。通常,会选择能释放机械应力的材料,以预防热应力对装置造成损伤。选用底部填充材料,能在热应力发生时帮助保护管芯及焊料凸块,以减少机械破坏(例如凸块破裂等)的可能性。
尽管如此,热致机械应力依旧存在于公知的倒装芯片封装集成电路中,例如可观察到凸块破料、邻近凸块间的桥接短路及在底部填充材料及介电层中(脱层)的破裂等损坏。底部填充材料与衬底上的阻焊材料仍具有实质上不同的热膨胀系数性质,以使热膨胀系数的失配仍旧存在。因此,在公知技术中,就算使用底部填充材料仍会有热损坏发生。
发明内容
为克服现有技术缺陷,本发明的一实施例提供一种封装装置,包括:一封装衬底,包含:一介电层,位于该衬底的一管芯侧表面;多个导电焊盘,形成于该介电层的表面;及一阻焊层,设置于该导电焊盘及该介电层上,其中该阻焊材料包含多个第一开口及多个第二开口,所述多个第一开口暴露所述多个导电焊盘,所述多个第二开口暴露介于所述多个导电焊盘之间的该介电层的表面,所述多个第二开口与所述多个导电焊盘具有至少10微米的间距。
本发明的另一实施例也提供一种封装装置的制造方法,包括:形成一介电层于一封装衬底的一管芯侧表面,其中该介电层的表面上具有多个导电凸块焊盘与该介电层中的金属导电层连接;以一阻焊材料覆盖该介电层及所述多个导电凸块焊盘;依照所述多个导电凸块焊盘在该阻焊材料中形成多个第一开口;以及在所述多个导电凸块焊盘之间形成多个第二开口,所述多个第二开口延伸穿越该阻焊材料且暴露该介电层的表面。
本发明的又一实施例更提供一种封装装置,包括:一封装衬底,包含:一介电层,位于一衬底的芯部的两侧上;多个导电焊盘,形成于该介电层的表面;至少一集成电路管芯,粘着于所述多个导电焊盘上;一阻焊层,设置于所述多个导电焊盘及该介电层上;以及一底部填充材料,设置于至少一集成电路管芯及该衬底之间,其中该阻焊层包含暴露所述多个导电焊盘的第一开口;及暴露所述多个导电焊盘之间的介电层的表面的第二开口,该底部填充材料与所述多个第二开口中的该介电层的表面相接触,所述多个第二开口与所述多个导电焊盘具有至少10微米的间距。
本发明提供新颖的方法及装置来减少集成电路封装中的热应力。衬底用于设置具有焊料凸块的倒装芯片集成电路。防焊开口暴露出一部分的衬底介电层,以使底部填充材料与衬底介电层物理接触。相较于先前的封装体结构,通过减少热循环中的机械应力增进整个封装体的热效能。
为让本发明的上述和其他目的、特征、优点能更明显易懂,下文特举出较佳实施例,并配合附图,作详细说明如下。
附图说明
图1显示本发明一实施例的剖面图。
图2显示图1的实施例的用于集成电路组成的实施例中的剖面图。
图3显示本发明另一实施例的具有两倒装芯片集成电路管芯设置于其上的衬底组成的剖面图。
其中,附图标记说明如下:
具体实施方式
本发明接下来将会提供许多不同的实施例以实施本发明中不同的特征。然而,这些实施例并非用于限定本发明。以下所讨论的特定实施例仅用于举例本发明实施例的制造及使用,但不限定本发明的范畴。
在此,将详细描述本发明实施例,提供新颖的方法及装置来减少集成电路封装中的热应力。衬底用于设置具有焊料凸块的倒装芯片集成电路。防焊开口暴露出一部分的衬底介电层,以使底部填充材料与衬底介电层物理接触。相较于先前的封装体结构,通过减少热循环中的机械应力增进整个封装体的热效能。
在图1中,显示为本发明一实施例的剖面图。首先,提供衬底11。衬底11可具有贯穿孔25的芯部19形成,贯穿孔25镀有例如铜及其合金、或镀有其他导电金属及其合金的导体。贯穿孔25中填有导电插塞或填充材料21。介电层16可为额外的堆积层或其他绝缘体,在图中其显示为覆盖芯部19的两侧。多层金属层18为例如形成在水平及垂直方向的导电通路。阻焊材料15位于电路板的两侧,围绕球焊盘(ball lands)24。球焊盘(ball lands)24位于管芯侧上(图1中衬底的上侧),设计用于承接焊球以制造封装集成电路至外部的电性连接。凸块焊盘17位于介电层16的上部或管芯侧表面,并由具有防焊开口(solder resist openings,SROs)于其中的阻焊材料15所覆盖。在阻焊材料15中,填有预焊材料27。
防焊开口33形成于图1的衬底11的管芯侧上。在一实施例中,在阻焊材料15上进行激光钻孔工艺步骤以形成防焊开口33。在此实施例中,此步骤可在于凸块焊盘17上设置预焊材料27之后进行。在任何情况下,阻焊材料15现在被图案化为阻焊环(solder mask rings,SMR)31,其为中心在凸块焊盘17上的孔环。防焊开口33形成于凸块焊盘之间,并暴露出介电层的上部表面。阻焊环31可在于凸块焊盘17上设置预焊材料27之后,使用额外的激光钻孔图案化步骤完成。
本发明另一实施例中,为在于凸块焊盘上设置预焊材料之前,以光刻工艺步骤同时定义阻焊环31及防焊开口33以形成如图1所示的阻焊环及防焊开口。此实施例中,可以光刻技术进行一工艺,同时定义阻焊环31及防焊开口33。在此方法中,在设置预焊材至凸块焊盘17上之前,已完成对于阻焊材料15的图案化。在此方法中,防焊结构可由光刻工艺形成,且接着将预焊材料经由锡膏印刷(stencil printing)印刷在阻焊材料15中。形成阻焊环31或防焊开口33的目的在于使底部填充材料涂布于集成电路管芯底下,集成电路管芯可设置在衬底11上以与介电层物理接触。此种新颖性的特征减低了本发明实施例所提供的封装体中的热机械应力,如以下所详述。
图1所示的距离D,为阻焊环31的延伸的水平厚度,且其可变化。在第一实施例中,此距离D可为铜凸块焊盘17的外部边缘至阻焊环31边缘的距离,并具有约10μm的最小距离。半导体工艺节点、集成电路上终端的数量、及凸块焊盘17的直径将随特定应用而变化,并可具有不同的合适延伸距离D。距离D虽可变化,然而,较佳为使用较小的距离D,这是因为当涂布底部填充材料时,使用厚度较小的阻焊环31可避免底部填充材料中有气泡产生。在这些实施例中,包含大于或等于约10μm的阻焊环的距离D。在其他实施例中,阻焊环的距离D可介于约10μm至20μm之间、约20μm至30μm之间、30μm至40μm之间、40μm至50μm之间,且在其他未受限制的实施例中,距离D可大于50μm。
图2显示完整的组件40的另一剖面图,此组件40包含图1的衬底11,且其已进行额外的工艺步骤来连接管芯13及底部填充材料41,例如以焊球22连接。需注意的是,如图2所示,底部填充材料41直接位于介电层16的上表面上并与其物理接触。此种结构与公知技术的组件形成鲜明的对照,公知技术的底部填充材料基本上是接触阻焊材料的上表面。相较于底部填充材料与阻焊材料之间的热系数差异,底部填充材料及介电层的热膨胀系数有较佳的匹配。在一实施例中,图2的组成40的结构,与公知技术的结构相比较,不但热效能较佳,且由热效应(thermal effects)所导致的机械应力较低。
在例如图2所示的实施例中,任何可能存在的热膨胀系数失配,相较于公知技术均已减少。在使用此种结构的实施例中,集成电路13在实用上对于降低热膨胀系数失配及所导致的机械应力的效果将极为显著。当工艺节点持续微缩,且晶片现已被薄化至可使用例如硅穿孔(TSVs),则需额外注意关于管芯翘曲的问题。本发明实施例所提供的方法及装置对于这些薄化的管芯具有特别的优势。对于小于45nm的半导体工艺节点来说,改善热应力是非常重要的。由于对于持续薄化的管芯,管芯翘曲是很需注意的问题。本发明实施例相较于公知技术提供了较佳的热效能,且降低了预焊材料破裂、底部填充材料破裂、介电层破裂、球破裂及桥接短路的发生。
图3显示本发明另一实施例,其为将多个管芯组成结合至阻焊环中。在图3中,衬底11近似于图1的衬底,阻焊材料15中具有防焊开口33。底部填充材料41涂布至每个管芯底下,且由于使用了防焊开口33,底部填充材料与介电层16的上表面相接触。虽然图3显示两个管芯依倒装芯片封装的方向设置于衬底上,如需特定应用,可设置更多管芯于衬底上。
虽然本发明已以多个较佳实施例公开如上,然其并非用以限定本发明,任何所属技术领域中普通技术人员,在不脱离本发明的精神和范围内,当可作任意的更动与润饰,因此本发明的保护范围当视后附的权利要求所界定的范围为准。
再者,本发明的范围不仅限于说明书中所揭示的特定实施例的方法及步骤。因此,任何所属技术领域中普通技术人员,在不脱离本发明的精神和范围内,当可作任意的更动与润饰。本领域普通技术人员将可依照本发明所揭示的现有或未来所发展的特定方法或步骤达成相同的功能或相同的结果。因此本发明的保护范围包含这些方法或步骤。
Claims (10)
1.一种封装装置,包括:
一封装衬底,包含:
一介电层,位于该衬底的一管芯侧表面;
多个导电焊盘,形成于该介电层的表面;及
一阻焊层,设置于该导电焊盘及该介电层上,
其中该阻焊层包含多个第一开口及多个第二开口,所述多个第一开口暴露所述多个导电焊盘,所述多个第二开口暴露介于所述多个导电焊盘之间的该介电层的表面,所述多个第二开口与所述多个导电焊盘具有至少10微米的间距。
2.如权利要求1所述的封装装置,其中所述多个第二开口与所述多个导电焊盘具有至少50微米的间距。
3.一种封装装置的制造方法,包括:
形成一介电层于一封装衬底的一管芯侧表面,其中该介电层的表面上具有多个导电凸块焊盘与该介电层中的金属导电层连接;
以一阻焊材料覆盖该介电层及所述多个导电凸块焊盘;
依照所述多个导电凸块焊盘在该阻焊材料中形成多个第一开口;以及
在所述多个导电凸块焊盘之间形成多个第二开口,所述多个第二开口延伸穿越该阻焊材料且暴露该介电层的表面。
4.如权利要求3所述的封装装置的制造方法,还包含:
设置一具有多个焊料凸块位于所述多个导电凸块焊盘上的倒装芯片集成电路;
进行一热回焊,以使所述多个焊料凸块与所述多个导电凸块焊盘电性及机械连接;及
涂布底部填充材料于该倒装芯片集成电路下方;
其中该底部填充材料与该介电层的表面具有物理接触。
5.如权利要求3所述的封装装置的制造方法,其中所述多个第一开口是经图案化以使该阻焊材料形成围绕该导电凸块焊盘的孔环。
6.如权利要求3所述的封装装置的制造方法,其中所述多个第二开口与所述多个导电凸块焊盘具有至少10微米的间距。
7.如权利要求3所述的封装装置的制造方法,其中形成该第二开口包含在该阻焊材料上进行激光钻孔。
8.一种封装装置,包括:
一封装衬底,包含:
一介电层,位于一衬底芯部的两侧上;
多个导电焊盘,形成于该介电层的表面;
至少一集成电路管芯,粘着于所述多个导电焊盘上;
一阻焊层,设置于所述多个导电焊盘及该介电层上;以及
一底部填充材料,设置于至少一集成电路管芯及该衬底之间,
其中该阻焊层包含暴露所述多个导电焊盘的第一开口;及暴露所述多个导电焊盘之间的介电层的表面的第二开口,该底部填充材料与所述多个第二开口中的该介电层的表面相接触,所述多个第二开口与所述多个导电焊盘具有至少10微米的间距。
9.如权利要求8所述的封装装置,其中所述多个第二开口与所述多个导电焊盘具有至少50微米的间距。
10.如权利要求8所述的封装装置,还包含多个集成电路管芯设置其所对应的所述多个导电焊盘中。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/852,196 | 2010-08-06 | ||
US12/852,196 US20120032337A1 (en) | 2010-08-06 | 2010-08-06 | Flip Chip Substrate Package Assembly and Process for Making Same |
Publications (1)
Publication Number | Publication Date |
---|---|
CN102376667A true CN102376667A (zh) | 2012-03-14 |
Family
ID=45555544
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2011100585204A Pending CN102376667A (zh) | 2010-08-06 | 2011-03-08 | 封装装置及其制造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US20120032337A1 (zh) |
KR (1) | KR101333801B1 (zh) |
CN (1) | CN102376667A (zh) |
TW (1) | TWI496259B (zh) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103811448A (zh) * | 2012-11-07 | 2014-05-21 | 台湾积体电路制造股份有限公司 | 弯曲轮廓的堆叠封装件接头 |
CN106973496A (zh) * | 2017-05-09 | 2017-07-21 | 上海天马微电子有限公司 | 一种柔性电路板及显示装置 |
CN108122875A (zh) * | 2016-11-28 | 2018-06-05 | 台湾积体电路制造股份有限公司 | 半导体装置 |
CN112234027A (zh) * | 2020-10-14 | 2021-01-15 | 天津津航计算技术研究所 | 一种2.5d电子封装结构 |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9137903B2 (en) * | 2010-12-21 | 2015-09-15 | Tessera, Inc. | Semiconductor chip assembly and method for making same |
US8624392B2 (en) | 2011-06-03 | 2014-01-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrical connection for chip scale packaging |
US8912668B2 (en) | 2012-03-01 | 2014-12-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrical connections for chip scale packaging |
US9548281B2 (en) | 2011-10-07 | 2017-01-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrical connection for chip scale packaging |
JP2013214568A (ja) * | 2012-03-30 | 2013-10-17 | Fujitsu Ltd | 配線基板及び配線基板の製造方法 |
US8847369B2 (en) * | 2012-07-20 | 2014-09-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging structures and methods for semiconductor devices |
US9196573B2 (en) | 2012-07-31 | 2015-11-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump on pad (BOP) bonding structure |
KR101934917B1 (ko) | 2012-08-06 | 2019-01-04 | 삼성전자주식회사 | 반도체 패키지 및 그 제조 방법 |
US9673161B2 (en) | 2012-08-17 | 2017-06-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bonded structures for package and substrate |
US8829673B2 (en) | 2012-08-17 | 2014-09-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bonded structures for package and substrate |
US9136236B2 (en) | 2012-09-28 | 2015-09-15 | Intel Corporation | Localized high density substrate routing |
US9190380B2 (en) | 2012-12-06 | 2015-11-17 | Intel Corporation | High density substrate routing in BBUL package |
US9159690B2 (en) | 2013-09-25 | 2015-10-13 | Intel Corporation | Tall solders for through-mold interconnect |
US9349703B2 (en) | 2013-09-25 | 2016-05-24 | Intel Corporation | Method for making high density substrate interconnect using inkjet printing |
KR101595216B1 (ko) * | 2014-03-14 | 2016-02-26 | 인텔 코포레이션 | 로컬화된 고밀도 기판 라우팅 |
KR102063470B1 (ko) * | 2018-05-03 | 2020-01-09 | 삼성전자주식회사 | 반도체 패키지 |
KR102658460B1 (ko) * | 2018-11-09 | 2024-04-18 | 삼성전자주식회사 | 마이크로 led 소자의 실장 구조 |
US20200211949A1 (en) * | 2018-12-26 | 2020-07-02 | Intel Corporation | Microelectronic assemblies with via-trace-via structures |
US20220069489A1 (en) * | 2020-08-28 | 2022-03-03 | Unimicron Technology Corp. | Circuit board structure and manufacturing method thereof |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040125577A1 (en) * | 2002-12-27 | 2004-07-01 | Patrizio Vinciarelli | Low loss, high density array interconnection |
CN1551338A (zh) * | 2003-05-19 | 2004-12-01 | �¹������ҵ��ʽ���� | 制造半导体封装的方法和制造半导体器件的方法 |
US20050013082A1 (en) * | 2002-12-24 | 2005-01-20 | Eiji Kawamoto | Electronic component-built-in module |
WO2006008701A2 (en) * | 2004-07-13 | 2006-01-26 | Koninklijke Philips Electronics N.V. | Assembly and method of placing the assembly on an external board |
CN101287331A (zh) * | 2007-04-10 | 2008-10-15 | 全懋精密科技股份有限公司 | 电路板电性连接垫的导电结构 |
CN101436578A (zh) * | 2007-11-14 | 2009-05-20 | 新光电气工业株式会社 | 配线基板和制造配线基板的方法 |
CN101582406A (zh) * | 2008-05-15 | 2009-11-18 | 新光电气工业株式会社 | 配线基板、配线基板的制造方法以及半导体封装件 |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6861345B2 (en) * | 1999-08-27 | 2005-03-01 | Micron Technology, Inc. | Method of disposing conductive bumps onto a semiconductor device |
US6294840B1 (en) * | 1999-11-18 | 2001-09-25 | Lsi Logic Corporation | Dual-thickness solder mask in integrated circuit package |
TW498506B (en) * | 2001-04-20 | 2002-08-11 | Advanced Semiconductor Eng | Flip-chip joint structure and the processing thereof |
US20020164836A1 (en) * | 2001-05-07 | 2002-11-07 | Advanced Semiconductor Engineering Inc. | Method of manufacturing printed circuit board |
JP3560599B2 (ja) * | 2002-04-26 | 2004-09-02 | 松下電器産業株式会社 | 電子回路装置 |
US6984545B2 (en) * | 2002-07-22 | 2006-01-10 | Micron Technology, Inc. | Methods of encapsulating selected locations of a semiconductor die assembly using a thick solder mask |
KR100463442B1 (ko) * | 2002-12-23 | 2004-12-23 | 삼성전기주식회사 | 볼 그리드 어레이 기판 및 이의 제조방법 |
TWI243462B (en) * | 2004-05-14 | 2005-11-11 | Advanced Semiconductor Eng | Semiconductor package including passive component |
US20060160346A1 (en) * | 2005-01-19 | 2006-07-20 | Intel Corporation | Substrate bump formation |
US20070148951A1 (en) * | 2005-12-27 | 2007-06-28 | Mengzhi Pang | System and method for flip chip substrate pad |
TWI307132B (en) * | 2006-03-24 | 2009-03-01 | Via Tech Inc | Chip package and fabricating method thereof |
JP4219951B2 (ja) * | 2006-10-25 | 2009-02-04 | 新光電気工業株式会社 | はんだボール搭載方法及びはんだボール搭載基板の製造方法 |
US20080182398A1 (en) * | 2007-01-30 | 2008-07-31 | Carpenter Burton J | Varied Solder Mask Opening Diameters Within a Ball Grid Array Substrate |
KR100852176B1 (ko) * | 2007-06-04 | 2008-08-13 | 삼성전자주식회사 | 인쇄회로보드 및 이를 갖는 반도체 모듈 |
KR100876899B1 (ko) * | 2007-10-10 | 2009-01-07 | 주식회사 하이닉스반도체 | 반도체 패키지 |
JP5079456B2 (ja) * | 2007-11-06 | 2012-11-21 | 新光電気工業株式会社 | 半導体装置及びその製造方法 |
JP5150518B2 (ja) * | 2008-03-25 | 2013-02-20 | パナソニック株式会社 | 半導体装置および多層配線基板ならびにそれらの製造方法 |
TWI478300B (zh) * | 2008-06-23 | 2015-03-21 | Unimicron Technology Corp | 覆晶式封裝基板及其製法 |
TW201009963A (en) * | 2008-08-18 | 2010-03-01 | Unimicron Technology Corp | Flip-chip package and method thereof |
KR20100104377A (ko) * | 2009-03-17 | 2010-09-29 | 삼성전자주식회사 | 내부 스트레스를 줄일 수 있는 반도체 패키지 |
JP5185885B2 (ja) * | 2009-05-21 | 2013-04-17 | 新光電気工業株式会社 | 配線基板および半導体装置 |
US8891246B2 (en) * | 2010-03-17 | 2014-11-18 | Intel Corporation | System-in-package using embedded-die coreless substrates, and processes of forming same |
US8686560B2 (en) * | 2010-04-07 | 2014-04-01 | Maxim Integrated Products, Inc. | Wafer-level chip-scale package device having bump assemblies configured to mitigate failures due to stress |
-
2010
- 2010-08-06 US US12/852,196 patent/US20120032337A1/en not_active Abandoned
- 2010-12-29 KR KR1020100138125A patent/KR101333801B1/ko active IP Right Grant
-
2011
- 2011-02-18 TW TW100105363A patent/TWI496259B/zh active
- 2011-03-08 CN CN2011100585204A patent/CN102376667A/zh active Pending
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050013082A1 (en) * | 2002-12-24 | 2005-01-20 | Eiji Kawamoto | Electronic component-built-in module |
US20040125577A1 (en) * | 2002-12-27 | 2004-07-01 | Patrizio Vinciarelli | Low loss, high density array interconnection |
CN1551338A (zh) * | 2003-05-19 | 2004-12-01 | �¹������ҵ��ʽ���� | 制造半导体封装的方法和制造半导体器件的方法 |
WO2006008701A2 (en) * | 2004-07-13 | 2006-01-26 | Koninklijke Philips Electronics N.V. | Assembly and method of placing the assembly on an external board |
CN101287331A (zh) * | 2007-04-10 | 2008-10-15 | 全懋精密科技股份有限公司 | 电路板电性连接垫的导电结构 |
CN101436578A (zh) * | 2007-11-14 | 2009-05-20 | 新光电气工业株式会社 | 配线基板和制造配线基板的方法 |
CN101582406A (zh) * | 2008-05-15 | 2009-11-18 | 新光电气工业株式会社 | 配线基板、配线基板的制造方法以及半导体封装件 |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103811448A (zh) * | 2012-11-07 | 2014-05-21 | 台湾积体电路制造股份有限公司 | 弯曲轮廓的堆叠封装件接头 |
CN103811448B (zh) * | 2012-11-07 | 2017-03-01 | 台湾积体电路制造股份有限公司 | 弯曲轮廓的堆叠封装件接头 |
CN108122875A (zh) * | 2016-11-28 | 2018-06-05 | 台湾积体电路制造股份有限公司 | 半导体装置 |
CN108122875B (zh) * | 2016-11-28 | 2022-12-20 | 台湾积体电路制造股份有限公司 | 半导体装置及半导体封装 |
CN106973496A (zh) * | 2017-05-09 | 2017-07-21 | 上海天马微电子有限公司 | 一种柔性电路板及显示装置 |
CN106973496B (zh) * | 2017-05-09 | 2019-06-11 | 上海天马微电子有限公司 | 一种柔性电路板及显示装置 |
CN112234027A (zh) * | 2020-10-14 | 2021-01-15 | 天津津航计算技术研究所 | 一种2.5d电子封装结构 |
Also Published As
Publication number | Publication date |
---|---|
US20120032337A1 (en) | 2012-02-09 |
TWI496259B (zh) | 2015-08-11 |
KR20120014099A (ko) | 2012-02-16 |
KR101333801B1 (ko) | 2013-11-29 |
TW201208022A (en) | 2012-02-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN102376667A (zh) | 封装装置及其制造方法 | |
CN103094244B (zh) | 嵌埋穿孔中介层的封装基板及其制法 | |
US10109608B2 (en) | Semiconductor package | |
CN104253115B (zh) | 用于半导体封装中减小的管芯到管芯间隔的底部填充材料流控制 | |
US6596560B1 (en) | Method of making wafer level packaging and chip structure | |
US20140151867A1 (en) | Semiconductor package and method for fabricating base for semiconductor package | |
CN106057769B (zh) | 用于交替的封装功能的微电子衬底 | |
US20140035095A1 (en) | Semiconductor package and method for fabricating base for semiconductor package | |
JP2007115774A (ja) | 半導体装置の製造方法 | |
TW201417235A (zh) | 封裝結構及其製法 | |
US10312210B2 (en) | Semiconductor package | |
JP2006173250A (ja) | 半導体装置およびその製造方法 | |
JP5017872B2 (ja) | 半導体装置及びその製造方法 | |
US20120153470A1 (en) | Bga package structure and method for fabricating the same | |
CN101523594A (zh) | 半导体封装和用于制造半导体封装的方法 | |
US10129980B2 (en) | Circuit board and electronic component device | |
US20060097400A1 (en) | Substrate via pad structure providing reliable connectivity in array package devices | |
JP2017011075A (ja) | 電子部品装置及びその製造方法 | |
JP2004221600A (ja) | 突出した(raised)ハンダ・ボール・パッドを備えるボール・グリッド・アレイ・パッケージ構造 | |
CN102800633A (zh) | 半导体组件结构及其制法 | |
TWI576979B (zh) | 封裝基板及其製造方法 | |
KR20210012557A (ko) | 반도체 패키지 및 이를 포함하는 반도체 모듈 | |
JP2001230537A (ja) | ハンダバンプの形成方法 | |
TWI814524B (zh) | 電子封裝件及其製法與電子結構及其製法 | |
TWI418276B (zh) | 導電凸塊無翼部的封裝基板之製法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20120314 |