CN1551338A - 制造半导体封装的方法和制造半导体器件的方法 - Google Patents
制造半导体封装的方法和制造半导体器件的方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 67
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 238000000034 method Methods 0.000 title claims description 21
- 229910000679 solder Inorganic materials 0.000 claims abstract description 134
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000010438 heat treatment Methods 0.000 claims abstract description 13
- 239000000853 adhesive Substances 0.000 claims abstract description 6
- 230000001070 adhesive effect Effects 0.000 claims abstract description 6
- 230000005496 eutectics Effects 0.000 claims description 9
- 239000011230 binding agent Substances 0.000 claims description 8
- 230000008018 melting Effects 0.000 claims description 4
- 238000002844 melting Methods 0.000 claims description 4
- 239000002184 metal Substances 0.000 abstract description 15
- 229910052751 metal Inorganic materials 0.000 abstract description 15
- 229920001721 polyimide Polymers 0.000 abstract description 13
- 239000010410 layer Substances 0.000 description 37
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 18
- 229910052802 copper Inorganic materials 0.000 description 16
- 239000010949 copper Substances 0.000 description 16
- 238000010992 reflux Methods 0.000 description 9
- 239000011229 interlayer Substances 0.000 description 8
- 238000007747 plating Methods 0.000 description 8
- 239000000126 substance Substances 0.000 description 6
- 238000005538 encapsulation Methods 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 239000009719 polyimide resin Substances 0.000 description 4
- 239000011889 copper foil Substances 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 238000009826 distribution Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 150000001879 copper Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000007766 curtain coating Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 150000002118 epoxides Chemical class 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000004382 potting Methods 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
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Abstract
一种用于制造半导体封装的方法,包括步骤:在聚酰亚胺膜(绝缘基片)的一个面上形成具有第一焊垫的第一金属布线层(第一导电图案);在聚酰亚胺膜的另一个面上形成具有第二焊垫的第四金属布线层(第二导电图案);在聚酰亚胺膜上形成第一阻焊层,第一阻焊层具有大小足以暴露第一焊垫所有侧表面的开孔;通过第一焊料凸块将半导体元件与第一焊垫电连接;将绝缘粘合剂填充入聚酰亚胺膜和半导体元件之间的间隙;和通过加热第二焊料凸块使第二焊料凸块与第二焊垫接合。
Description
技术领域
本发明涉及制造半导体封装的方法和制造半导体器件的方法。具体而言,本发明涉及用于提高半导体封装和半导体器件产出率的技术。
背景技术
最近,随着对电子器件的小型化,要求对安装在电子器件上的半导体封装进行小型化,并且在电子器件中将半导体封装高密度地安装在母板上。满足该要求的半导体封装包括,通过内部结构的革新使其外部尺寸减小至半导体元件尺寸的芯片大小封装(CSP,chip sizepackage)。
上述CSP包括多种类型。其中,类型称作球栅阵列(BGA)的半导体封装可高密度地安装在母板上,极有助于电子器件的小型化。
图1表示上述BGA类型半导体封装的放大剖面图。该封装具有,通过在绝缘基片101的两面形成第一和第二导电垫103和107所构成的插入物(interposer)110,半导体元件105通过第一焊料凸块104与第一焊垫103电连接。此外,用作该半导体封装外部连接终端的第二焊料凸块108,与存在于插入物110元件面(即,面对安装板(mountboard)的一面)上的第二焊垫107接合,上述BGA通过这些第二焊料凸块108电连接在安装板上。
通过回流第一凸块104,使第一凸块104与第一焊垫103电连接。在回流期间,为防止焊料粘附于与第一焊垫103所处相同平面的导电图案,在绝缘基片101上除第一焊垫103以外区域中形成第一阻焊层102。出于相同原因,在形成有第二焊垫107的绝缘基片101的表面形成第二阻焊层106。
在此BGA类型的半导体封装中,对于第一焊料凸块104的数量较少时的情形,半导体元件105与插入物110之间的键合强度受到削弱,半导体元件105与插入物110之间易于出现导电失效。因此,通常在半导体元件105与插入物110之间注入称作底填充树脂(underfillresin)的绝缘粘合剂109,以加强在半导体元件105与插入物110之间的键合强度。
应注意的是,在以下提及的专利文献1,2和3中,批露了上述通过焊料凸块将半导体元件电连接到插入物或安装板的技术,作为与本发明相关的技术。
(专利文献1)
日本专利公开特许公报No.Hei 11(1999)-87899
(专利文献2)
日本专利公开特许公报No.Hei 11(1999)-150206
(专利文献3)
日本专利公开特许公报No.Hei 11(1999)-297889
另外,通过回流第二焊料凸块108,使第二焊料凸块108接合在第二焊垫107上。通过此回流,第一焊料凸块104还将被加热和熔化。
此时,被融化的第一焊料凸块104的体积因热膨胀而增大,而在第一焊料凸块104周围的粘合剂109保持固态。因此,膨胀的焊料凸块104渗出到阻焊剂102与第一焊垫103之间键合强度较弱的界面。
由于焊料渗出,如图中虚线圆圈中所示,这导致在相邻第一焊料凸块104之间发生短路。因此,降低了半导体封装的产出率。
发明内容
本发明的目的在于提供一种制造半导体封装的方法和制造半导体器件的方法,其中,产出率可得到提高。
根据本发明的一个方面,提供了用于制造半导体封装的方法,包括:在绝缘基片的一个面上形成具有第一焊垫的第一导电图案;在绝缘基片的另一个面上形成具有第二焊垫的第二导电图案;在绝缘基片的一个面上形成阻焊层,阻焊层具有大小足以暴露第一焊垫所有侧表面的开孔;通过第一焊料凸块将半导体元件与第一焊垫电连接;将绝缘粘合剂填充入绝缘基片的一个面和半导体元件之间的间隙;和在填充绝缘粘合剂之后在第二焊垫上安置第二焊料凸块,并通过加热和熔化第二焊料凸块将第二焊料凸块接合在第二焊垫上。
根据本发明,所形成阻焊层的开孔具有足以暴露第一焊垫所有侧表面的尺寸。因此,第一焊垫和阻焊层不会交叠,且之间不具有交界面。因此,即使在第二焊料凸块被加热熔化时将第一焊料凸块熔化的情形中,所融化的第一焊料凸块不会渗到第一焊垫和阻焊层之间的界面。从而,能够降低因焊料渗出导致相邻第一焊料凸块之间造成短路的风险,并可提高半导体封装的产出率。
因此,本发明特别适用于当加热第二焊料凸块时第一焊料凸块完全被熔化的情形,以及将第二焊料凸块的加热温度设置成等于或高于第一焊料凸块的熔点的情形。
此外,不仅在加热第二焊料凸块的情形中,而且在对第一焊料凸块所给出的温度热历史(thermal history)等于或高于第一焊料凸块熔点的情形中,可获得同以上相似的优点。
此外,根据本发明的另一方面,提供了用于制造半导体器件的方法,该方法包括通过加热和熔化在前述半导体封装中的第二焊料凸块将第二焊料凸块电连接在安装板终端上的步骤。
根据本发明,即使在第二焊料凸块被加热熔化时将半导体封装的第一焊料凸块熔化的情形中,也能防止因上述原因造成相邻第一焊料凸块发生电短路。
在将第二焊料凸块连接至终端后通过加热所熔化的焊料将电子元件电连接在安装板上的步骤中,还可获得这样的优点。
附图说明
图1为根据已知示例的半导体封装的剖面图;
图2A至2E为按步骤顺序显示制造根据本发明实施例的半导体封装的方法的剖面图;
图3为显示制造根据本发明实施例的半导体器件的方法的剖面图;和
图4为显示在本发明实施例中回流的温度分布的曲线图。
具体实施方式
下面,将结合附图描述本发明的实施例。
图2A至2E为按步骤顺序显示制造根据本发明实施例的半导体封装的方法的剖面图。
为进行描述,将对获得如图2A所示剖面结构之前的制作步骤作以说明。
首先,通过使用激光,钻床等,在两面附着有铜箔的柔性聚酰亚胺膜(绝缘基片)1中形成通孔1a。随后,在该通孔1a的内表面和铜箔表面形成化学镀铜层。此外,在该化学镀铜层上生长电镀铜层,从而,在聚酰亚胺膜1上由铜箔和这些镀铜层制成厚度近似为35μm的铜层。此后,使该铜层形成图案,从而使余留在聚酰亚胺膜1两面的铜层形成为第二和第三级金属布线层2和3。通过处在通孔1a中的由电镀和化学镀的铜层制成的镀铜层4,将金属布线层2和3电连接。
随后,通过幕涂,在聚酰亚胺膜1的两面涂敷厚度约30μm的感光聚酰亚胺树脂,然后对感光聚酰亚胺树脂曝光,显影,和加热固化。这样,在第二级金属布线层2上形成具有第一通孔5a的第一夹层绝缘层5,在第三级金属布线层3上形成具有第二通孔6a的第二夹层绝缘层6,第一通孔5a的深度到达第二级金属布线层2,第二通孔6a的深度到达第三级金属布线层3。
应注意,除感光聚酰亚胺树脂外,绝缘层5和6还可由非感光聚酰亚胺树脂,环氧树脂等制成。在此情形中,通过将激光束施加到各个绝缘层5和6,以蒸发施加了激光束的区域中的树脂,来形成通孔5a和6a。
之后,在各绝缘层5和6的表面形成化学镀铜层。此外,使用该化学镀铜层作为籽晶层,生长电镀铜层。这样,在各个绝缘层5和6上形成由这些化学镀和电镀的铜层所构成的厚度近似为13μm的铜层。然后,将第一夹层绝缘层5上的铜层形成图案,制成第一级金属布线(第一导电图案)7,将第二夹层绝缘层6上的铜层形成图案,制成第四级金属布线(第二导电图案)8。
第一金属布线7与第二级金属布线2通过第一通孔5a电连接,且具有第一焊垫7a,第一焊垫7a用于与以后所谈到的在半导体元件上的焊料凸块接合。每个第一焊垫7a的平面形状为圆形,其直径近似为100μm。
此外,第四金属布线8与第三级金属布线3通过第二通孔6a电连接,第四金属布线8具有第二焊垫8a,第二焊垫8a以后与用作封装外部连接终端的焊料凸块接合。如同于第一焊垫7a的情形,每个第二焊垫8a的平面形状为圆形,其直径近似为400μm。
下面,将描述获得如图2B所示剖面结构之前的步骤。
首先,在第一夹层绝缘层5上涂覆由感光树脂制成的阻焊剂,对阻焊剂曝光和显影以形成第一阻焊层9,其厚度近似为23μm。第一阻焊层9具有第一开孔9a,每个第一开孔9a的形状为大小足以暴露第一焊垫7a所有侧表面的圆形。每个第一开孔9a内表面与各自第一焊垫7a侧表面之间的距离d近似为50μm。此外,每个第一开孔9a的直径近似为200μm,不过并不对其进行具体限定。
此后,使用在形成第一阻焊层9的情形中所用类似的方法,在第二夹层绝缘层6上形成厚度为33μm的第二阻焊层10。在第二阻焊层10中,形成大小足以暴露第二焊垫8a的第二开孔10a。
通过上述步骤,获得了在其两面形成有阻焊层9和10的插入物20的基本结构。
下面,将描述获得如图2C所示剖面结构之前的步骤。
首先,在半导体元件11的电极终端11a上设置低共熔(eutectic)焊料球,通过回流低共熔焊料球,使低共熔焊料球形成第一焊料凸块12。然后,将第一焊料凸块12冷却凝固后,使第一焊料凸块12与第一焊垫7a接触。在该状态,回流第一焊料凸块12在等于或高于其熔点(近似为183℃)的温度。
这样,将第一焊料凸块12熔化以浸润第一焊垫7a的表面并在其上扩展,当将焊料冷却凝固后,通过第一焊料凸块12将半导体元件11和第一焊垫7a电连接。这种连接结构也称作倒装芯片连接(flip-chipconnection)。
此外,对第一焊料凸块12的布置设计并不作具体限定。在本实施例中,在半导体元件11的电极形成表面上,以栅格形式设置五十多个第一焊料凸块12。
另外,对于具有一些(即,如上所述五十多个)第一焊料凸块12,在半导体元件11和插入物20之间的键合强度一般较弱,半导体元件11倾向于从第一焊垫7a剥落。
因此,在本实施例中,为弥补键合强度的这种不足,将环氧树脂作为绝缘粘合剂13填充入半导体元件11和第一阻焊层9之间的间隙,如图2D所示。在填充之前以及填充当时,绝缘粘合剂13为液态,填充之后,将该粘合剂加热到约为150℃将其固化。
该绝缘粘合剂13使半导体元件11不易从插入物20剥落,能够防止半导体元件11和第一焊垫7a之间连接失效。
随后,如图2E所示,在第二焊垫8a上设置由低共熔焊料制成的第二焊料凸块14,低共熔焊料与第一焊料凸块12成分相同,并通过热气加热或远红外线加热,回流第二焊料凸块14,以将其与第二焊垫8a接合。如图4所示,该回流的温度分布具有预热部分和预热部分之后的回流部分,预热部分用于在低于低共熔焊料熔点(近似为183℃)的温度,例如在120℃和140℃之间的温度,对第二焊料凸块14加热50秒至70秒。此外,在回流部分,在等于或高于低共熔焊料熔点的温度,例如最低温度为225℃且峰值温度为245℃,对第二焊料凸块14加热40秒至60秒。
注意,还可将回流前的第二焊料凸块14称作焊料球。
将通过该回流所熔化的第二焊料凸块14冷却和固化,以使其与第二焊垫8a接合。
通过上述步骤,形成根据本实施例的BGA类型半导体封装的基本结构。
根据上述实施例,当在如图2E所示步骤中回流第二焊料凸块14时,在固化的绝缘粘合剂13中,所制成与第二焊料凸块14相同材料的第一焊料凸块12也被熔化和热膨胀。但由于形成了第一阻焊剂9,以使第一阻焊剂9不与第一电极焊垫7a交叠,不存在第一阻焊剂9与第一电极焊垫7a之间键合强度较弱的界面,所熔化的第一焊料凸块12不会沿界面渗出。
由于这减少了因焊料渗出界面造成相邻焊料凸块12之间短路的风险,从而能提高半导体封装的产出率。
应注意,与第一电极焊垫7a相比,第一夹层绝缘层5具有与第一阻焊层9良好的粘附性。因此,熔化的焊料不易从第一夹层绝缘层5和第一阻焊层9之间的界面渗出。
而且,在以上描述中,考虑了在回流第二焊料凸块14期间第一焊料凸块12的渗出。不过,即使对该半导体封装给定熔化第一焊料凸块12的温度热历史的情形中,也可获得与上述相似优点。
当将上述半导体封装安装在安装板15上以产生如图3的剖面图所示半导体器件时,该热历史包括多种回流处理。
例如,为实现上述设置,在半导体封装的第二焊料凸块14与安装板15的第一终端16接触的状态中,将整个结构放置在回流环境中。通过此回流,不仅将第二焊料凸块14熔化,还将第一焊料凸块12熔化。即使当第一焊料凸块12这样被熔化,也能防止因上述原因使相邻第一焊料凸块12发生电短路。
此外,对于完成上述设置之后使用焊料19将电子元件18,诸如另一半导体封装以及片状电容器,与安装板15的第二终端17电连接的情形,用于熔化焊料19的热量(heat)也可对半导体封装施加。不过,在此情形中,也可获得与以上所述相似的优点。
可仅在安装板15的一个面,或可在其两个面安置这些电子元件18。特别是,在两面安置电子元件18的情形中,对于各个面实现两次回流处理,且每次执行各回流处理都将第一焊料凸块12熔化。因此,在此情形中,明显抑制在第一焊料凸块12之间出现短路。
尽管详细描述了本发明的实施例,但本发明并不限于上述实施例。
例如,在前面所述步骤中使用了具有柔性的聚酰亚胺膜1。不过,除此之外,还可使用刚性基片,如玻璃环氧基片。
此外,在前面描述中,在插入物20中总共形成四个布线层。不过,所层叠的布线层数目并不限于此,可形成五个或更多的布线层。在此情形中,在最上面的布线层中形成上述第一焊垫7a,在最下面的布线层中形成上述的第二焊垫8a。
此外,还可将上述本发明应用于,除半导体元件11之外,在插入物20上安置CSP的情形,在CSP中,在半导体元件上形成与半导体元件的电极相连的重布线层(rerouting layer),并在重布线层中的焊垫上形成焊料凸块。
如上所述,根据本发明,所形成阻焊层的开孔大小足以暴露第一焊垫的所有侧表面。因此,熔化的第一焊料凸块不会渗到阻焊层与第一焊垫之间的界面,能够减少在相邻第一焊料凸块之间造成短路的风险。另外,能够提高半导体封装或半导体器件的产出率。
Claims (9)
1.一种制造半导体封装的方法,包括:
在绝缘基片的一侧上形成具有第一焊垫的第一导电图案;
在绝缘基片的另一侧上形成具有第二焊垫的第二导电图案;
在绝缘基片的所述一侧上形成阻焊层,阻焊层具有大小足以暴露第一焊垫所有侧表面的开口;
通过第一焊料凸块将半导体元件与第一焊垫电连接;
将绝缘粘合剂填充入绝缘基片的所述一侧和半导体元件之间的空间;和
在填充绝缘粘合剂之后在第二焊垫上安置第二焊料凸块,并通过加热和熔化第二焊料凸块将第二焊料凸块与第二焊垫接合。
2.根据权利要求1所述的方法,其中,第二焊料凸块的加热温度等于或高于第一焊料凸块的熔点。
3.根据权利要求1所述的方法,其中,第一和第二焊料凸块由低共熔焊料制成。
4.根据权利要求1所述的方法,其中,将第二焊料凸块与第二焊垫接合后,对第一焊料凸块给出温度等于或高于第一焊料凸块熔点的热历史。
5.根据权利要求1所述的方法,其中,在绝缘基片的一侧上形成一个或多个布线层,并且其中,形成第一导电图案作为布线层的最上层。
6.根据权利要求1所述的方法,其中,在绝缘基片的另一侧上形成一个或多个布线层,并且其中,形成第二导电图案作为布线层的最下层。
7.一种制造半导体器件的方法,包括:
在绝缘基片的一侧上形成具有第一焊垫的第一导电图案;
在绝缘基片的另一侧上形成具有第二焊垫的第二导电图案;
在绝缘基片的该一侧上形成阻焊层,阻焊层具有大小足以暴露第一焊垫所有侧表面的开口;
通过第一焊料凸块将半导体元件电连接到第一焊垫上;
将绝缘粘合剂填充入绝缘基片的该一侧和半导体元件之间的空间;
在填充绝缘粘合剂之后将在第二焊料凸块安装到第二焊垫上,并通过加热和熔化第二焊料凸块将第二焊料凸块接合在第二焊垫上;和
将第二焊料凸块与第二焊垫接合后,通过加热和熔化第二焊料凸块,将第二焊料凸块与安装板的终端电连接。
8.根据权利要求7所述的方法,其中,在将第二焊料凸块电连接至安装板的终端的步骤中,第二焊料凸块的加热温度等于或高于第一焊料凸块的熔点。
9.根据权利要求7所述的方法,还包括:在将第二焊料凸块连接至终端之后,通过被加热熔化的焊料,将电子元件电连接至安装板。
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WO1999036957A1 (fr) * | 1998-01-19 | 1999-07-22 | Citizen Watch Co., Ltd. | Boitier de semiconducteur |
US6770965B2 (en) * | 2000-12-28 | 2004-08-03 | Ngk Spark Plug Co., Ltd. | Wiring substrate using embedding resin |
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-
2004
- 2004-04-30 US US10/834,975 patent/US20040235287A1/en not_active Abandoned
- 2004-05-04 TW TW093112501A patent/TW200504952A/zh unknown
- 2004-05-18 KR KR1020040035085A patent/KR20040100949A/ko not_active Application Discontinuation
- 2004-05-19 CN CNA2004100446409A patent/CN1551338A/zh active Pending
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CN102076180B (zh) * | 2009-11-20 | 2012-06-27 | 南亚电路板股份有限公司 | 电路板结构及其形成方法 |
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CN102376667A (zh) * | 2010-08-06 | 2012-03-14 | 台湾积体电路制造股份有限公司 | 封装装置及其制造方法 |
CN103972204A (zh) * | 2013-02-06 | 2014-08-06 | 矽品精密工业股份有限公司 | 封装基板、半导体封装件及其制法 |
Also Published As
Publication number | Publication date |
---|---|
US20040235287A1 (en) | 2004-11-25 |
TW200504952A (en) | 2005-02-01 |
JP2004342988A (ja) | 2004-12-02 |
KR20040100949A (ko) | 2004-12-02 |
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