KR100856609B1 - 반도체장치 및 그 제조방법 - Google Patents
반도체장치 및 그 제조방법 Download PDFInfo
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- KR100856609B1 KR100856609B1 KR20020025228A KR20020025228A KR100856609B1 KR 100856609 B1 KR100856609 B1 KR 100856609B1 KR 20020025228 A KR20020025228 A KR 20020025228A KR 20020025228 A KR20020025228 A KR 20020025228A KR 100856609 B1 KR100856609 B1 KR 100856609B1
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Semiconductor Memories (AREA)
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Abstract
Description
Claims (37)
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- 복수의 와이어들을 갖는 배선 기판으로서, 상기 기판의 주면에 형성된 상기 와이어에 전기적으로 접속된 복수의 본딩 패드들을 구비하고, 상기 본딩 패드들은 제 1 피치로 배치된 배선 기판;집적 회로 및, 주면에 형성된 복수의 제 1 단자들을 갖는 제 1 반도체 칩으로서, 상기 제 1 반도체 칩은 상기 제 1 반도체 칩의 주면이 상기 배선 기판의 주면과 대면하고, 상기 제 1 반도체 칩의 상기 제 1 단자들이 복수의 범프 전극들을 통해 상기 본딩 패드들의 제 1 세트에 접속되도록 상기 배선 기판의 주면 상에 실장되고, 상기 제 1 반도체 칩의 상기 제 1 단자들은 상기 제 1 피치에 배치되는 제 1 반도체 칩;집적 회로 및, 주면에 형성된 복수의 제 2 단자들을 갖는 제 2 반도체 칩으로서, 상기 제 2 반도체 칩은 상기 제 2 반도체 칩의 주면에 대향한 상기 제 2 반도체 칩의 배면이 상기 제 1 반도체 칩의 주면에 대향한 제 1 반도체 칩의 배면에 대향하도록 상기 제 1 반도체 칩 상에 적층되고, 상기 제 2 반도체 칩의 상기 제 2 단자들은 복수의 본딩 와이어들을 통해 본딩 패드의 제 2 세트에 전기적으로 접속되는 제 2 반도체 칩;을 구비하고,상기 제 2 반도체 칩의 제 2 단자들은 상기 제 1 피치보다 좁은 제 2 피치에 배치되고, 상기 제 1 피치는 인접 본딩 패드들과 인접 제 1 단자들의 피치이고, 상기 제 2 피치는 인접 제 2 단자들의 피치인 반도체 장치.
- 제 20 항에 있어서,상기 제 1 반도체 칩은 그 위에 형성된 메모리 소자를 구비한 칩이고, 상기 제 2 반도체 칩은 그 위에 형성된 마이크로프로세서 또는 ASIC를 갖는 칩인 반도체 장치.
- 제 20 항에 있어서,상기 제 1 반도체 칩은 그 위에 형성된 DRAM 또는 플래시 메모리를 구비한 칩인 반도체 장치.
- 제 20 항에 있어서,상기 복수의 범프 전극들은 상기 제 1 반도체 칩의 주면 상에 배열 형태로 배치된 땜납 범프들인 반도체 장치.
- 제 23 항에 있어서,상기 배선 기판의 주면 상에 형성된 상기 와어어들의 최소 피치는 0.5 mm이고, 상기 제 1 반도체 칩의 주면 상에 형성된 상기 범프 전극들의 최소 피치는 또한 0.5 mm인 반도체 장치.
- 제 20 항에 있어서,상기 복수의 범프 전극들은 제 1 반도체 칩의 본딩 패드들 상에 접속된 Au 범프들인 반도체 장치.
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- 제 20 항에 있어서,상기 주면의 대향 면에 배치된 복수의 범프 전극들을 더 포함하고,상기 복수의 범프 전극들은 상기 배선 기판의 본딩 패드들에 전기적으로 접속되는 반도체 장치.
- 제 20 항에 있어서,상기 배선 기판은 패키지 기판을 장착하기 위한 마더 보드인 반도체 장치.
- 제 20 항에 있어서,상기 제 1 및 제 2 반도체 칩들, 상기 본딩 와이어 및 상기 배선 기판의 주면을 밀봉하는 성형 수지를 더 포함하는 반도체 장치.
- 제 20 항에 있어서,상기 제 1 반도체 칩은 그 주면에 형성된 표면 패시베이션 막, 상기 패시베이션 막상에 형성된 유기 막 및 상기 유기 막상에 형성된 Cu 배선들을 포함하고, 상기 Cu 배선들은 전기 도금법으로 형성되는 반도체 장치.
- 제 30 항에 있어서,상기 제 1 반도체 칩의 상기 제 1 단자들은 상기 Cu 배선들의 제 1 단부들에 대응하고, 상기 복수의 범프 전극들은 상기 Cu 배선의 상기 제 1 단부들상에 배치되는 반도체 장치.
- (a) 복수의 배선들을 갖는 배선 기판 및 상기 배선 기판의 주면에 형성된 복수의 배선에 전기적으로 접속된 복수의 본딩 패드들을 제공하되, 제 1 반도체 칩은 집적 회로 및 그 주면에 형성된 복수의 제 1 단자들을 포함하고, 복수의 범프 전극들은 각기 복수의 제 1 단자들 상에 형성되고, 제 2 반도체 칩은 집적회로 및 그 주면에 형성된 복수의 제 2 단자들을 구비하고, 상기 배선 기판의 본딩 패드들은 제 1 피치에 배치되고, 상기 제 1 반도체 칩의 제 1 단자들 및 복수의 범프 전극들은 상기 제 1 피치에 배치되는, 본딩 패드들을 제공하는 단계;(b) 배선 기판의 주면 상에 상기 제 1 반도체 칩을 배치하되, 상기 제 1 반도체 칩의 주면이 배선 기판의 주면에 대향하도록 배치하고, 상기 제 1 반도체 칩의 복수의 제 1 단자들 및 상기 배선 기판의 복수의 본딩 패드들의 제 1 세트를 복수의 범프 전극들을 통해 전기적으로 서로 접속하는 단계;(c) 상기 제 1 반도체 칩 상에 상기 제 2 반도체 칩을 배치하되, 상기 제 2 반도체 칩의 배면이 배선 기판의 주면에 대향하도록 배치하고, 상기 제 1 반도체 칩의 복수의 제 2 단자들 및 상기 배선 기판의 본딩 패드의 제 2 세트가 복수의 본딩 와이어를 전기적으로 서로 접속하는 단계;(d) 상기 제 1 및 제 2 반도체 칩들을 수지로 밀봉하는 단계를 포함하되, 상기 제 2 반도체 칩의 상기 제 2 단자들은 상기 제 1 피치보다 좁은 제 2 피치로 배치되고, 상기 제 1 피치는 인접 본딩 패드들 및 인접 제 1 단자들의 피치이고, 상기 제 2 피치는 인접 제 2 단자들의 피치가 되도록 밀봉하는 단계를 포함하는 반도체장치의 제조 방법.
- 제 32 항에 있어서,복수의 범프 전극들은 상기 제 1 반도체 칩의 주면 상에 배열 형태로 형성된 땜납 범프들인 반도체 장치의 제조 방법.
- 제 32 항에 있어서,상기 주면에 대향하게 상기 배선 기판의 배면 상에 복수의 추가의 범프 전극들을 형성하는 단계를 더 포함하고, 상기 추가의 범프 전극들은 배선 기판의 본딩 패드들에 전기적으로 접속되는 반도체 장치의 제조 방법.
- 제 32 항에 있어서,상기 배선 기판은 패키지 기판을 실장하기 위한 마더 보드인 반도체 장치의 제조 방법.
- 제 32 항에 있어서,상기 제 1 반도체 칩은 그 주면에 형성된 표면 패시베이션 막, 상기 패시베이션 막상에 형성된 유기 막 및 상기 유기 막상에 형성된 Cu 배선들을 포함하고, 상기 Cu 배선들은 전기 도금법으로 형성되는 반도체 장치의 제조 방법.
- 제 36항에 있어서,상기 제 1 반도체 칩의 상기 제 1 단자들은 상기 Cu 배선들의 제 1 단부들에 대응하고, 상기 복수의 범프 전극들은 상기 Cu 배선의 상기 제 1 단부들상에 배치되는 반도체 장치의 제조 방법.
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KR101085244B1 (ko) * | 2003-09-30 | 2011-11-22 | 르네사스 일렉트로닉스 가부시키가이샤 | 반도체 장치의 제조 방법 |
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US20020185744A1 (en) | 2002-12-12 |
US6828174B2 (en) | 2004-12-07 |
US20030111737A1 (en) | 2003-06-19 |
TW558818B (en) | 2003-10-21 |
KR20020095061A (ko) | 2002-12-20 |
JP2002368188A (ja) | 2002-12-20 |
JP4790157B2 (ja) | 2011-10-12 |
US6841881B2 (en) | 2005-01-11 |
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