CN1738039A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN1738039A
CN1738039A CNA2005101038187A CN200510103818A CN1738039A CN 1738039 A CN1738039 A CN 1738039A CN A2005101038187 A CNA2005101038187 A CN A2005101038187A CN 200510103818 A CN200510103818 A CN 200510103818A CN 1738039 A CN1738039 A CN 1738039A
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China
Prior art keywords
solder
eutectic
electrode pad
solder layer
eutectic solder
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CNA2005101038187A
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CN100399558C (zh
Inventor
友野章
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Kioxia Corp
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Toshiba Corp
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Publication of CN1738039A publication Critical patent/CN1738039A/zh
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Abstract

一种半导体器件，包括倒装芯片焊接到电路衬底的半导体元件。利用具有焊剂功能的密封树脂，倒装芯片焊接所述半导体元件和所述电路衬底。所述半导体元件包括通过第一低熔点焊料层在第一电极焊盘上形成的焊料凸点。所述电路衬底包括对应于所述第一电极焊盘的第二电极焊盘，并且在所述第二电极焊盘上形成第二低熔点焊料层。所述焊料凸点通过所述第一和所述第二低熔点焊料层焊接到所述第一和所述第二电极焊盘。

Description

半导体器件及其制造方法
相关申请的交叉引用
本申请基于并要求2004年8月13提交的在先的日本专利申请No.2004-235850的优先权，在此引入其整个内容作为参考。
技术领域
本发明涉及应用倒装芯片焊接的半导体器件及其制造方法。
背景技术
近些年，为了处理具有增加的管脚、减小的间距和加快的信号速度的微芯片(半导体元件)，倒装芯片焊接用作具有较短的布线和连接长度的贴装技术。用于倒装芯片焊接的微芯片包括，例如，平面形成的电极焊盘和在电极焊盘上形成的焊料凸点。另一方面，其上将贴装微芯片的电路衬底具有在与微芯片的电极焊盘相对应的位置上形成的电极焊盘。倒装芯片焊接是这样一种方法，放置微芯片的电极焊盘和电路衬底的电极焊盘以使它们彼此相对，并且通过加热和熔融其间的焊料凸点，焊接微芯片的电极焊盘和电路衬底的电极焊盘。
通常，向电路衬底表面施加焊剂胶粘剂以减少焊料凸点上的氧化膜，其后在电路衬底上对准和贴装微芯片。随后，利用回流炉加热和熔融焊料凸点，以使两面的电极焊盘焊接，之后去除焊剂。然后，在电路衬底和微芯片之间填充并固化密封树脂(底部填充材料)。从而制成利用倒装芯片焊接的半导体器件。并且，对于倒装芯片焊接，具有焊剂功能的密封树脂，即所谓的非流动底部填充材料，也用于简化焊接工艺。利用具有焊剂功能的密封树脂的焊接工艺省略了清除焊剂和填充密封树脂的步骤，允许工艺简化和成本降低。
接下来，参考图12至14来说明利用具有焊剂功能的密封树脂的焊接工艺。首先，如图12所示，在微芯片1的电极焊盘2上形成由高熔点焊料，例如Sn-Ag焊料(熔点：221℃)构成的焊料凸点3。另一方面，在其上将贴装微芯片1的电路衬底4的电极焊盘5上，形成由Sn-Bi焊料(熔点：139℃)等构成的低熔点焊料层6。然后向电路衬底4上施加具有焊剂功能的密封树脂7。在此，一般地，电路衬底4在贴装区域(15至20mm的正方形)中呈现约20至50μm的翘曲。
下一步，如图13所示，通过贴装工具8吸附并保持微芯片1。在仅使低熔点焊料层6熔融的温度(例如，139℃或更高，并低于221℃)下预热贴装工具8。在对准微芯片1的电极焊盘2和电路衬底4的电极焊盘5后，将微芯片1通过密封树脂7压到电路衬底4之上。在保持该压力状态的同时，贴装工具8加热密封树脂7和低熔点焊料层6。通过加热被激活的密封树脂7的焊剂功能消除了在焊接界面的氧化膜和外来物质，而仅使低熔点焊料层6熔融，并与焊料凸点3浸湿。在这一阶段，电路衬底4通过压力平行。从而微芯片1被初步焊接到衬底4。
随后，从贴装工具8释放微芯片1。在这一阶段，施加到微芯片1上的压力被消除，使得电路衬底4回翘曲，如图14所示。在压力刚刚释放之后低熔点焊料层6仍然处于熔融状态，使得它们可以根据电路衬底4回翘曲的程度被拉开，如图15所示。随后，固化和硬化密封树脂7，导致在完成加热并熔融焊料凸点3的最后连接工艺之后，在低熔点焊料层6被拉开的部分断开。因此，对于利用具有焊剂功能的密封树脂的倒装芯片焊接工艺而言，问题是由于电路衬底4的翘曲而出现断开。
并且，为了处理微芯片的更细的间距和更高的信号速度，提出了应用铜引线以降低电阻以及低介电常数绝缘膜(低κ膜)以降低布线间电容。但是，包括低κ膜的材料通常具有机械和粘附强度低的缺点。从而，在倒装芯片焊接工艺中，由于微芯片和电路衬底之间的热膨胀系数差异引起的热应力，低κ膜本身或其界面很可能产生断裂或剥离。具体地说，无锌焊料，例如Sn-Ag焊料的利用在焊料凸点回流步骤期间引起大的热应力，由于低κ膜的低机械和粘附强度，很可能发生断裂或剥离。
另外，关于焊料凸点的结构或焊接方法已提出了多种申请。例如，日本专利特开申请号Hei 10-294337提出了由从电路衬底侧依次形成的高熔点焊料金属层、中熔点焊料金属层和低熔点焊料层构成的凸点电极结构。该结构以在电路衬底侧形成高强度高熔点的焊料金属层的方式，根据微芯片和电路衬底之间在凸点电极中的热膨胀系数的差异，允许降低热应力。这样的凸点结构有助于减小对微芯片的应力，但是对克服由于电路衬底的回翘曲引起的断开不够有效。
日本专利特开申请号Hei 10-209626提出一种方法，在由高熔点导电材料构成的支柱的两端形成焊料层，用提供对微芯片和衬底的电极焊盘的粘接的焊剂初步焊接两端上的焊料层，，以及通过熔融和固化两端的焊料层进行焊接。但是，这样的焊接方法根本不适用于具有增加的管脚数的微芯片的倒装芯片焊接。日本专利特开申请号Hei 10-12659提出了通过低熔点层将在微芯片侧设置的金属凸点和在电路衬底侧设置的高熔点焊料凸点焊接在一起的结构。在这样的焊接结构中，对克服由于电路衬底的回翘曲引起的断开不能得到满意的效果，也不能期望应力得到降低。
发明内容
因此，本发明的目的之一在于提供一种半导体器件及其制造方法，当利用具有焊剂功能的密封树脂进行倒装芯片焊接时，其能够有效抑制由于电路衬底回翘曲引起的凸点焊接部分的断开。
根据本发明的一个方面的半导体器件，包括：半导体元件，包括半导体元件本体、在所述半导体元件本体上设置的第一电极焊盘，以及在所述第一电极焊盘上形成的第一低熔点焊料层；电路衬底，包括对应于所述第一电极焊盘的第二电极焊盘，以及在所述第二电极焊盘上形成的第二低熔点焊料层；连接部分，包括在所述第一和所述第二低熔点焊料层中的一个低熔点焊料层上形成的由高熔点焊料构成的焊料凸点，并且其中所述第一和所述第二电极焊盘通过焊接到另一低熔点焊料层的所述焊料凸点连接；以及具有焊剂功能的密封树脂，填充于所述半导体元件和所述电路衬底之间，以密封所述连接部分。
根据本发明的一个方面的半导体器件制造方法，包括以下步骤：在半导体元件的第一电极焊盘上形成第一低熔点焊料层；在电路衬底的第二电极焊盘上形成第二低熔点焊料层；在所述第一和所述第二低熔点焊料层的一个上形成由高熔点焊料构成的焊料凸点；向所述半导体元件和所述电路衬底的至少一个的表面上施加具有焊剂功能的密封树脂；对准所述半导体元件的所述第一电极焊盘和所述电路衬底的所述第二电极焊盘，随后通过所述密封树脂，在所述电路衬底上对接所述半导体元件；在对所述半导体元件施加压力的同时，仅仅熔融所述第一和所述第二低熔点焊料层，并且将所述焊料凸点焊接到另一低熔点焊料层；以及释放对所述半导体元件的压力，随后固化所述密封树脂。
附图说明
虽然利用参考附图描述了本发明，但提供这些附图仅是为了说明的目的，并不以任何方式限定本发明。
图1是示出了根据本发明第一实施例的半导体器件的一般结构的图；
图2是示出了在图1中所示的半导体器件中所采用的半导体元件的一般结构的图；
图3是图2中所示的半导体元件的主要结构的截面图；
图4是在图1中所示的半导体器件中所采用的电路衬底的一般结构的图；
图5示出了制造图1中所示的半导体器件的工艺中加热和熔融低熔点焊料层的步骤；
图6示出了在图5中所示的加热和熔融步骤之后释放对半导体元件的压力的状态；
图7是图1中的半导体器件的连接部分的结构截面图，该部分被放大显示；
图8是示出了根据本发明第二实施例的半导体器件中所采用的半导体元件的结构的示意图；
图9是示出了根据本发明第二实施例的半导体器件中所采用的电路衬底的结构的示意图；
图10示出了根据本发明第二实施例加热和熔融低熔点焊料层的步骤；
图11是示出了根据本发明第二实施例的半导体器件的结构的示意图；
图12示出了传统半导体器件中所采用的半导体元件和电路衬底的例子；
图13示出了在半导体器件的传统制造工艺中加热和熔融低熔点焊料层的步骤；
图14示出了在图13中所示的加热和熔融步骤之后释放对半导体元件的压力的状态，以及传统半导体器件的结构；
图15是放大显示的图14中所示的半导体器件的连接部分的截面图。
具体实施方式
下面将参考附图详细说明本发明的实施例。虽然根据附图对本发明的实施例进行说明，应当注意，提供附图只是为了说明的目的，并不限定本
发明的范围。
图1是示出了根据本发明第一实施例的半导体器件的一般结构的截面图。图1所示的半导体器件(半导体模块)10具有所谓的倒装芯片焊接结构，其中在微芯片(半导体元件)11中设置的各第一电极焊盘12和在电路衬底13中设置的各第二电极焊盘14是电和机械焊接连接的部分，每一个包括焊料凸点15。焊料凸点15由高熔点焊料构成，并且通过低熔点焊料层16在第一电极焊盘12上形成。并且，焊料凸点15被焊接到在第二电极焊盘14上形成的第二低熔点焊料层17。也就是说，第一电极焊盘12和第二电极焊盘14通过第一低熔点焊料层16、焊料凸点15和第二低熔点焊料层17电连接。
在微芯片11和电路衬底13之间的间隙部分中，将密封树脂18作为底部填充材料填充于其中。密封树脂18通过固化处理进行硬化。利用密封树脂18，气密地密封焊料凸点15以及第一和第二电极焊盘12和14。密封树脂18具有焊剂功能，即所谓的非流动底部填充材料。例如，树脂合成物被用作具有这样的焊剂功能的密封树脂18，其中提供焊剂功能的酸酐等与环氧树脂、丙烯酸树脂、胺基树脂、有机硅树脂或聚酰亚胺树脂混合。
下面给出上述半导体器件10的细节，包括半导体器件10的制造方法。微芯片11是半导体器件10侧的元件，如图2所示，包括在其表面上形成的多个第一电极焊盘12，并且第一电极焊盘12电连接到内部电路，该内部电路没有示出。在各第一电极焊盘12上形成第一低熔点焊料层16，并且在各第一低熔点焊料层16上形成由高熔点焊料构成的焊料凸点15。例如，在预定区域中矩阵排列焊料凸点15，以处理增加的管脚数。
在此涉及的低熔点焊料和高熔点焊料满足以下条件：Mp1＜Mp2，其中Mp1是低熔点焊料的熔点，Mp2是高熔点焊料的熔点。低熔点焊料层16应具有低于构成焊料凸点15的高熔点焊料的熔点Mp2的熔点Mp1，但是实际上优选地，Mp1比高熔点焊料的Mp2低20℃或更多。满足上述条件的各种焊料金属可用作构成焊料凸点15的高熔点焊料以及第一低熔点焊料层16。这同样适用于第二低熔点焊料层17。
焊料凸点15的构成材料可以是，例如，Sn-Ag焊料合金(熔点：221℃)、Sn-Ag-Cu焊料合金(熔点：217℃)、Sn-Zn焊料合金(熔点：199℃)、Sn-Pb焊料合金(熔点：183℃)或类似材料。优选地，利用实际上不含Pb的焊料金属(无铅焊料)，因为考虑到环境负荷和对人类身体的影响，要求降低所用的铅的数量。具体地说，Sn-Ag型焊料合金(包括Sn-Ag焊料合金或Sn-Ag-Cu焊料合金)是高度实用的，适合用作焊料凸点15的材料。
第一和第二低熔点焊料层16、17由例如Sn-Bi焊料合金(熔点：139℃)、Sn-Bi-Ag焊料合金(熔点：138℃)、Sb-Zn-Bi焊料合金(熔点：190℃)、Bi-In焊料合金(熔点：72.4℃)、Bi-Pd焊料合金(熔点：126℃)、Sn-In焊料合金(熔点：118℃)、In-Ag焊料合金(熔点：144℃)等形成。列出的作为焊料凸点15的构成材料的那些焊料合金，如果它们是具有比焊料凸点15低的熔点的焊料合金，也可用于第一和第二低熔点焊料层16和17。尤其在其中，优选地利用包含Bi的Bi型焊料合金，当与构成焊料凸点15的高熔点焊料合金时，该Bi型焊料合金可提高熔点。
第一低熔点焊料层16可通过例如电镀的方法形成。也可能通过在除第一电极焊盘12之外的微芯片11的表面上形成掩膜，并且施加低熔点焊料粘合剂形成第一低熔点焊料层16。可通过例如电镀或通过利用由高熔点焊料构成的微球形成焊料凸点15。可以通过如下方法形成焊料凸点15：向第一低熔点焊料层16上施加焊剂，在其上贴装由高熔点焊料构成的微球，加热微球至低熔点焊料的熔点或更高，且低于高熔点焊料熔点的温度，仅熔融低熔点焊料层16，以及固定由高熔点焊料构成的微球。应当注意，当在施加第一熔点焊料层16的步骤之后贴装由高熔点焊料构成的微球时，可省略施加焊剂的步骤。
焊料凸点15和第一低熔点焊料层16的凸出形状没有具体指定，但优选地，凸出的高度H(焊料凸点15和第一低熔点焊料层16的总高度)在焊料凸点15的最大直径D的75％至100％的范围内。如果凸出的高度H小于焊料凸点15的最大直径D的75％，其中焊料凸点15和第一低熔点焊料层16之间的比率恒定，则第一低熔点焊料层16的体积与凸出的高度H成比例地变小，表明其使得不可能承受压力释放后电路衬底13的回翘曲。并且，当第一低熔点焊料层16的体积恒定时，焊料凸点15的体积比按比例缩小，导致通过最终熔融焊料凸点15形成的焊接合金的熔点低，并引起热循环特性、可靠性等的劣化。另一方面，如果凸出的高度H超过焊料凸点15的最大直径D的100％，在焊接工艺中密封树脂18包含空气的可能性提高，易于随之发生空隙失效(void failure)。
如图3的放大的图所示，其上形成焊料凸点15和第一低熔点焊料层16的微芯片(微芯片本体)具有电路部分，该电路部分包括铜布线21和低介电常数的绝缘膜(低κ膜)22。对于低介电常数绝缘膜22，采用例如具有3.5或更低的相对介电常数的材料。举例来说，这样的低介电常数绝缘膜22是掺氟的氧化硅膜(SiOF膜)、掺碳的氧化硅膜(SiOC膜)、有机氧化硅膜、HSQ(氢倍半硅氧烷，hydrogen silsesquioxane)膜、MSQ(甲基倍半硅氧烷，methyl silsesquioxane)膜、BCB(苯并环丁烯，benzocyclobutene)膜、PAE(聚芳基醚，polyarylether)膜、PTFE(聚四氟乙烯，polytetrafluoroethylene)膜，以及由这些材料构成的多孔膜。
在铜布线21的凸点连接部分上形成铜焊盘23，再在铜焊盘23上形成铝焊盘24。铜焊盘23和铝焊盘24的多层膜形成微芯片11的电极焊盘12。注意在图中，25代表由SiO2、Si3N4等构成的钝化膜。并且，如果需要，在铝焊盘24和第一低熔点焊料层16之间形成阻挡金属。阻挡金属层增加了铝焊盘24和第一低熔点焊料层16之间的粘附性(焊料润湿性)，并且同时防止焊料金属扩散到在微芯片11的电极材料中。利用钛膜/铜膜/镍膜结构的多层膜、钛膜/镍膜/钯膜结构的多层膜等作为阻挡金属。
如上所述的低介电常数绝缘膜22有助于降低线间电容，并由此引起更快且间距更细的信号布线，但另一方面，它具有机械强度和粘附强度低的缺点。具体地说，低介电常数绝缘膜22之间的粘附强度或低介电常数绝缘膜22与半导体衬底、金属膜、绝缘膜等之间的粘附强度为15J/m2或更小。如上所述，因为由微芯片11和电路衬底12之间的热膨胀系数的差异引起的应力等的原因，低介电常数绝缘膜22易于在膜本身或其多层界面上引起断裂或剥离。如下所述，根据本实施例的半导体器件10可有效克服由低介电常数绝缘膜22引起的断裂、剥离等。但是，应注意，微芯片11不限于在其中具有低介电常数绝缘膜22，并且自然地，也可采用不包括低介电常数绝缘膜的微芯片。
作为其上贴装微芯片11的电路衬底13，可采用由各种材料，例如树脂衬底、陶瓷衬底、玻璃衬底等构成的衬底。作为树脂衬底，采用通常采用的多层铜叠片板(多层印刷电路板)等。如图4所示，当微芯片11进行倒装芯片焊接时，电路衬底13在对应于焊料凸点15的位置具有第二电极焊盘14。与微芯片11一样，在电路衬底13的第二电极焊盘14上形成低熔点焊料层17。第二低熔点焊料层17的构成材料和形成方法与第一低熔点焊料层16相同。
在此，电路衬底13在15至20mm的正方形贴装区域(该区域包括第二电极焊盘14)中一般呈现约20至50μm的翘曲。电路衬底13的翘曲归因于生产工艺及其构成材料，一般不可避免。在焊接之前的步骤中，向该电路衬底13的表面(该表面包括电极焊盘14)施加具有焊剂功能的密封树脂18。应注意，具有焊剂功能的密封树脂18可施加到微芯片11表面，然而，优选地施加到电路衬底13的表面，以确保密封树脂18的施加量。
下面进行微芯片11和电路衬底13之间的倒装芯片焊接。首先，如图5所示，电路衬底13置于贴装台31上。同时，通过贴装工具32吸附并保持微芯片11。贴装工具32包括用于吸附并保持微芯片11的吸附孔33和用于加热微芯片11的加热装置34。将贴装工具32预热至仅仅使得低熔点焊料层16、17熔融的温度(在低熔点焊料的熔点Mp1或更高且低于高熔点焊料的熔点Mp2的温度)。接着对准微芯片11的第一电极焊盘12和电路衬底13的第二电极焊盘14，随后微芯片11通过密封树脂18压到电路衬底13上。
优选地设置各焊料凸点15、第一低熔点焊料层16，以及第二低熔点焊料层17的量，其中由高熔点焊料构成焊料凸点15，使得焊料凸点15的体积与第一和第二低熔点焊料层16、17的总体积之间的比率在4∶1至1∶1的范围内，并且第一低熔点焊料层16的体积与第二低熔点焊料层17的体积的比率在1∶1.6至1.6∶1的范围内。当由高熔点焊料构成的焊料凸点15的体积(相对于焊料层15、16和17的总和)的比率小于50％时，通过最终熔融焊料凸点15形成的焊接合金的熔点下降，并且利用半导体器件10的组件的热循环特性、可靠性等劣化。另一方面，如果焊料凸点15的体积的比率超过80％，通过第一和第二低熔点焊料层16、17，断开抑制效果和应力缓解效果劣化。并且，在第一低熔点焊料层16和第二低熔点焊料层17之间，如果一层的体积相对于另一层的体积比率超过1.6，具有较小体积的低熔点焊料层的断开抑制效果和应力缓解效果劣化。
并且，第一和第二低熔点焊料层16、17的厚度优选地分别在相对于贴装区域内的电路衬底13的翘曲量的50％至80％的范围内。当各低熔点焊料层16、17的厚度小于电路衬底13翘曲量的50％时，通过低熔点焊料层16、17对电路衬底13的回翘曲的追踪不完全。另一方面，当各低熔点焊料层16、17的厚度大于电路衬底13翘曲量的80％时，构成焊料凸点15的高熔点焊料的量成比例下降，导致利用半导体器件10的组件的热循环特性、可靠性等劣化。第一和第二低熔点焊料层16、17的总厚度优选地在贴装区域内电路衬底13翘曲量的100％至160％的范围内。
然后，在微芯片11受压并保持被压在电路衬底13上的状态的同时，加热密封树脂18及第一和第二低熔点焊料层16、17。在这一阶段，由于压力作用，电路衬底13处于平行状态。如上所述，加热温度处在仅使低熔点焊料层16、17熔融的水平，也就是说，在低熔点焊料的熔点Mp1或更高且低于高熔点焊料的熔点Mp2的温度。加热并激活的密封树脂18的焊剂功能消除了在焊接界面的氧化膜、外界物质等，并且仅仅将第一和第二低熔点焊料层16、17熔融和焊接到焊料凸点15。更具体地说，通过允许熔融的第二低熔点焊料层17与焊料凸点15的侧面润湿，将焊料凸点15和第二低熔点焊料层17焊接在一起。从而初步焊接微芯片11和电路衬底13。
应当注意，可通过利用在贴装台31侧设置的加热装置进行对密封树脂18及第一和第二低熔点焊料层16、17的加热。贴装台31侧的加热装置可与贴装工具32中设置的加热装置34同时使用。换句话说，可通过利用贴装工具32中设置的加热装置34和贴装台31中设置的加热装置中的至少一个进行对密封树脂18及第一和第二低熔点焊料层16、17的加热。
随后，如图6所示，从贴装工具32释放微芯片11。在这一阶段，由于消除了施加到微芯片11上的压力，电路衬底13回翘曲。在压力刚刚释放之后，第一和第二低熔点焊料层16、17处于熔融状态，并且如图7所示，分别拉伸，追踪电路衬底13的回翘曲。因此，第一和第二低熔点焊料层16、17的拉伸允许增加对电路衬底13回翘曲追踪的量。这可导致对压力刚刚释放之后由于电路衬底13的回翘曲引起的在凸点连接部分的断开的显著抑制。
并且，在仅仅熔融第一和第二低熔点焊料层16、17的焊接步骤(初步焊接步骤)中，由微芯片11和电路衬底13之间的热膨胀系数之间的差异引起的热应力施加在微芯片11侧。尽管在这一阶段引起的热应力很小，如果采用在其中具有机械和粘附强度低的低介电常数绝缘膜22的微芯片11，低介电常数的绝缘膜22可能引起断裂、剥离等。对于这一点，在本实施例的半导体器件10中，第一和第二低熔点焊料层16、17分别用作应力缓解层，使得能够抑制由低介电常数绝缘膜22引起的断裂、剥离等的发生。
随后，固化具有焊剂功能的密封树脂18，从而得到如图1所示的半导体器件10。在本实施例的半导体器件10中，当固化密封树脂18时，仅仅第一和第二低熔点焊料层16、17被加热、熔融，然后焊接到焊料凸点15。随着半导体器件10经过如此处理，利用在形成外部电极的焊料回流工艺期间产生的热量，熔融焊料凸点15及第一和第二低熔点焊料层16、17，并且最终焊接微芯片11和电路衬底13。在最终的焊接工艺中，热应力仍然施加在微芯片11上，但是与初步焊接工艺一样，第一和第二低熔点焊料层16、17分别用作应力缓解层，以使由低介电常数绝缘膜22引起的断裂、剥离等得到抑制。
在上述的本实施例的半导体器件10中，在焊料凸点15与第一和第二电极焊盘12、14之间分别配置低熔点焊料层16、17。因此，在利用具有焊剂功能的密封树脂18的倒装芯片焊接工艺中，即使当在刚刚释放用于焊接的压力之后，电路衬底回翘曲时，第一和第二低熔点焊料层16、17分别拉伸，追踪电路衬底13的回翘曲。这允许对由电路衬底13回翘曲引起的在凸点连接部分的断开的显著抑制。断开的抑制明显地有助于提高利用具有焊剂功能的密封树脂制造半导体器件的成品率。
并且，在初步焊接工艺(倒装芯片焊接工艺)和最终焊接工艺(熔融焊料凸点的工艺)中，第一和第二低熔点焊料层16、17用作应力缓解层。因此，即使当采用包括具有低机械和粘附强度的低介电常数绝缘膜22的微芯片11时，由低介电常数绝缘膜22引起的断裂、剥离等也可得到抑制。这使得不但能抑制无效发生的比率，还能提高在实际应用中的可靠性。具体地说，即使当焊料凸点15由具有比Sn-Pb共晶焊料高的熔点的无铅(Pb)焊料形成时，任何由低介电常数绝缘膜22引起的断裂、剥离等可得到高度可重复的抑制。
接下来，参考图8至图11说明根据本发明的第二实施例的半导体器件。在根据第二实施例的半导体器件中，在电路衬底侧形成由高熔点焊料构成的焊料凸点。如图8所示，微芯片41具有多个在其表面上形成的第一电极焊盘42，该微芯片是半导体器件侧的组成元件。在第一电极焊盘42上分别形成第一低熔点焊料层43。与上述第一实施例一样，微芯片41包括电路部分，，该电路部分包括例如铜布线和低介电常数绝缘膜。然而，电路部分的构成不限于此。
在将贴装微芯片41的电路衬底44上对应于倒装芯片焊接到微芯片41之上的第一电极42的位置上，形成第二低熔点焊料层45。在电路衬底44的第二电极焊盘45上形成低熔点焊料层46，再在其上形成由高熔点焊料构成的焊料凸点47。作为第一和第二低熔点焊料层43、46以及焊料凸点47的构成材料，采用与第一实施例类似的焊料金属。并且，各层43、46、47的形成方法和形状，以及第一和第二低熔点焊料层43、46相对于焊料凸点47的体积比率优选地与第一实施例类似。
在此，相对于15至20mm的正方形贴装区域(设置有第二电极焊盘45的区域)，电路衬底44通常呈现20至50μm的翘曲。在焊接之前的工艺期间，向电路衬底44的表面(设置有焊料凸点47的表面)施加具有焊剂功能的密封树脂48。采用与第一实施例类似的具有焊剂功能的一种材料作为密封树脂48。施加具有焊剂功能的密封树脂48，以填充通过焊料凸点47形成的凸出和凹陷。向包括焊料凸点47的电路衬底44的密封树脂的这种施加抑制了在焊接工艺期间的任何空气杂质以及由此产生的气孔。
下面进行微芯片41和电路衬底44的倒装芯片焊接。首先，如图10所示，将电路衬底44置于贴装台31上。另一方面，通过贴装工具32吸附并保持微芯片41。将贴装工具32预热至仅仅使低熔点焊料层43、46熔融的温度(低熔点焊料的熔点Mp1或更高且低于高熔点焊料的熔点Mp2的温度)。随后，对准微芯片41的第一电极焊盘42和电路衬底44的第二电极焊盘45，并且接下来通过密封树脂48将微芯片41压到电路衬底44上。
在保持微芯片41受压，并压到电路衬底44上的状态的同时，加热密封树脂48及第一和第二低熔点焊料层43、46。在这一阶段，由于压力作用，电路衬底44处于平行状态。加热温度应为仅使低熔点焊料层43、46熔融的温度。加热并激活的密封树脂48的焊剂功能消除了在焊接界面的氧化膜、外界物质等，并且将第一和第二低熔点焊料层43、46熔融和焊接到焊料凸点47。更具体地说，通过允许熔融的第一低熔点焊料层43与焊料凸点47的侧面润湿，将焊料凸点47和第一低熔点焊料层43焊接在一起。应注意，通过利用在贴装工具32中设置的加热装置34和在贴装台31侧设置的加热装置中的至少一个，进行对密封树脂48及第一和第二低熔点焊料层43、46的加热。
随后，从贴装工具32释放微芯片41。在这一阶段，由于消除了施加到微芯片41上的压力，电路衬底44回翘曲。压力刚刚释放之后第一和第二低熔点焊料层43、46处于熔融状态，并且与图7的状态类似地，分别拉伸，追踪电路衬底44的回翘曲。这允许对压力刚刚释放之后由电路衬底44的回翘曲引起的在凸点连接部分的断开的显著抑制。
此后，固化具有焊剂功能的密封树脂48，从而得到如图11所示的半导体器件50。具体地说，本发明的半导体器件50包括这样的结构(倒装芯片焊接结构)，其中通过由高熔点焊料构成的焊料凸点47以及分别连接到焊料凸点47的第一和第二低熔点焊料层43、46，将在微芯片41上设置的第一电极焊盘42和在电路衬底44上设置的第二电极焊盘45电和机械焊接在一起。利用密封树脂48作为底部填充材料填充微芯片41和电路衬底44之间的间隙部分。通过固化处理硬化密封树脂48。
第二实施例的半导体器件50处于这样的状态，其中仅仅第一和第二低熔点焊料层43、46被加热、熔融和焊接到焊料凸点47，并且密封树脂48被固化。在处于这种状态中的半导体器件50中，利用用于其后形成外部电极的焊料回流工艺中产生的热量，熔融焊料凸点47及第一和第二低熔点焊料层43、46，以致最终将微芯片41和电路衬底44焊接到一起。
在上述第二实施例的半导体器件50中，在由高熔点焊料构成的焊料凸点47与第一和第二电极焊盘42、45之间分别配置低熔点焊料层43、46。因此，在利用具有焊剂功能的密封树脂48的倒装芯片焊接工艺中，即使当在刚刚释放用于焊接的压力之后，电路衬底44回翘曲时，第一和第二低熔点焊料层43、46分别拉伸，追踪电路衬底44的回翘曲。这允许对由电路衬底44的回翘曲引起的在凸点连接部分中的断开的显著抑制。这样的断开抑制明显地有助于提高利用具有焊剂功能的密封树脂制造半导体器件的成品率。
并且，在初步焊接工艺(倒装芯片焊接工艺)和最终焊接工艺(焊料凸点熔融工艺)中，第一和第二低熔点焊料层43、46用作应力缓解层。因此，即使当采用包括具有低机械和粘附强度的低介电常数绝缘膜的微芯片41时，由低介电常数绝缘膜引起断裂、剥离等也可得到抑制。这使得能够在半导体器件50的制造过程中降低无效发生的比率，并且同时提高在实际应用中的可靠性。具体地说，即使当焊料凸点47由具有比Sn-Pb共晶焊料高的熔点的无铅(Pb)焊料形成时，任何由低介电常数绝缘膜引起的断裂、剥离等可得到高度可重复的抑制。
应当注意，本发明并不限于在此结合图示说明的具体实施例，并且可用于利用具有焊剂功能的密封树脂进行倒装芯片焊接的各种半导体器件及其制造方法。在下面权利要求书的范围内的所有修改，以及参考上面的半导体器件及其制造方法，都视为包括在本发明中。

Claims (15)

1.一种半导体器件，包括：
半导体元件，包括半导体元件本体、在所述半导体元件本体上设置的第一电极焊盘，以及在所述第一电极焊盘上形成的第一低熔点焊料层；
电路衬底，包括对应于所述第一电极焊盘的第二电极焊盘，以及在所述第二电极焊盘上形成的第二低熔点焊料层；
连接部分，包括在低熔点焊料层上形成的由高熔点焊料构成的焊料凸点，所述低熔点焊料层选自所述第一和所述第二低熔点焊料层的一个，并且其中所述第一和所述第二电极焊盘通过焊接到另一低熔点焊料层的所述焊料凸点连接；以及
密封树脂，填充于所述半导体元件和所述电路衬底之间，以密封所述连接部分，并且具有焊剂功能。
2.根据权利要求1的半导体器件，其中所述半导体元件包括具有3.5或更低的相对介电常数的低介电常数绝缘膜。
3.根据权利要求2的半导体器件，其中所述低介电常数绝缘膜相对于选自半导体衬底、金属膜以及形成所述半导体元件的绝缘膜之一具有15J/m2或更低的粘附强度。
4.根据权利要求1的半导体器件，其中所述焊料凸点由选自锡-银(Sn-Ag)焊料合金、锡-银-铜(Sn-Ag-Cu)焊料合金、锡-锌(Sn-Zn)焊料合金以及锡-铅(Sn-Pb)焊料合金之一形成。
5.根据权利要求4的半导体器件，其中所述焊料凸点由实质上不包括铅的焊料合金构成。
6.根据权利要求1的半导体器件，其中所述第一和所述第二低熔点焊料层由选自锡-铋(Sn-Bi)焊料合金、锡-铋-银(Sn-Bi-Ag)焊料合金、锡-锌-铋(Sn-Zn-Bi)焊料合金、铋-铟(Bi-In)焊料合金、铋-钯(Bi-Pd)焊料合金、锡-铟(Sn-In)焊料合金以及铟-银(In-Ag)焊料合金之一形成。
7.根据权利要求6的半导体器件，其中所述第一和所述第二低熔点焊料层由包括铋的焊料合金形成。
8.根据权利要求1的半导体器件，其中所述焊料凸点的体积与所述第一和所述第二低熔点焊料层的总体积的比率在4∶1至1∶1的范围内，并且所述第一低熔点焊料层和所述第二低熔点焊料层的体积之间的比率在1∶1.6至1.6∶1的范围内。
9.根据权利要求1的半导体器件，其中所述第一和所述第二低熔点焊料层分别具有相对于所述电路衬底的贴装区域中的翘曲量的50％至80％范围内的厚度。
10.根据权利要求1的半导体器件，其中由所述焊料凸点和所述一个低熔点焊料层形成的凸出具有相对于所述焊料凸点的最大直径的75％至100％范围内的高度。
11.一种半导体器件制造方法，包括以下步骤：
在半导体元件的第一电极焊盘上形成第一低熔点焊料层；
在电路衬底的第二电极焊盘上形成第二低熔点焊料层；
在选自所述第一和所述第二低熔点焊料层的一个低熔点焊料层上形成由高熔点焊料构成的焊料凸点；
向选自所述半导体元件和所述电路衬底的至少一个的表面上施加具有焊剂功能的密封树脂；
对准所述半导体元件的所述第一电极焊盘和所述电路衬底的所述第二电极焊盘，随后通过所述密封树脂，在所述电路衬底上对接所述半导体元件；
通过在所述半导体元件上施加压力，仅仅熔融所述第一和所述第二低熔点焊料层，并且焊接所述焊料凸点和选自所述第一和所述第二低熔点焊料层的另一低熔点焊料层；以及
释放在所述半导体元件上的压力并固化所述密封树脂。
12.根据权利要求11的半导体器件制造方法，还包括：
在固化所述密封树脂后，熔融所述第一和所述第二低熔点焊料层以及所述焊料凸点，并焊接所述第一电极焊盘和所述第二电极焊盘。
13.根据权利要求11的半导体器件制造方法，其中利用在选自保持所述半导体元件的贴装工具和放置所述电路衬底的贴装台之间的至少一个中设置的加热装置熔融所述第一和所述第二低熔点焊料层。
14.根据权利要求11的半导体器件制造方法，其中所述半导体元件包括具有3.5或更低的相对介电常数的低介电常数绝缘膜。
15.根据权利要求11的半导体器件制造方法，其中所述焊料凸点由选自锡-银(Sn-Ag)焊料合金、锡-银-铜(Sn-Ag-Cu)焊料合金、锡-锌(Sn-Zn)焊料合金以及锡-铅(Sn-Pb)焊料合金之一形成，并且所述第一和所述第二低熔点焊料层由选自锡-铋(Sn-Bi)焊料合金、锡-铋-银(Sn-Bi-Ag)焊料合金、锡-锌-铋(Sn-Zn-Bi)焊料合金、铋-铟(Bi-In)焊料合金、铋-钯(Bi-Pd)焊料合金、锡-铟(Sn-In)焊料合金以及铟-银(In-Ag)焊料合金之一形成。
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