TW200417026A - Method for forming rod-shaped semiconductor layer, and rod-shaped semiconductor device and method of fabricating the same - Google Patents

Method for forming rod-shaped semiconductor layer, and rod-shaped semiconductor device and method of fabricating the same Download PDF

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TW200417026A
TW200417026A TW092122206A TW92122206A TW200417026A TW 200417026 A TW200417026 A TW 200417026A TW 092122206 A TW092122206 A TW 092122206A TW 92122206 A TW92122206 A TW 92122206A TW 200417026 A TW200417026 A TW 200417026A
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shaped semiconductor
rod
item
scope
patent application
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TW092122206A
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TWI222222B (en
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Hao-Yu Chen
Yee-Chia Yeo
Fu-Liang Yang
Chen-Ming Hu
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Taiwan Semiconductor Mfg
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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
    • H01L29/7854—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection with rounded corners
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET

Description

200417026 五、發明說明（l) 發明所屬之技術領域 本發明係有關於一種半導體製程技術，且特別有關於 一種向性能的棍形半導體元件及其製造方法，其係形成於 一具有奈米尺寸之棍形半導體層上，具有較佳之閘極控制 能力，特別適合應用在深次微米以下的CMOS元件。 先前技術 為了 k而金氧半導體场效應電晶體（1116131-0\丨(16- semiconductor field effect transistors ;M0SFET)的
操作效能，傳統常見的方法為縮小金氧半導體場效應電晶 體的尺寸，如此除了可改善元件的操作效能外，還能同時讀I 提高元件的密度和降低製造成本。然而，由於傳統塊金氧 半導體場效應電晶體（bulk M0SFET)之閘極長度（gate 1 ength )的縮小，便容易由於源極與汲極與其間之通道相 互作用，而影響了閘極對於其通道之開啟/關閉狀態的控 制能力，而進一步引起之所謂之短通道效應（sh〇U channel ef fects ; SCE )。 為了抑制所衍生之短通道效應的問題，傳統上，解決 的有增加主體摻雜濃度、降低閘極氧化層的厚度、以 及超淺源極/汲極接合面（ultra-shall〇w source/drain φ junction)等。 决醢：f極長度縮小至奈米尺寸時，用上述傳統的方法 A m二統塊金氧半導體場效應電晶體的短通道問題是相
200417026 五、發明說明（2) 於美國專利第634241 0號案中，Bin Yu揭露了 _種形 成於絕緣層上有半導體（SOI)基底上之金氧半導體場效應 電晶體及其製造方法。美國專利第6342410號案中所揭露 之金氧半導體場效應電晶體，其閘極結構係包覆一半導體 柱（semiconductor pillar)之三表面上。具有如此閘極結 構之金氧半導體場效應電晶體可表現出對於閘通道之較佳 控制能力，可將常見習知之短通道效應（SCE)減至最低並
具有速度上之較佳表現，固可更將緊體金氧半導體場效肩 電晶體之尺寸縮小至數十奈米之程度，有利於縮小元件只 寸並降低其内短通道效應發生之可能性。此外，由於其省 氧半導體場效應電晶體係設置於一絕緣層上有半導體、 (S0 I)之基底上，可更避免接合電容的產生以增強場效麻 電晶體操作速度上之表現。 ~ 發明内容 ^ 本發明的主要目的就是提供一種具有較佳閘通道控 能力以及具有較小尺寸之半導體元件及其製作方法。工 為達上述目的，本發明提供了一種棍形半導體元件， 其結構包括： 一棍形（rod-shaped)半 以及一閘極導電層，覆蓋於 懸置棍形半導體層表面，且 半導體層間更設置有一閘極 半導體層之閘極結構。 導體層，懸置於一絕緣層上； 部份絕緣層上並環繞部份上述 閘極導電層與其所環繞之棍^ 介電層’以構成一環繞於棍形
Ζ,νν^Ι Ι\)ΔΌ 五、發明說明（3) 此外上述棍形半導0开杜语 分別位於該閘極沾 更包括兩源極/沒極區， 極電晶體。 兩側之棍形半導體層内，以構成一閘 此外’本發明亦提 導體層之方法，包括·八 7成上述棍形（rod-shaped)半 k供路出於一絕緣JS μ々 island);以及對兮主€ 一半導體島（sem i conductor τ 〇亥半導體島進行_ 述半導體島之材料；^子# Μ π丁 口火私序，使組成上 (rod-shaped)半導體層。 #成棍形 簡吕之’採用上述方法形成再 體層的棍形半導體亓杜夕制从+之棍形（rod —shaPed)半導 丁今篮tl件之製作方法句 提供露出於一绍妗^ β lsla⑷；對上述半f體層島上進V半導體島（se—咖 體島之材料原子ΛζΥ/構序d ΐ組成半導 緣芦上方.开Q Ϊ :ΐ 棍形半導體層懸置於絕 4增上万，形成一閘極介電層環 導辦厗，日14- pq . 口 F刀之上返懸置棍形半 介電層並未與絕緣層接㈤；以及形成： 閘極v電層環繞於閘極介電層上 成 Λ、 卢μ从匕 復盍於纟巴緣層上，以槿 成一 ％L、％於棍形半導體層之閘極結構。 再者，上述回火程序係於下述條件下所進行： (a) ··回火溫度介於6〇〇〜i2〇(TC ; 時 (b) ··回火時間約2秒至2小時，較佳為1〇秒至 (c) :環境壓力約於10-9〜800托（T〇rr)， ΙΟ—3 〜800 托（T0rr); 馬
200417026 五、發明說明（4) (d):於含氫氣之製程氣氛下進行，並可選擇性地加 入如氮氣、氬氣或兩者之混合氣體。在此，氫氣之流量較 佳地介於0· 01〜lOOOsccm，而氮氣之流量較佳地介於 0 · 0 1〜1 0 0 0 s c c m，而氩氣之流量則較佳地介於 0.01〜lOOOsccm 〇 由於本發明之棍形半導體元件結構，具有完全環繞於 閘通道周圍之全繞式閘極結構（Gate al 1 arouncO， 閘通道之控制能力及閘極開關速度上有較佳表現，有助_ 解決習知之短通道效應（S C E )及因汲極電壓所造成之能障 降低效應（DIBL)等問題。 此外，本發明之棍形半導體元件之製造方法，有利於 元件尺寸的縮小化並防止其短通道效應發生之可能性。' 再者，由於本發明之棍形半導體元件係設置於一絶緣 層上有半導體（S0I)之基底上，可更避免接合電容的產生$ 而增強如此之棍形半導體元件於操作速度上表現。 為讓本發明之上述目的、特徵和優點能更明顯易懂， 下文特舉較佳實施例，並配合所附圖式，作詳細說明如 下： 實施方式 本發明將配合剖面圖第1 A圖至弟1 G圖說明本發明之汽 形半導體元件的製作流程’並配合俯視圖第2A圖至第2D圖 以輔助說明其相對應厶俯視情形。 首先如第1 A圖所齐’其顯示本發明之起始步驟’在該
200417026 五、發明說明（5) 圖中，首先提供一基底，例如為一絕緣層上有半導體層 (semiconductor on insulator ;S0I)之基底，在此則以 一絕緣層102上有矽層104之矽基底1〇{)為例。絕緣層1〇2之 材質可選自於二氧化矽、氮化矽或氧化鋁等材料，在此絕 緣層102之材質以二氧化石夕為說明，其厚度介於1〇1〇〇〇〇 埃，較佳地介於500〜2000埃。而矽層1〇4之材質除選自於 =材料之外，亦可選自於矽鍺材料以及如砷化鎵（GaAs)或 W 化銦（InP)等化合物半導體（c〇mp〇und semic〇nduct〇r) 材料，，厚度介於2〜1 000埃，較佳地為介於2〇〜1〇〇〇埃。 接著’於石夕層104上依序形成—氧化層以及一罩幕 層。在此，氧化層例如為利用熱氧化 〇X1d=lon)所形成之二氧化矽（以％)材料’而罩幕層則例 如為利用化學氣相沉積法⑽）所形成之氮化石夕材料 層= = =:微影/餘刻料(未顯示)“於罩幕 "^ 2義出70件之主動區域圖案11。並留下具有 型之罩幕觀及氧化層·，i 圖案110所覆蓋之石夕層ι〇4部分。 此~，弟1 A圖中剖面結構俜 A]，切線内之剖面情形，而於：俯視圖第2A圖中 所示，於石夕層m 形成有主二；視情形則如第2A圖中 购。在此，主動區域；=。動;^圖案11◦之罩幕層 行於第2A圖内之γ方向）延伸0 了一更^分為沿第一方向（平 向（平行於第2A圖内之X方向)/;圖案112以及沿第二方 成。 人万向）延伸之兩第二圖案114所構
200417026 五、發明說明（6) 清參照第1 B圖，接著’藉由一蝕刻程序（未頬 動λ域圖案n〇所覆蓋之石夕層m。接著更經由-锨衫/蝕刻程序（未顯示）以去除主動區域圖案1 10内之第一 圖案112部份内之罩幕層108a及氧化層1063 ,以露且 此第：：案U2外…島(Slllc〇n⑷蝴“:出= I於先刖主動區域圖案110之第二圖案114下方未去除的| 幕層1 08b及氧化層（未顯示）。 ”、 A〜由第1B圖中之剖面結構係對應於上視圖第2B圖内 ” 、，友中之剖面情形，其上視結構如第2Β圖中所示，於 之上顯現出具有第二圖案114之兩罩幕層1〇8b以及 夕島1G4a，其中切島1043具有介於1 : 卜50 ·1之長寬比（L/w rati〇)。 請參照第1 C圖，接著對矽島丨〇 4進 使石夕島购内之組成原子(在此為石夕原子;遷；火私序116 二7:二而而重捲新：列’且重新排列後之組成原子為消 ^表面張力而捲肖’並於回火程序116結束後形成沿第 芦104向(如，第Γ，圖内”向）沿伸之一棍形(Γ〇ά - Shaped)石夕 I 1 P ^ ^棍形矽層104c之橫截面較佳地如第1D圖至 圓幵^第化之方形（第id圖）' 印形（第1或 小於65太半Γ ?截面之轴長⑴或直徑（D)較佳地為 不'、η"1 )，以提供較佳之元件表現。接著更蝕列去 ί Γ未形 曰圖不）去除“見第仏圖），卩露出具 114之矽層104b。 不 口系
200417026
上述回火程序1 1 6為本發明之關鍵步驟，可利用_般 蠢晶反應機台或常壓或低壓之爐管機台所完成，其製程條 件詳述如下： U (a) :回火溫度介於600〜120(TC ; (b) :回火時間約2秒至2小時，較佳為10秒〜丨小時； (c) :環境壓力約於1〇-9〜80 0托（T〇rr)，較佳為 ’ 10-3 〜80 0 托（Torr); (d) ·於含氫氣之製程氣氛下進行，並可選擇性地加 入如氮氣、氬氣或兩者之混合氣體。在此，氫氣之流量較 佳地介於0· 01〜100〇sccm，而氮氣之流量較佳地介於 0. 0 1〜1 OOOsccm，而氬氣之流量則較佳地介於 0.01 〜lOOOsccm 〇 ，此時，第1G圖巾之剖面結構係對應於±視圖第％圖内 A〜A切線中之剖面情形，其上視結構如第2β圖中所示， 絕緣層1 02上顯現出一棍形矽層丨〇4c及其兩側延伸自棍开/ 矽層104c由矽層l〇4b構成之兩擴大部。 '乂 請參照第1G圖，接著進行一餘刻程序（未顯示），以 述棍形矽層104c及其鄰近之矽層1〇413為蝕刻罩
刻絕緣層1 G2以降低其厚度，上述#刻程序之方法例如77 濕钱刻法。並於上述#刻程序結束後，於棍形⑼1〇4二 圖中），亚路出矽層l〇4b間之棍形矽層1〇4c底 彳 曰102接觸面，進而使得棍形矽層1〇4c懸置-σ 門 之絕緣層102上方。 7層1〇40間
200417026
—接著更採用傳統的薄膜沉積及微影/蝕刻等程序，以 定義出严繞於棍形矽層104c部份區域内表面之閘極介電層 If 〇及％繞於閘極介電層丨2 〇之閘極導電層〗2 2。在此閘極 導電層1 22除了環繞於閘極介電層丨2〇表面外，更沿一第二 方向（詳見第2D圖）延伸並覆蓋於絕緣層丨〇2上。接著更利 S習知之源極/汲極離子植入程序（未顯示），於未為閘極 導電層1 22覆蓋兩側之棍狀矽層丨〇4c部份及其兩側延伸自 棍形矽層104c由矽層i〇4b構成之兩擴大部内分別形成源極 /汲極區1 24，以構成具有環繞於一棍形半導體閘極結構之 閘極電晶體，即為本發明之棍形半導體元件。 在此上述環繞於部份棍形石夕層1 〇 4 c之閘極介電声 12(^气材質除可選自於一般如二氧化矽（siHc〇n心…曰⑷ 或II氧化矽（oxynitride)之介電材料材料外，亦可自選自 於如氧化锆（Zr02)、氧化铪（Hf〇2)、五氧化二鈕（Ta2〇5)、 氧化鈦（Ti〇2)以及氧化鋁（Al2〇3)等相對電容率（relative permittivity)大於5之高介電常數材料（high k dielectric)。此環繞於部份棍形矽層1〇4(：之閘極介電層 120之形成方法則可為濺鍍法、熱氧化法（thermai 曰
oxidation)或化學氣相沉積法（CVD)，其中較佳之方法為 衍生自化學氣相沉積法之原子層化學氣相沉積法（ALCVD) 或熱氧化法’其厚度則介於6〜1 〇 〇埃。而上述閘極導電層 122則選自於如為複晶矽（polysilic〇n)、複晶矽鍺 (poly-SiGe)、金屬或金屬氮化物等材質，其形成方法則 例如為電漿加強型化學氣相沉積法（PECVD)或濺鍍法，其
200417026 五、發明說明（9) 厚度約介於12〜100埃。 A ^日寺於第1 G圖中之剖面結構係對應於俯視圖第2 D圖 内A〜A七刀線中之剖面情形，其俯視結構則如第2〇圖中所 =f:極V電層1 2 2沿—第二方向延伸且覆蓋於絕緣層工〇 2 上，此第二方向大體垂直於先前棍形矽層i〇4c所沿伸之第 一方向。 於本發明中，除了提出了 一種製作棍形外觀之半導體 方法外’亦提供了-種使用此棍形半導體層之棍形半 導肢元件結構及其製作方法。 明參照第3圖，係顯示本發明之棍形半導體元件之立 體結構。在此，此元件之閘極導電層122及閘極介電層12〇 係完全環繞於一棍形半導體層（為閘極介電層12〇所完胃全 繞之棍形石夕層104c，未顯示）之部份區域上，而其所完全 環繞之部分即為問通道所在位置。一對源極/汲極區丨24， 分別形成於閘極導電層1 2 2兩側先前之棍狀矽層部份及石夕 層内，以構成具有環繞於一棍形半導體閘極結構之閘極 晶體，即為本發明之棍形半導體元件。 * a 相較於美國專利第634241 0號案所揭露之金氧半導體 場效應電晶體’本發明閘極電晶體具有完全環繞於閘通、首 周圍之全繞式閘極結構（Gate al 1 around)，相較於美國1〜 專利第63424 1 0號案内所揭露之包覆於一半導體柱' (semi conductor pi 1 lar)之三表面之閘極結構的金氧半 體場效應電晶體（M0SFET)以及習知之塊狀金氧半導體尸六 應電晶體（BULK M0SFET)，對於閘通道之控制能力及閑
0503-8978TWf(N1);TSMC2002-0896;s hawn.p t d 200417026 五、發明說明（ίο) 開關速度上有較佳表現，且對於習知之短通道效應（SCE) 及因沒極電壓所造成之能障降低效應（DIBL)可減至最低， 極有利於縮小元件尺寸並降低其内短通道效應發生之可能 性0 此外’由於本發明之棍形半導體元件係設置於一絕缘 層上有半導體（SOI)之基底上，可更避免接合電容的產 而增強如此之棍形半導體元件於操作速度上表電：。的產t
雖然本發明已以較佳實施例揭露如上，然豆並 限定本發明’任何熟習此技藝者，在不脫離本發明 和範圍内’當可作各種之更動與潤飾’因此本發 ：:’ 範圍當視後附之申請專利範圍所界定者為準。 保4
200417026 圖式簡單說明 第1A〜1 G圖為一系列剖面圖，用以說明本發明中形成 棍形半導體層之方法以及棍形半導體元件之製造方法。 第2A〜2D圖為一系列俯視圖，用以說明本發明中形成 棍形半導體層之方法以及棍形半導體元件之製造方法' 第3圖為一立體圖，用以說明本發明之棍形半導體元 件之立體結構。 相關符號說明 1 0 2〜絕緣層； 1 0 4 a〜石夕島； I 06a〜氧化層； II 0〜主動區域圖案； 11 4〜第二圖案； 1 2 0〜閘極介電層； 1 2 4〜源極/沒極區； D〜直徑； W〜秒島寬度。 I 〇 〇〜矽基底； 104、l〇4b〜石夕層； 104c〜棍形石夕層； 108a、l〇8b〜罩幕層 II 2〜第一圖案； 11 6〜回火程序； 1 2 2〜閘極導電層； X〜軸長； L〜矽島長度；

Claims (1)

  1. 200417026
    申請專利範圍 1 ·—種棍形半導體元件，包括： 以及 棍形（rod-shaped)半導體層，懸置於〜 ^ 、〜絕緣層上； —閘極導電層，覆蓋於該絕緣 之棍形半篆雜a^ 上並％繞部々乂 #募系$ -ψ. ^ —體層表面，且遠閘極導電層盥Α 4心置 形+導體層^言史置有—閘極介電/與其所王裏繞之該棍 形半導體層之閘極結構。 層’以構成—環繞於棍 2.如申請專利範圍第^項所述之 中S:棍形半導體層係沿-第一方向延半導體元件，其 係。$ 一方向延伸，且該第一大& 而°亥閘極導電層 向。 $向大體正交於該第二方 3·如申請專利範圍第1項所 其 中該閘極介電層係環繞於部份該之+昆形半導體元件， 其 4·如申請專利範圍第i項所/半導體層之表面 中該棍形半導體層之材質為矽欲棍形半導體元件， 5·如申請專利範圍第丨項所、材料。 其 中該棍形半導體層之材質為化棍形半導體元件， 6·如申請專利範圍第i項σ半導體材料。 中該棍形半導體層具有為卵形、'之棍形半導體元件，其 面。 ^圓形或圓角化方形之橫截 7·如申請專利範圍第6項所、十、 中該橫截面具有一少於65奈来’'之棍形半導體元件，其 8 ·如申請專利範圍第j項、戶nm)之軸長或直徑。 中該閘極介電層之材質為二^所述之棍形半導體元件，其 化石夕（silicon dioxide)或
    200417026
    六、申請專利範圍 氮氧化石夕（oxynitride)。 9 ·如申請專利範圍第1項所述之棍形半導體元件，其 中該閘極介電層材質為相對電容率（relative 八 permittivity)大於5之介電材料。 1 0.如申請專利範圍第9項所述之棍形半導體元件，1 中該相對電容率大於5之材質為五氧化二鈕（Τ\〇5)、氧化、 铪（Hf〇2)、氧化鍅（Zr〇2)、氧化鈦（Ti〇2)或氧化鋁 (A 12 03 ) 〇 導體元件，其 金屬或金屬氮1 11 ·如申請專利範圍第1項所述之棍形半 中該閘極導電層材質為複晶矽、複晶矽鍺、 化物。 1 2 ·如申請專利範圍第1項所述之棍形半導體元件，其 中更包括兩源極/汲極區，分別位於該閘極結構兩側之該、 棍形半導體層内，以構成一閘極電晶體。 1 3 ·如申請專利範圍第1 2項所述之棍形半導體元件， 其中該等源極/汲極區更包括分別連接於該棍形半導體層 且延伸自該棍形半導體層之一擴大部。 " 1 4·如申請專利範圍第1項所述之棍形半導體元件，其 中該絕緣層之材質為二氧化矽。 /、 1 5·如申請專利範圍第1項所述之棍形半導體元件，其 中该絕緣層係設置於一石夕基材上。 1 6 · —種形成棍形半導體層之方法，包括·· 提供位於一絕緣層上之一半導體島（semi conductor island)；以及
    0503-8978m(Nl) ；TSMC2002^0896;shawn.ptd 第18頁 200417026
    對該半導體島進行一回火程序，使組成該半導體 材料原子重新排列以構成一棍形（r〇d_shaped)半導體層。 1 7·如申請專利範圍第丨6項所述之形成棍形半導體曰声 之方法，其中該半導體島具有介於2〜1〇〇〇埃之厚度。曰 18·如申請專利範圍第17項所述之形成棍形半&導體芦 之方法，其中該半導體島具有介於1 :1〜50 :1之長寬比9 1 9·如申請專利範圍第丨6項所述之形成棍形半導體層 之方法，其中該半導體島材質為矽或矽鍺材料。 θ 20·如申請專利範圍第16項所述之形成棍形半導體層 之方法’其中該半導體島材質為化合物半導體材料。 21 ·如申請專利範圍第丨6項所述之形成棍形半導體層 之方法’其中该絕緣層之材質為二氧化妙。 一 22·如申請專利範圍第16項所述之形成棍形半導體層 之方法，其中該回火程序係於6〇〇〜1 200 °c之溫度下進行曰 2 3 ·如申請專利範圍第1 6項所述之形成棍形半導體声 之方法，其中該回火程序之回火時間介於2秒至2小時/ 24·如申請專利範圍第丨6項所述之形成棍形半導體層 之方法，其中該回火程序係於1(Γ9~800托（T0rr)之環境^ 力下進行。 ^ 2 5 ·如申請專利範圍第1 6項所述之形成棍形半導體層 之方法，其中該回火程序係於含氫氣之環境下進行。e 26·如申請專利範圍第25項所述之形成棍形半導體層 之方法，其中於該回火程序中更含有氮氣、氩氣或氮氣曰與
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    200417026
    六、申請專利範圍 氬氣之混合氣體。 2 7·如申請專利範圍第丨6項所述形成棍形半導體層之 方法，其中該棍形半導體層之橫截面為卵形、圓形或9圓角 28·如申請專利範圍第2?項所述之形成棍形半導體層 之方法，其中該橫截面具有一少於65奈米（nm)之軸長或曰直 徑0 2 9 · —種棍形半導體元件的製造方法，包括： kt、路出於一絕緣層上之一半導體島（semiconductor island); 對该半導體島進行一回火程序，使組成該半導體島之 材料原子重新排列以構成一棍形（r〇d —shaped)半導體層； 部份姓刻該絕緣層，以使該棍形半導體層懸置於該絕 緣層上； 形成一閘極介電層環繞部分之該懸置棍形半導體層， 且該閘極介電層並未與該絕緣層接觸；以及 ^ 形成一閘極導電層環繞於該閘極介電層上並覆蓋於該 系巴緣層上’以構成一環繞於棍形半導體層之閘極結構。 ^ 3 0 ·如申請專利範圍第2 9項所述之棍形半導體元件的 製造方法’其中該棍形半導體層係沿一第一方向延伸，而 該閘極導電層係沿一第二方向延伸，且該第一方向大體正 交於該第二方向。 ，3 1 ·如申請專利範圍第2 9項所述之棍形半導體元件的 製造方法’其中該半導體島為一長方形之半導體島。
    200417026 六、申請專利範圍 32·如申請專利範圍第29項所述之棍形半導體元件的 製造方法，其中該棍形半導體層之材質為矽或矽鍺材料。 33·如申請專利範圍第29項所述之棍形半導體元件的 製造方法，其中該棍形半導體層之材質為化合物半導體 料。 34·如申請專利範圍第29項所述之棍形半導體元件的 製造方法，其中該棍形半導體層之橫戴面為卵形、圓形 圓角化之方形。 35.如申請專利範圍第34項所述之棍形半導體元件的 製造方法，其中該橫截面具有一少於65奈米（nm)之軸長或 直徑。 36·如申請專利範圍第29項所述之棍形半導體元件的 製ie方法，其中戎閘極介電層之材質為二氧化石夕（s丨1丨^ ^ dioxide)或氮乳化^(Qxynitride)。 3 7 ·如申請專利範圍第2 9項所述之棍形半導體元件的 製造方法’其中該閘極介電層材質為相對電容率 (relative permittivity)大於 5 之介電材料。 38·如申請專利範圍第37項所述之棍形半導體元件的 製造方法，其中該相對電容率大於5之介電材料為五氧化 二钽（Ta2 05 )、氧化銓（Hf〇2)、氧化锆（Zr02)、氧化鈦 (Ti02)或氧化鋁（Al2〇3)。 39·如申請專利範圍第29項所述之棍形半導體元件的 衣^^方法’其中邊閘極導電層材質為複晶碎、複晶秒錯、 金屬或金屬氮化物。
    0503-8978TWf(Nl)；TSMC2002-0896;shawn.ptd 第21頁 200417026
    製造=·法如申Λ專利範圍第29項所述之棍形半導艘元件的 ’、更包括對該閘極結構兩側之該棍形半導體 ΐ 離子植入程序，以於該間極結構兩側之= =導體層内为別形成一源極/汲極區，以構成一閘極電晶 止41 ·如申請專利範圍第2 9項所述之棍形半導體元件的 製造方法，其中該絕緣層之材質為二氧化矽。 42·如申請專利範圍第29項所述之棍形半導體元件的 製造方法，其中該半導體島具有介於2〜1〇00埃之厚度。 43·如申請專利範圍第42項所述之棍形半導體元&件的 製造方法，其中該半導體島具有有介於1 :1〜5〇 :1之長 寬比（L/W ratio)。 44·如申請專利範圍第29項所述之棍形半導體元件的 製造方法，其中該回火程序係於600〜;l2〇〇t之溫度下進 行。 45. 如申請專利範圍第29項所述之棍形半導體元件的 製造方法’其中該回火程序之回火時間介於2秒至2小時。 46. 如申請專利範圍第29項所述之棍形半導體元件的 製造方法，其中該回火程序係於1()-9〜8〇〇托（T〇rr)之環境 壓力下進行。 47·如申請專利範圍第29項所述之棍形半導體元件的 製造方法，其中該回火程序係於含氫氣之環境下進行。 48·如申請專利範圍第47項所述之棍形半導體元件的 製造方法’其中於該回火程序中更含有氮氣、氬氣或氮氣
    0503-8978Wf(Nl);TSMC2002-0896;shawn.ptd 第 22 頁 200417026 六、申請專利範圍 與氬氣之混合氣體。 I « IIIHH 0503-8978TWf(N1);TSMC2002-0896;shawn.ptd 第23頁
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