SG114537A1 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
SG114537A1
SG114537A1 SG200202132A SG200202132A SG114537A1 SG 114537 A1 SG114537 A1 SG 114537A1 SG 200202132 A SG200202132 A SG 200202132A SG 200202132 A SG200202132 A SG 200202132A SG 114537 A1 SG114537 A1 SG 114537A1
Authority
SG
Singapore
Prior art keywords
semiconductor device
semiconductor
Prior art date
Application number
SG200202132A
Other languages
English (en)
Inventor
Aoki Yutaka
Original Assignee
Casio Computer Co Ltd
Oki Electric Ind Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd, Oki Electric Ind Co Ltd filed Critical Casio Computer Co Ltd
Publication of SG114537A1 publication Critical patent/SG114537A1/en

Links

Classifications

    • H—ELECTRICITY
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Waveguide Aerials (AREA)
  • Details Of Aerials (AREA)
SG200202132A 2001-04-17 2002-04-11 Semiconductor device SG114537A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001118242A JP3939504B2 (ja) 2001-04-17 2001-04-17 半導体装置並びにその製造方法および実装構造

Publications (1)

Publication Number Publication Date
SG114537A1 true SG114537A1 (en) 2005-09-28

Family

ID=18968664

Family Applications (1)

Application Number Title Priority Date Filing Date
SG200202132A SG114537A1 (en) 2001-04-17 2002-04-11 Semiconductor device

Country Status (7)

Country Link
US (1) US6639299B2 (fr)
EP (2) EP1251558A2 (fr)
JP (1) JP3939504B2 (fr)
KR (1) KR100885352B1 (fr)
CN (1) CN1320646C (fr)
SG (1) SG114537A1 (fr)
TW (1) TW544817B (fr)

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US6936531B2 (en) * 1998-12-21 2005-08-30 Megic Corporation Process of fabricating a chip structure
US6965165B2 (en) 1998-12-21 2005-11-15 Mou-Shiung Lin Top layers of metal for high performance IC's
US7381642B2 (en) 2004-09-23 2008-06-03 Megica Corporation Top layers of metal for integrated circuits
US7271489B2 (en) 2003-10-15 2007-09-18 Megica Corporation Post passivation interconnection schemes on top of the IC chips
US8158508B2 (en) 2001-03-05 2012-04-17 Megica Corporation Structure and manufacturing method of a chip scale package
JP4824228B2 (ja) * 2001-09-07 2011-11-30 株式会社リコー 半導体装置
EP1423876B1 (fr) 2001-09-07 2013-07-10 Ricoh Company, Ltd. Dispositif a semi-conducteur et regulateur de tension
US7932603B2 (en) * 2001-12-13 2011-04-26 Megica Corporation Chip structure and process for forming the same
TW584950B (en) 2001-12-31 2004-04-21 Megic Corp Chip packaging structure and process thereof
TW544882B (en) 2001-12-31 2003-08-01 Megic Corp Chip package structure and process thereof
US6673698B1 (en) 2002-01-19 2004-01-06 Megic Corporation Thin film semiconductor package utilizing a glass substrate with composite polymer/metal interconnect layers
TW503496B (en) 2001-12-31 2002-09-21 Megic Corp Chip packaging structure and manufacturing process of the same
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