MY8600554A - Semiconductor integrated circuit device and a method of manufacture thereof - Google Patents

Semiconductor integrated circuit device and a method of manufacture thereof

Info

Publication number
MY8600554A
MY8600554A MY8600554A MY8600554A MY8600554A MY 8600554 A MY8600554 A MY 8600554A MY 8600554 A MY8600554 A MY 8600554A MY 8600554 A MY8600554 A MY 8600554A MY 8600554 A MY8600554 A MY 8600554A
Authority
MY
Malaysia
Prior art keywords
integrated circuit
semiconductor integrated
circuit device
manufacture
input
Prior art date
Application number
MY8600554A
Other languages
English (en)
Inventor
Yoshikazu Takahashi
Tsuneo Itoh
Makoto Takechi
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of MY8600554A publication Critical patent/MY8600554A/xx

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    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
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    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19043Component type being a resistor

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)
MY8600554A 1981-06-22 1986-12-30 Semiconductor integrated circuit device and a method of manufacture thereof MY8600554A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9535781A JPS57211248A (en) 1981-06-22 1981-06-22 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
MY8600554A true MY8600554A (en) 1986-12-31

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Family Applications (1)

Application Number Title Priority Date Filing Date
MY8600554A MY8600554A (en) 1981-06-22 1986-12-30 Semiconductor integrated circuit device and a method of manufacture thereof

Country Status (10)

Country Link
US (1) US4893168A (it)
JP (1) JPS57211248A (it)
KR (1) KR910000155B1 (it)
DE (1) DE3223276A1 (it)
FR (1) FR2508255B1 (it)
GB (1) GB2104284B (it)
HK (1) HK54686A (it)
IT (1) IT1152980B (it)
MY (1) MY8600554A (it)
SG (1) SG20786G (it)

Families Citing this family (60)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5864047A (ja) * 1981-10-13 1983-04-16 Nec Corp マスタ−スライス半導体集積回路装置
JPS5897847A (ja) * 1981-12-08 1983-06-10 Nec Corp 集積回路装置
JPS58124263A (ja) * 1982-01-20 1983-07-23 Toshiba Corp 半導体装置
JPS58213448A (ja) * 1982-06-07 1983-12-12 Hitachi Ltd 負荷駆動方式
US4409499A (en) * 1982-06-14 1983-10-11 Standard Microsystems Corporation High-speed merged plane logic function array
JPS5941852A (ja) * 1982-06-24 1984-03-08 ストレイジ・テクノロジ−・パ−トナ−ズ 集積回路チツプ
US4870471A (en) * 1982-09-30 1989-09-26 Mitsubishi Denki Kabushiki Kaisha Complementary metal-oxide semiconductor integrated circuit device with isolation
US5281545A (en) * 1982-12-10 1994-01-25 Ricoh Company, Ltd. Processes for manufacturing a semiconductor device
JPS59139646A (ja) * 1983-01-31 1984-08-10 Hitachi Micro Comput Eng Ltd 半導体集積回路装置
KR910008521B1 (ko) * 1983-01-31 1991-10-18 가부시기가이샤 히다찌세이사꾸쇼 반도체집적회로
JPS59167122A (ja) * 1983-03-11 1984-09-20 Nec Corp 入出力バツフア−
US4568961A (en) * 1983-03-11 1986-02-04 Rca Corporation Variable geometry automated universal array
JPS607147A (ja) * 1983-06-24 1985-01-14 Mitsubishi Electric Corp 半導体装置
JPS60501881A (ja) * 1983-07-14 1985-10-31 アドバンスト・マイクロ・ディバイシズ・インコ−ポレ−テッド 専用されていない入力/出力セルを有する半導体ダイ
JPS6027145A (ja) * 1983-07-25 1985-02-12 Hitachi Ltd 半導体集積回路装置
US5276346A (en) * 1983-12-26 1994-01-04 Hitachi, Ltd. Semiconductor integrated circuit device having protective/output elements and internal circuits
US5610089A (en) * 1983-12-26 1997-03-11 Hitachi, Ltd. Method of fabrication of semiconductor integrated circuit device
JPS61111576A (ja) * 1984-10-13 1986-05-29 Fujitsu Ltd 半導体装置
JPS61218143A (ja) * 1985-03-25 1986-09-27 Hitachi Ltd 半導体集積回路装置
JPS6289341A (ja) * 1985-10-15 1987-04-23 Mitsubishi Electric Corp マスタスライス方式大規模半導体集積回路装置の製造方法
JPH0638453B2 (ja) * 1986-05-12 1994-05-18 日本電気株式会社 半導体装置
US4862197A (en) * 1986-08-28 1989-08-29 Hewlett-Packard Co. Process for manufacturing thermal ink jet printhead and integrated circuit (IC) structures produced thereby
JPS63108733A (ja) * 1986-10-24 1988-05-13 Nec Corp 半導体集積回路
JPH0758734B2 (ja) * 1987-02-23 1995-06-21 株式会社東芝 絶縁ゲ−ト型セミカスタム集積回路
US5243208A (en) * 1987-05-27 1993-09-07 Hitachi, Ltd. Semiconductor integrated circuit device having a gate array with a ram and by-pass signal lines which interconnect a logic section and I/O unit circuit of the gate array
DE68929068T2 (de) * 1988-04-22 1999-12-23 Fujitsu Ltd., Kawasaki Integrierte Halbleiterschaltungsanordnung vom "Masterslice"-Typ
JPH01289138A (ja) * 1988-05-16 1989-11-21 Toshiba Corp マスタースライス型半導体集積回路
US5162893A (en) * 1988-05-23 1992-11-10 Fujitsu Limited Semiconductor integrated circuit device with an enlarged internal logic circuit area
JPH01293647A (ja) * 1988-05-23 1989-11-27 Fujitsu Ltd 半導体装置
US5300796A (en) * 1988-06-29 1994-04-05 Hitachi, Ltd. Semiconductor device having an internal cell array region and a peripheral region surrounding the internal cell array for providing input/output basic cells
US5019889A (en) * 1988-06-29 1991-05-28 Hitachi, Ltd. Semiconductor integrated circuit device
EP0360164A3 (en) * 1988-09-20 1990-07-04 National Semiconductor Corporation Standard cell output driver connection system
US4987578A (en) * 1988-10-07 1991-01-22 Advanced Micro Devices, Inc. Mask programmable bus control gate array
JPH07111971B2 (ja) * 1989-10-11 1995-11-29 三菱電機株式会社 集積回路装置の製造方法
JPH06105709B2 (ja) * 1989-12-02 1994-12-21 東芝マイクロエレクトロニクス株式会社 半導体集積回路装置
US5216280A (en) * 1989-12-02 1993-06-01 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device having pads at periphery of semiconductor chip
JPH02223220A (ja) * 1990-01-29 1990-09-05 Hitachi Ltd 半導体集積回路装置
US4988636A (en) * 1990-01-29 1991-01-29 International Business Machines Corporation Method of making bit stack compatible input/output circuits
US5153507A (en) * 1990-11-16 1992-10-06 Vlsi Technology, Inc. Multi-purpose bond pad test die
JP2707871B2 (ja) * 1991-05-31 1998-02-04 富士ゼロックス株式会社 電子デバイス及びその製造方法
US5134094A (en) * 1991-07-22 1992-07-28 Silicon Power Corporation Single inline packaged solid state relay with high current density capability
US5220197A (en) * 1991-07-22 1993-06-15 Silicon Power Corporation Single inline packaged solid state relay with high current density capability
US6487682B2 (en) 1991-09-18 2002-11-26 Fujitsu Limited Semiconductor integrated circuit
US5341018A (en) * 1991-09-18 1994-08-23 Nec Corporation Semiconductor integrated circuit device having a plurality of input circuits each including differently sized transistors
JPH06140607A (ja) * 1992-10-28 1994-05-20 Mitsubishi Electric Corp 半導体集積回路
US5404041A (en) * 1993-03-31 1995-04-04 Texas Instruments Incorporated Source contact placement for efficient ESD/EOS protection in grounded substrate MOS integrated circuit
US5691218A (en) * 1993-07-01 1997-11-25 Lsi Logic Corporation Method of fabricating a programmable polysilicon gate array base cell structure
US5436578A (en) * 1993-07-14 1995-07-25 Hewlett-Packard Corporation CMOS output pad driver with variable drive currents ESD protection and improved leakage current behavior
US5796129A (en) * 1993-08-03 1998-08-18 Seiko Epson Corp. Master slice type integrated circuit system having block areas optimized based on function
US5552333A (en) * 1994-09-16 1996-09-03 Lsi Logic Corporation Method for designing low profile variable width input/output cells
US5760428A (en) * 1996-01-25 1998-06-02 Lsi Logic Corporation Variable width low profile gate array input/output architecture
US5698873A (en) * 1996-03-08 1997-12-16 Lsi Logic Corporation High density gate array base cell architecture
US5796638A (en) * 1996-06-24 1998-08-18 The Board Of Trustees Of The University Of Illinois Methods, apparatus and computer program products for synthesizing integrated circuits with electrostatic discharge capability and connecting ground rules faults therein
US5767565A (en) * 1996-07-22 1998-06-16 Alliance Semiconductor Corporation Semiconductor devices having cooperative mode option at assembly stage and method thereof
US5969390A (en) * 1997-07-22 1999-10-19 Zilog, Inc. Layout solution for electromagnetic interference reduction
US6114731A (en) * 1998-03-27 2000-09-05 Adaptec, Inc. Low capacitance ESD structure having a source inside a well and the bottom portion of the drain inside a substrate
US6078068A (en) * 1998-07-15 2000-06-20 Adaptec, Inc. Electrostatic discharge protection bus/die edge seal
JP3914649B2 (ja) * 1999-02-10 2007-05-16 株式会社東芝 半導体装置
JP3530450B2 (ja) * 2000-02-18 2004-05-24 Necエレクトロニクス株式会社 マクロ回路の配線方法、マクロ回路配線装置、及びマクロ回路
JP4146290B2 (ja) * 2003-06-06 2008-09-10 株式会社ルネサステクノロジ 半導体装置

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3771217A (en) * 1971-04-16 1973-11-13 Texas Instruments Inc Integrated circuit arrays utilizing discretionary wiring and method of fabricating same
US3936812A (en) * 1974-12-30 1976-02-03 Ibm Corporation Segmented parallel rail paths for input/output signals
JPS5851425B2 (ja) * 1975-08-22 1983-11-16 株式会社日立製作所 ハンドウタイソウチ
US4161662A (en) * 1976-01-22 1979-07-17 Motorola, Inc. Standardized digital logic chip
US4207556A (en) * 1976-12-14 1980-06-10 Nippon Telegraph And Telephone Public Corporation Programmable logic array arrangement
JPS60953B2 (ja) * 1977-12-30 1985-01-11 富士通株式会社 半導体集積回路装置
JPS5925381B2 (ja) * 1977-12-30 1984-06-16 富士通株式会社 半導体集積回路装置
US4249193A (en) * 1978-05-25 1981-02-03 International Business Machines Corporation LSI Semiconductor device and fabrication thereof
JPS55163859A (en) * 1979-06-07 1980-12-20 Fujitsu Ltd Manufacture of semiconductor device
JPS561545A (en) * 1979-06-15 1981-01-09 Mitsubishi Electric Corp Input/output buffer cell for semiconductor integrated circuit
JPS5631730U (it) * 1979-07-19 1981-03-27
JPS5619639A (en) * 1979-07-27 1981-02-24 Hitachi Ltd Semiconductor device
JPS5690548A (en) * 1979-11-20 1981-07-22 Fujitsu Ltd Manufacture of semiconductor device by master slice system
JPS57181152A (en) * 1981-04-30 1982-11-08 Toshiba Corp Semiconductor integrated circuit device

Also Published As

Publication number Publication date
JPH0440866B2 (it) 1992-07-06
FR2508255A1 (fr) 1982-12-24
GB2104284B (en) 1985-06-19
KR910000155B1 (ko) 1991-01-21
GB2104284A (en) 1983-03-02
US4893168A (en) 1990-01-09
JPS57211248A (en) 1982-12-25
HK54686A (en) 1986-08-01
IT1152980B (it) 1987-01-14
KR840000985A (ko) 1984-03-26
IT8221971A0 (it) 1982-06-21
FR2508255B1 (fr) 1987-12-24
SG20786G (en) 1987-03-27
DE3223276A1 (de) 1983-01-05

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