KR970052022A - 에스 오 아이 기판 제조방법 - Google Patents

에스 오 아이 기판 제조방법 Download PDF

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Publication number
KR970052022A
KR970052022A KR1019950069460A KR19950069460A KR970052022A KR 970052022 A KR970052022 A KR 970052022A KR 1019950069460 A KR1019950069460 A KR 1019950069460A KR 19950069460 A KR19950069460 A KR 19950069460A KR 970052022 A KR970052022 A KR 970052022A
Authority
KR
South Korea
Prior art keywords
film
sacrificial
layer
forming
manufacturing
Prior art date
Application number
KR1019950069460A
Other languages
English (en)
Korean (ko)
Inventor
김재갑
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950069460A priority Critical patent/KR970052022A/ko
Priority to JP8356108A priority patent/JPH1012850A/ja
Priority to GB9627000A priority patent/GB2309587B/en
Priority to TW085116216A priority patent/TW309648B/zh
Priority to DE19654697A priority patent/DE19654697A1/de
Priority to CN96123929A priority patent/CN1084524C/zh
Publication of KR970052022A publication Critical patent/KR970052022A/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26533—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically inactive species in silicon to make buried insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/78654—Monocrystalline silicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76267—Vertical isolation by silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76281—Lateral isolation by selective oxidation of silicon

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Element Separation (AREA)
KR1019950069460A 1995-12-30 1995-12-30 에스 오 아이 기판 제조방법 KR970052022A (ko)

Priority Applications (6)

Application Number Priority Date Filing Date Title
KR1019950069460A KR970052022A (ko) 1995-12-30 1995-12-30 에스 오 아이 기판 제조방법
JP8356108A JPH1012850A (ja) 1995-12-30 1996-12-25 Ｓｏｉ基板およびその製造方法
GB9627000A GB2309587B (en) 1995-12-30 1996-12-27 Silicon-on-insulator substrate and method fabricating the same
TW085116216A TW309648B (zh) 1995-12-30 1996-12-28
DE19654697A DE19654697A1 (de) 1995-12-30 1996-12-30 Substrat mit Silicium auf einem Isolator und Verfahren zu dessen Herstellung
CN96123929A CN1084524C (zh) 1995-12-30 1996-12-30 Soi基片的制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950069460A KR970052022A (ko) 1995-12-30 1995-12-30 에스 오 아이 기판 제조방법

Publications (1)

Publication Number Publication Date
KR970052022A true KR970052022A (ko) 1997-07-29

Family

ID=19448458

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950069460A KR970052022A (ko) 1995-12-30 1995-12-30 에스 오 아이 기판 제조방법

Country Status (6)

Country Link
JP (1) JPH1012850A (zh)
KR (1) KR970052022A (zh)
CN (1) CN1084524C (zh)
DE (1) DE19654697A1 (zh)
GB (1) GB2309587B (zh)
TW (1) TW309648B (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11204452A (ja) 1998-01-13 1999-07-30 Mitsubishi Electric Corp 半導体基板の処理方法および半導体基板
KR100366923B1 (ko) * 2001-02-19 2003-01-06 삼성전자 주식회사 에스오아이 기판 및 이의 제조방법
US6737332B1 (en) * 2002-03-28 2004-05-18 Advanced Micro Devices, Inc. Semiconductor device formed over a multiple thickness buried oxide layer, and methods of making same
EP1993127B1 (en) * 2007-05-18 2013-04-24 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of SOI substrate
US8119490B2 (en) * 2008-02-04 2012-02-21 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5745947A (en) * 1980-09-03 1982-03-16 Toshiba Corp Mos type semiconductor integrated circuit
GB2183905B (en) * 1985-11-18 1989-10-04 Plessey Co Plc Method of semiconductor device manufacture
JPS6423529A (en) * 1987-07-20 1989-01-26 Fuji Electric Co Ltd Manufacture of semiconductor device
NL8703039A (nl) * 1987-12-16 1989-07-17 Philips Nv Werkwijze voor het patroonmatig vervaardigen van een dunne laag uit een oxidisch supergeleidend materiaal.
JPH03201535A (ja) * 1989-12-28 1991-09-03 Nippon Telegr & Teleph Corp <Ntt> 半導体装置とその製造方法
JPH042120A (ja) * 1990-04-18 1992-01-07 Fujitsu Ltd 半導体装置の製造方法
JPH0467649A (ja) * 1990-07-09 1992-03-03 Fujitsu Ltd 半導体装置の製造方法
JPH0775244B2 (ja) * 1990-11-16 1995-08-09 信越半導体株式会社 誘電体分離基板及びその製造方法
JPH04297055A (ja) * 1991-03-26 1992-10-21 Sharp Corp 半導体装置の製造方法
EP0525256A1 (en) * 1991-07-25 1993-02-03 Motorola, Inc. Method of fabricating isolated device regions
US5270265A (en) * 1992-09-01 1993-12-14 Harris Corporation Stress relief technique of removing oxide from surface of trench-patterned semiconductor-on-insulator structure
JPH06268054A (ja) * 1993-03-10 1994-09-22 Nippondenso Co Ltd 半導体装置
JPH0745713A (ja) * 1993-07-29 1995-02-14 Kawasaki Steel Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
TW309648B (zh) 1997-07-01
GB9627000D0 (en) 1997-02-12
GB2309587A (en) 1997-07-30
CN1180238A (zh) 1998-04-29
GB2309587B (en) 2000-07-05
CN1084524C (zh) 2002-05-08
JPH1012850A (ja) 1998-01-16
DE19654697A1 (de) 1997-07-03

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