DE19654697A1 - Substrat mit Silicium auf einem Isolator und Verfahren zu dessen Herstellung - Google Patents
Substrat mit Silicium auf einem Isolator und Verfahren zu dessen HerstellungInfo
- Publication number
- DE19654697A1 DE19654697A1 DE19654697A DE19654697A DE19654697A1 DE 19654697 A1 DE19654697 A1 DE 19654697A1 DE 19654697 A DE19654697 A DE 19654697A DE 19654697 A DE19654697 A DE 19654697A DE 19654697 A1 DE19654697 A1 DE 19654697A1
- Authority
- DE
- Germany
- Prior art keywords
- layer
- wafer
- insulating layer
- photoresist
- sacrificial layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 42
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 6
- 239000010703 silicon Substances 0.000 title claims abstract description 6
- 239000012212 insulator Substances 0.000 title claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title abstract 2
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 20
- 239000001301 oxygen Substances 0.000 claims abstract description 20
- -1 oxygen ions Chemical class 0.000 claims abstract description 17
- 238000002955 isolation Methods 0.000 claims abstract description 16
- 238000005468 ion implantation Methods 0.000 claims abstract description 9
- 229920005989 resin Polymers 0.000 claims abstract description 8
- 239000011347 resin Substances 0.000 claims abstract description 8
- 238000000137 annealing Methods 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 36
- 229920002120 photoresistant polymer Polymers 0.000 claims description 23
- 238000000926 separation method Methods 0.000 claims description 13
- 238000010438 heat treatment Methods 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 claims description 5
- 239000011521 glass Substances 0.000 claims description 4
- 239000002253 acid Substances 0.000 claims 1
- 239000004744 fabric Substances 0.000 claims 1
- 239000000463 material Substances 0.000 abstract description 3
- 238000000059 patterning Methods 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 59
- 229920003002 synthetic resin Polymers 0.000 description 4
- 239000000057 synthetic resin Substances 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000005496 tempering Methods 0.000 description 2
- 239000002966 varnish Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000004922 lacquer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26533—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically inactive species in silicon to make buried insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/78654—Monocrystalline silicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76267—Vertical isolation by silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76281—Lateral isolation by selective oxidation of silicon
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Element Separation (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950069460A KR970052022A (ko) | 1995-12-30 | 1995-12-30 | 에스 오 아이 기판 제조방법 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE19654697A1 true DE19654697A1 (de) | 1997-07-03 |
Family
ID=19448458
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE19654697A Ceased DE19654697A1 (de) | 1995-12-30 | 1996-12-30 | Substrat mit Silicium auf einem Isolator und Verfahren zu dessen Herstellung |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPH1012850A (zh) |
| KR (1) | KR970052022A (zh) |
| CN (1) | CN1084524C (zh) |
| DE (1) | DE19654697A1 (zh) |
| GB (1) | GB2309587B (zh) |
| TW (1) | TW309648B (zh) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11204452A (ja) | 1998-01-13 | 1999-07-30 | Mitsubishi Electric Corp | 半導体基板の処理方法および半導体基板 |
| KR100366923B1 (ko) * | 2001-02-19 | 2003-01-06 | 삼성전자 주식회사 | 에스오아이 기판 및 이의 제조방법 |
| US6737332B1 (en) * | 2002-03-28 | 2004-05-18 | Advanced Micro Devices, Inc. | Semiconductor device formed over a multiple thickness buried oxide layer, and methods of making same |
| EP1993127B1 (en) | 2007-05-18 | 2013-04-24 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method of SOI substrate |
| US8119490B2 (en) * | 2008-02-04 | 2012-02-21 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing SOI substrate |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5745947A (en) * | 1980-09-03 | 1982-03-16 | Toshiba Corp | Mos type semiconductor integrated circuit |
| GB2183905B (en) * | 1985-11-18 | 1989-10-04 | Plessey Co Plc | Method of semiconductor device manufacture |
| JPS6423529A (en) * | 1987-07-20 | 1989-01-26 | Fuji Electric Co Ltd | Manufacture of semiconductor device |
| NL8703039A (nl) * | 1987-12-16 | 1989-07-17 | Philips Nv | Werkwijze voor het patroonmatig vervaardigen van een dunne laag uit een oxidisch supergeleidend materiaal. |
| JPH03201535A (ja) * | 1989-12-28 | 1991-09-03 | Nippon Telegr & Teleph Corp <Ntt> | 半導体装置とその製造方法 |
| JPH042120A (ja) * | 1990-04-18 | 1992-01-07 | Fujitsu Ltd | 半導体装置の製造方法 |
| JPH0467649A (ja) * | 1990-07-09 | 1992-03-03 | Fujitsu Ltd | 半導体装置の製造方法 |
| JPH0775244B2 (ja) * | 1990-11-16 | 1995-08-09 | 信越半導体株式会社 | 誘電体分離基板及びその製造方法 |
| JPH04297055A (ja) * | 1991-03-26 | 1992-10-21 | Sharp Corp | 半導体装置の製造方法 |
| EP0525256A1 (en) * | 1991-07-25 | 1993-02-03 | Motorola, Inc. | Method of fabricating isolated device regions |
| US5270265A (en) * | 1992-09-01 | 1993-12-14 | Harris Corporation | Stress relief technique of removing oxide from surface of trench-patterned semiconductor-on-insulator structure |
| JPH06268054A (ja) * | 1993-03-10 | 1994-09-22 | Nippondenso Co Ltd | 半導体装置 |
| JPH0745713A (ja) * | 1993-07-29 | 1995-02-14 | Kawasaki Steel Corp | 半導体装置の製造方法 |
-
1995
- 1995-12-30 KR KR1019950069460A patent/KR970052022A/ko not_active Application Discontinuation
-
1996
- 1996-12-25 JP JP8356108A patent/JPH1012850A/ja active Pending
- 1996-12-27 GB GB9627000A patent/GB2309587B/en not_active Expired - Fee Related
- 1996-12-28 TW TW085116216A patent/TW309648B/zh active
- 1996-12-30 DE DE19654697A patent/DE19654697A1/de not_active Ceased
- 1996-12-30 CN CN96123929A patent/CN1084524C/zh not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| TW309648B (zh) | 1997-07-01 |
| CN1084524C (zh) | 2002-05-08 |
| KR970052022A (ko) | 1997-07-29 |
| GB2309587A (en) | 1997-07-30 |
| JPH1012850A (ja) | 1998-01-16 |
| GB2309587B (en) | 2000-07-05 |
| CN1180238A (zh) | 1998-04-29 |
| GB9627000D0 (en) | 1997-02-12 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8110 | Request for examination paragraph 44 | ||
| 8127 | New person/name/address of the applicant |
Owner name: HYNIX SEMICONDUCTOR INC., ICHON, KYONGGI, KR |
|
| 8127 | New person/name/address of the applicant |
Owner name: MAGNACHIP SEMICONDUCTOR, LTD., CHEONGJU, KR |
|
| 8131 | Rejection |