GB2309587A - A method of fabricating a SOI substrate - Google Patents

A method of fabricating a SOI substrate Download PDF

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Publication number
GB2309587A
GB2309587A GB9627000A GB9627000A GB2309587A GB 2309587 A GB2309587 A GB 2309587A GB 9627000 A GB9627000 A GB 9627000A GB 9627000 A GB9627000 A GB 9627000A GB 2309587 A GB2309587 A GB 2309587A
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layer
wafer
region
insulating layer
silicon
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GB2309587B (en
GB9627000D0 (en
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Jae Kap Kim
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SK Hynix Inc
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Hyundai Electronics Industries Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26533—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically inactive species in silicon to make buried insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/78654—Monocrystalline silicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76267—Vertical isolation by silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76281—Lateral isolation by selective oxidation of silicon

Description

2309587 SILICON-ON-INSULATOR SUBSTRATE AND METHOD OF FABRICATING THE SAME
BACKGROUND OF THE INVENTION
The present invention relates to a silicon-oninsulator (11S0I11) substrate and a method of fabricating the same, and more particularly to a SOI substrate having a planar surface and a method of fabricating a SOI substrate, io which can simultaneously form an isolation film and a buried insulating layer.
In general, in a a fabrication process of a complementary metal oxide semiconductor (11CMOST1) transistor, an isolation region of a large area is needed in order to isolate devices and prevent latch-up of a CMOS transistor. There are, however, problems in that an isolation region of a large area results in reduced chip dimensions and reduced integration of devices.
A SOI technique had been proposed in order to above problems. With complete isolation between devices, a SOI substrate, having a buried insulating layer sandwiched between a Si handling substrate and a Si device substrate, prevents latch-up of a CMOS transistor and allows for high operational speed of devices.
According to a separation by implanted oxygen (11SIMOX'1) method, referring to FIG.1A, there is a Si wafer doped with impurity ions having a predetermined conductivity type. oxygen ions are implanted into the Si 1 wafer 10 with a predetermined energy form a doped impurity region 11.
Referring to FIG.IB, the annealing process is carried out to form a buried insulating layer 11A in the Si wafer 10 and to form a Si layer 10A on the buried insulating layer 11A, where a device is to be formed. Next, a pad oxide 12 is formed on the Si layer 10A by a thermal oxidation and a silicon nitride layer 13 is deposited on the pad oxide 12 by a chemical vapor deposition. Then, the pad oxide 12 and the silicon nitride layer 13 are patterned to expose an isolation region F of the Si layer 10A.
Referring to FIG.1C, the thermal oxidation is carried out to form a field oxide 14 at the exposed Si layer 10A of the isolation region F, thereby defining an active region is AA by the field oxide 14. Accordingly, a SOI substrate 200 is fabricated which comprises the Si wafer 10, the Si layer 10A, a buried insulating layer 11A formed between the Si wafer 10 and the Si layer 10A, and the field oxide 14 for an isolation.
The conventional method using SIMOX and LOCOS has disadvantages in that it takes a long time to fabricate the SOI substrate, since a long thermal oxidation process is required in order to form the buried insulating layer 11A and the field oxide 14. In addition, since the field oxide
14 for defining the active region AA is formed by LOCOS process. the fabrication process is complicated.
Furthermore, since the SOI substrate 200 has a topology due 2 to the field oxide, a separate additional process for planarization is required in order to obtain the SOI substrate having a planar surface.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method, of fabricating a SOI substrate, which simultaneously forms a buried layer and an isolation film.
Another object of the present invention is to provide a method, of fabricating, a SOI substrate, which is simplified.
Another object of the present invention is to provide SOI substrate having a planar surface.
In accordance with one embodiment, there is provided method of fabricating a silicon-on-insulator wafer, comprising the steps of: forming a sacrificial layer on an isolation region of the Si wafer to expose an active region of the Si wafer; implanting oxygen ions into the Si wafer to form an ion implantation region within the Si wafer; and annealing the Si wafer to form a Si layer in the active region and to form a buried insulating layer in the Si wafer, the Si layer being isolated from the Si wafer by the buried insulating layer, which is coplanar with the Si layer.
In one embodiment, the step for forming the sacrificial layer includes the steps of: coating 3 photosensitive resin on the Si waf er; and exposing and developing the photosensitive resin to form the sacrificial layer over the isolation region of the Si wafer. The photosensitive resin for said sacrificial layer is either polymide or photoresist.
Alternatively, the step for forming the sacrificial layer includes the steps of: forming a layer having a different etching rate from the Si wafer on the Si wafer; coating a photoresist film on the layer; patterning the photoresist film to expose the layer over the active region; etching the layer by using the photoresist film as a mask to form the sacrificial layer over the isolation region of the Si wafer; and removing the photoresist pattern. The layer for the sacrificial layer is spin on glass.
In one embodiment, the oxygen ions are implanted with energy sufficient to pass said sacrificial layer, and a dose of 5X1017 - 7x101lions /CM2.
In one embodiment, the sacrificial layer has a :0 thickness H expressed by the following equation.
H = dl + 1/2.d2 wherein dl is the ion implantation depth of oxygen ions and d2 is the thickness of the ion implantation region.
In one embodiment, the step for annealing said Si wafer is carried out at a temperature of 1100-13000C for 2- 7 hours.
There is also provided a silicon-on-insulator 4 substrate, comprising: a Si wafer where an isolation region and an active region are defined; a Si layer formed in the active region of the Si wafer; and an insulating layer formed in the Si wafer, the insulating layer being coplanar with the Si layer, for isolating the Si layer from the Si wafer.
In one embodiment, the insulating layer of an buried insulating layer. And of the insulating layer, the portion formed in the isolation region of the. Si wafer and being 10 coplanar with the Si layer, serves as a field oxide of the silicon-on- insulator substrtte and the portion formed in the active region of the Si wafer serves as a buried insulating layer of the silicon-on-insulator substrate.
BRIEF DESCRIPTION OF THE DRAWINGS
The objects and feature of the invention may be better understood with reference to the following detailed description, appended claims, and attached drawings 20 wherein:
FIG.1A through FIG.1C are simplified sectional views illustrating a conventional process of fabricating a SOI substrate; FIG.2 is a simplified sectional view of a SOI substrate in accordance with an embodiment of the present invention; and FIG.3A through FIG.3C are simplified sectional views illustrating a process of fabricating a SOI substrate in accordance with an embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
Referring to FIG.2, in accordance with an embodiment of the present invention, a SOI substrate 100 where is defined to an active region AA and a field region F, comprises a Si wafer 1 supporting the SO1 substrate 100 and a Si layer 1A formed over the Si wafer 1, where a device is to be formed, and a biried insulating layer 3A for isolating the Si layer 1A from the Si wafer 1. The Si layer 1A is formed at the active region AA of the SOI substrate 100.
Over the Si wafer 1, the buried insulation layer 3A, made of an oxide layer, is formed to surround the Si layer!A, thereby isolating the Si layer 1A from the Si wafer 1. of the buried insulating layer 3A, the portion in the isolation region F serves as a field oxide for an isolation and the portion sandwiched between the Si layer 1A and the Si wafer 1 in the active region AA serves as a buried insulating layer of the SOI substrate 100. Herein, the depth of the Si layer 1A is 0.08-0.3pm and the thickness of the buried insulating layer 3A serving as a field oxide in the isolation region F is 0.07-0.45gm.
A method of fabricating the SCI substrate 100 of FIG.2 is as follows. Referring to FIG.3A, on the surface of a Si 6 wafer 1 which is either a doped. Si wafer or an undoped Si wafer, a sacrificial layer 2 is formed at a predetermined thickness. Herein, the sacrificial layer 2 is made of a resin such as photoresist or polymide. Otherwise, the sacrificial layer 2 may be a material having a different etching rate from the Si wafer 1, for example spin on glass (11SOG11). The sacrificial layer 2 is patterned to remain at the isolation region F of the Si wafer 1.
At this time, in case where the sacrificial layer 2 comprises a photosensitive resin, it is patterned by an exposure and development p:rocess. on the other hand, in case where the sacrificial layer 2 comprises a material having a different etching rate from the Si wafer 1, for example SOG, a photoresist pattern is formed on the sacrificial layer 2 by a conventional lithography process and then the sacrificial layer 2 is patterned by using the photoresist pattern as a mask.
Referring to FIG.3B, oxygen ions having a predetermined energy are implanted into the Si wafer 1. The thickness H of the sacrificial layer 2 depends on the oxygen ion implantation process and is expressed by the following equation.
H di + d2/2 Herein, di is an depth where the oxygen ions are implanted into the Si wafer 1 and d2 is a thickness of an region 3 of the Si waf er 1, where the oxygen ions are implanted. At this time, if the implantation depth di makes 7 0.08-0.3gm and the thickness d2 of the implantation region 3 makes 0.07-0. 5gm, the thickness of the sacrificial layer 2 is 0.1-0.6gm.
The oxygen ions are implanted into the Si wafer 1 with a dose of 5X1017 7x101'ions/cm' and with energy sufficient to pass the sacrif icial layer implanted into the Si wafer 1 surface of the Si wafer 1 in otherwise, in the active region 2. The oxygen -Lons are to be located below the the isolation region F. AA, the implanted oxygen ions are located within the Si wafer 1 at the depth of 0.08gm-0.3gm. As above desqribed, the depth di where the oxygen ions are implanted into the Si wafer 1 depends on the thickness H of the sacrificial layer 2.
Referring to FIG.3C, the process for annealing the Si wafer 1 is carried out at a temperature of 1100-13000C for 2-7 hours to form a buried insulating layer 3A as an insulating layer and to form a Si layer 1A where a device is to be formed. The Si layer 1A is isolated from the Si wafer 1 by the buried insulating layer 3A. Of the buried insulating layer 3A, the portion in the isolation region F serves as a field oxide for an isolation and the portion in the active region AA serves as a buried insulating layer of the SOI substrate100.
Herein, the buried insulating layer 3A is formed only in the Si wafer 1 such that the portion of the buried insulating layer 3A which is protruded to the surface of the Si wafer 1 is not exist.
8 Afterwards, the sacrificial layer 2 is removed to obtain a SOI substrate 100 having a planar surface, which includes the Si wafer 1, the Si layer 1A, and a buried insulating layer 3A formed between the Si wafer 1 and the SI layer 1A. The sacrificial layer 2 may be removed before or after the annealing process.
According to the present invention, a buried insulating layer serving as a field oxide as well as an insulating layer of a SOI substrate is formed by one oxygen ion implantation process and annealing process, thereby simplifying the fabrication, process, reducing the process time, and obtaining the SOI substrate having a planar surface.
While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to this description. It is therefore contemplated that the appended claims will cover any such modifications or embodiments as fall within the true scope of the invention.
is 9

Claims (19)

what is claimed in:
1. A method of fabricating a silicon-on-insulator substrate, comprising the steps of:
forming a sacrificial layer on an isolation region or the Si wafer to expose an active region of said Si wafer; implanting oxygen ions into said Si wafer to form an ion implantation region within said Si wafer; and annealing said Si wafer to form-a Si layer in said active region and to form a buried insulating layer in said Si wailer, said Si layer bei&g isolated from said Si wafer by said buried insulating layer which is coplanar with said Si layer.
2. The method as claimed in claim 1, wherein said step for forming said sacrificial layer includes the steps of:
coating photosensitive resin on said Si wafer; and exposing and developing said photosensitive resin to form said sacrificial layer over said isolation region of .0 said Si wafer.
3. The method as claimed in claim 2, wherein said photosensitive resin for said sacrificial layer is polymide.
4. The method as claimed in claim 2, wherein said photosensitive resin for said sacrificial layer is photoresist.
5. The method as claimed in claim 1, wherein said step for forming said sacrificial layer includes the steps of:
forming a layer having a different etching rate from Si wafer on said Si wafer; coating a photoresist film on said layer; patterning said photoresist film to expose said layer over said active region; etching said layer by using said photoresist film as a mask to form said sacrif:cial layer over said isolation region of said Si wafer; and removing said photoresist pattern.
is
6. The method as claimed in claim 5, wherein said layer for said sacrificial layer is spin on glass.
7. The method as claimed in claim 1, wherein said oxygen ions are implanted into said Si wafer with a dose of 5X1017 - 7x1018ions/cm2.
8. The method as claimed in claim 1, wherein the oxygen ions are implanted with energy sufficient to pass said sacrificial layer.
9. The method as claimed in claim 1, wherein said sacrificial layer has a thickness H expressed by the 11 equation, H = dl + 1/2.d2 wherein di is the ion implantation depth of oxygen ions and d2 is the thickness of said ion implantation region.
10. The method as claimed in claim 9, wherein said ion implantation depth of said oxygen ions ir. said active 10 region is 0.08-0.3jim.
t
11. The method as claimed in claim 9, wherein said thickness of said ion implantation region is 0.07-0.5gm.
12. The method as claimed in claim 9, wherein said sacrificial layer is formed at a thickness of 0.1-0.6gm.
13. The method as claimed in claim i, wherein said step for annealing said Si wafer is carried out at a 20 temperature of 1100-13000C for 2-7 hours.
14. A silicon-on- insulator substrate, comprising:
a Si wafer where an isolation region and an active region are defined; a Si layer formed in said active region of said Si wafer; and an insulating layer formed in said Si wafer, said 12 insulating layer being coplanar with said Si layer, for isolating said Si layer from said Si wafer.
15. The silicon-on- insulator substrate as claimed in claim 14, wherein said oxide layer is an buried insulating layer.
16. The siliccn-on-insulatcr substrate as claimed in claim 14, wherein of said insulating. layer, the portion formed in said isolation region of said Si wafer and being coplanar with said Si layey, serves as a field oxide of said silicon-on-insulator substrate.
17. The sil icon- on- insulator substrate as claimed in claim 14, wherein of said insulating layer, the portion formed in said active region of said Si wafer serves as a buried insulating layer of said silicon-on-insulator substrate.
18. The silicon-on- insulator substrate as claimed in claim 17, wherein said portion of said insulating layer formed in said ac.tive region has a thickness of 0.07 0. 45gm.
19. The silicon-on- insulator substrate as claimed in claim 14, wherein said Si layer has a depth of 0.08-0.3gm.
GB9627000A 1995-12-30 1996-12-27 Silicon-on-insulator substrate and method fabricating the same Expired - Fee Related GB2309587B (en)

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KR1019950069460A KR970052022A (en) 1995-12-30 1995-12-30 SOH eye substrate manufacturing method

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KR970052022A (en) 1997-07-29
TW309648B (en) 1997-07-01
GB9627000D0 (en) 1997-02-12
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CN1084524C (en) 2002-05-08
CN1180238A (en) 1998-04-29
DE19654697A1 (en) 1997-07-03

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