KR970052022A - SOH eye substrate manufacturing method - Google Patents

SOH eye substrate manufacturing method Download PDF

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Publication number
KR970052022A
KR970052022A KR1019950069460A KR19950069460A KR970052022A KR 970052022 A KR970052022 A KR 970052022A KR 1019950069460 A KR1019950069460 A KR 1019950069460A KR 19950069460 A KR19950069460 A KR 19950069460A KR 970052022 A KR970052022 A KR 970052022A
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KR
South Korea
Prior art keywords
film
sacrificial
layer
forming
manufacturing
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KR1019950069460A
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Korean (ko)
Inventor
김재갑
Original Assignee
김주용
현대전자산업 주식회사
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Priority to KR1019950069460A priority Critical patent/KR970052022A/en
Priority to JP8356108A priority patent/JPH1012850A/en
Priority to GB9627000A priority patent/GB2309587B/en
Priority to TW085116216A priority patent/TW309648B/zh
Priority to DE19654697A priority patent/DE19654697A1/en
Priority to CN96123929A priority patent/CN1084524C/en
Publication of KR970052022A publication Critical patent/KR970052022A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26533—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically inactive species in silicon to make buried insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/78654—Monocrystalline silicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76267—Vertical isolation by silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76281—Lateral isolation by selective oxidation of silicon

Abstract

본 발명은 에스 오 아이(이하 SOI : silicon on insulator) 기판 제조방법에 관한 것으로, 보다 구체적으로는 SIMOX(separation by implanted oxygen) 방법에 의한 SOI 기판 형성시, SOI층 하부의 절연막의 형성과 동시에 소자간의 분리막을 형성하여 공정단계를 감축할 수 있는 SOI기판 제조방법에 관한 것으로, 본 발명에 의하면 SIMOX 방식에 따른 SOI 기판 제조방법에 있어서, 소자 분리 예정 영역 상부에 희생막을 형성한 다음, 산소 이온을 이온 주입하여 별도의 소자분리막의 형성 공정 없이 소자 분리막을 포함한 베리드 산화층의 형성되므로, 공정 단계를 감축시키고, 이로써 소자의 제조 시간 및 수율을 개선할 수 있다.The present invention relates to a method of manufacturing a silicon on insulator (SOI) substrate, and more particularly, to forming an SOI substrate by a separation by implanted oxygen (SIMOX) method, and simultaneously with forming an insulating layer under the SOI layer. The present invention relates to a method for manufacturing an SOI substrate capable of reducing a process step by forming a separation membrane of the liver. According to the present invention, an SOI substrate manufacturing method according to the SIMOX method is provided. Since the buried oxide layer including the device isolation layer is formed by ion implantation without forming a separate device isolation layer, the process step can be reduced, thereby improving the fabrication time and yield of the device.

Description

에스 오 아이 기판 제조방법SOH eye substrate manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도 (가) 내지 (다)는 본 발명의 에스 오 아이 기판 제조방법을 설명하기 위한 각 제조공정에 있어서의 요부 단면도.2 (a) to (c) are cross-sectional views of the main parts in each manufacturing process for explaining the SOH eye substrate manufacturing method of the present invention.

Claims (7)

실리콘 기판상의 희생산화막을 형성하는 단계; 상기 희생막을 소자 분리 예정 영역에만 존재하도록 식각하는 단계; 상기 식각이 이루어진 희생막을 포함하는 실리콘 기판 전면에 산소 이온을 이온 주입하는 단계; 상기 잔존하는 희생막을 제거하는 단계; 및 상기 이온 주입이 이루어진 실리콘 기판을 열처리하여 소자 분리막을 포함하는 베리드 산화층을 형성하는 단계를 포함하는 것을 특징으로 하는 SOI 기판 제조방법.Forming a sacrificial oxide film on the silicon substrate; Etching the sacrificial layer so that the sacrificial layer exists only in a region in which the device is to be separated; Implanting oxygen ions into an entire surface of the silicon substrate including the etched sacrificial layer; Removing the remaining sacrificial film; And forming a buried oxide layer including an isolation layer by heat-treating the silicon substrate on which the ion implantation is performed. 제1항에 있어서, 상기 희생막은 감광막, 폴리이미드막, SOG막 중 선택되는 하나의 막인 것을 특징으로 하는 SOI 기판 제조방법.The method of claim 1, wherein the sacrificial film is one film selected from a photosensitive film, a polyimide film, and an SOG film. 제1항에 있어서, 상기 희생막의 두께는 산소 주입 예정 깊이+기판의 높이/2 정도인 것을 특징으로 하는 SOI 기판 제조방법.The method of claim 1, wherein a thickness of the sacrificial layer is about a predetermined oxygen injection depth + a height / 2 of a substrate. 제1항 내지 제3항 중 어느 한 항에 있어서, 상기 희생막이 존재하지 않는 영역에서의 산소 이온의 이온 주입 깊이는 0.08 내지 0.3㎛인 것을 특징으로 하는 SOI 기판 제조방법.The method of manufacturing an SOI substrate according to any one of claims 1 to 3, wherein an ion implantation depth of oxygen ions in a region where the sacrificial film is not present is 0.08 to 0.3 µm. 제1항에 있어서, 상기 이온 주입되는 산소 원자의 농도는 5×1017/㎠ 내지 7×1018/㎠의 정도인 것을 특징으로 하는 SOI 기판 제조방법.The method of claim 1, wherein the concentration of the ion-implanted oxygen atoms is about 5 × 10 17 / cm 2 to 7 × 10 18 / cm 2. 제1항에 있어서, 상기 열처리 단계는 1100 내지 1300℃의 온도에서 2 내지 7시간 정도 열처리하는 것을 특징으로 하는 SOI 기판 제조방법.The method of claim 1, wherein the heat treatment is performed at a temperature of 1100 to 1300 ° C. for about 2 to 7 hours. 제1항에 있어서, 상기 베드리 산화층 중 소자 분리막 부분의 두께는 0.07 내지 0.45㎛정도인 것을 특징으로 하는 SOI 기판 제조방법.The method of claim 1, wherein the thickness of the device isolation layer in the bed oxide layer is about 0.07 to 0.45 μm. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950069460A 1995-12-30 1995-12-30 SOH eye substrate manufacturing method KR970052022A (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
KR1019950069460A KR970052022A (en) 1995-12-30 1995-12-30 SOH eye substrate manufacturing method
JP8356108A JPH1012850A (en) 1995-12-30 1996-12-25 Soi substrate and its manufacture
GB9627000A GB2309587B (en) 1995-12-30 1996-12-27 Silicon-on-insulator substrate and method fabricating the same
TW085116216A TW309648B (en) 1995-12-30 1996-12-28
DE19654697A DE19654697A1 (en) 1995-12-30 1996-12-30 Silicon substrate on an insulator and method of making the same
CN96123929A CN1084524C (en) 1995-12-30 1996-12-30 Silicon-on-insulator substrate and method for fabricating the same

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KR1019950069460A KR970052022A (en) 1995-12-30 1995-12-30 SOH eye substrate manufacturing method

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KR970052022A true KR970052022A (en) 1997-07-29

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JP (1) JPH1012850A (en)
KR (1) KR970052022A (en)
CN (1) CN1084524C (en)
DE (1) DE19654697A1 (en)
GB (1) GB2309587B (en)
TW (1) TW309648B (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11204452A (en) 1998-01-13 1999-07-30 Mitsubishi Electric Corp Semiconductor substrate and method for treatment thereof
KR100366923B1 (en) * 2001-02-19 2003-01-06 삼성전자 주식회사 SOI Substrate and Method of Manufacturing Thereof
US6737332B1 (en) * 2002-03-28 2004-05-18 Advanced Micro Devices, Inc. Semiconductor device formed over a multiple thickness buried oxide layer, and methods of making same
EP1993127B1 (en) * 2007-05-18 2013-04-24 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of SOI substrate
US8119490B2 (en) * 2008-02-04 2012-02-21 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate

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JPS5745947A (en) * 1980-09-03 1982-03-16 Toshiba Corp Mos type semiconductor integrated circuit
GB2183905B (en) * 1985-11-18 1989-10-04 Plessey Co Plc Method of semiconductor device manufacture
JPS6423529A (en) * 1987-07-20 1989-01-26 Fuji Electric Co Ltd Manufacture of semiconductor device
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JPH03201535A (en) * 1989-12-28 1991-09-03 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device and manufacture thereof
JPH042120A (en) * 1990-04-18 1992-01-07 Fujitsu Ltd Manufacture of semiconductor device
JPH0467649A (en) * 1990-07-09 1992-03-03 Fujitsu Ltd Manufacture of semiconductor device
JPH0775244B2 (en) * 1990-11-16 1995-08-09 信越半導体株式会社 Dielectric isolation substrate and manufacturing method thereof
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JPH0745713A (en) * 1993-07-29 1995-02-14 Kawasaki Steel Corp Manufacture of semiconductor device

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Publication number Publication date
CN1084524C (en) 2002-05-08
CN1180238A (en) 1998-04-29
DE19654697A1 (en) 1997-07-03
GB2309587B (en) 2000-07-05
JPH1012850A (en) 1998-01-16
TW309648B (en) 1997-07-01
GB9627000D0 (en) 1997-02-12
GB2309587A (en) 1997-07-30

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