CN1180238A - Soi基片及其制造方法 - Google Patents

Soi基片及其制造方法 Download PDF

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CN1180238A
CN1180238A CN96123929A CN96123929A CN1180238A CN 1180238 A CN1180238 A CN 1180238A CN 96123929 A CN96123929 A CN 96123929A CN 96123929 A CN96123929 A CN 96123929A CN 1180238 A CN1180238 A CN 1180238A
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soi substrate
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金载甲
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MagnaChip Semiconductor Ltd
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Abstract

本发明提供一种SOI基片的制造方法,可使SOI基片具有平坦的表面,并能同时形成元件分隔膜和埋置绝缘层。该方法包括下列步骤:在硅晶片的元件分隔区形成损耗膜,以露出所述硅晶片的有源区;向所述硅晶片内注入氧离子,形成硅晶片内的离子注入区;对硅晶片退火,于是形成埋置绝缘层,该埋置绝缘层使有源区的硅层与所述硅晶片隔离,并形成与所述硅层具有同一平面的埋置绝缘层。

Description

SOI基片及其制造方法
本发明涉及SOI(绝缘膜上生长硅)基片及其制造方法，具体地说，涉及能同时形成有平坦表面的SOI基片、元件分隔膜和埋置绝缘层的SOI基片及其制造方法。
通常，CMOS晶体管的制造工艺中，为了确保在大面积上的元件间分隔及防止CMOS晶体管的闭锁现象，要形成元件分隔。此时，增加了分隔区就减少芯片区，从而成为阻碍高集成度化的因素。为解决这种问题，提出了SOI技术。
作为完全的元件分隔结构，在硅支撑基片与器件用硅基片之间设置预定厚度的埋置绝缘膜的SOI基片，可防止CMOS晶体管的闭锁现象，实现器件的高速动作。
以往的SIMOX(由注入的氧进行分隔)技术如图3A所示，制备掺杂预定杂质的硅晶片10。向硅晶片10内离子注入有一定能量的氧离子(O2)。
然后，参见图3B，对硅晶片10进行退火，在硅晶片10内形成硅层10A用于在埋置绝缘层11A上部形成器件。在硅层10A上部通过热氧化形成衬底氧化膜12、并在衬底氧化膜上部用化学汽相淀积法形成氮化硅膜13。对衬底氧化膜12和氮化硅膜13构图，使硅层10A的元件分隔区F露出。
如图3C所示，对露出的硅层部分F进行热氧化，于是形成场氧化膜13，并由场氧化膜14限定出有源区AA。
从而制造出由硅晶片10、硅层10A、埋置绝缘层11A及元件分隔用的场氧化膜14所组成的SOI基片200
用上述SIMOX技术和选择氧化法制备有源区的SOI基片存在下列问题，即由于为形成埋置绝缘层11A、场氧化膜14，需要进行较长时间的热处理，因而增加了制造时间
此外，因利用“LOCOS法”形成用于限定有源区的场氧化膜，因此存在使工艺变复杂的问题
而且，由于SOI基片具有由场氧化膜所决定的拓扑图形，因而要求其它平坦化工艺。
本发明的目的是提供一种能同时形成埋置绝缘层与场氧化膜的SOI基片的制造方法。
本发明的另一个目的是提供可使工艺简单化的SOI基片的制造方法。
本发明的再一个目的是提供表面平坦的SOI基片。
为实现上述目的，本发明提供的SOI基片制造方法包括下列步骤：在硅晶片的元件分隔区上形成损耗膜，并使所述硅晶片的有源区露出；向所述硅晶片内离子注入氧离子，形成在硅中的离子注入区，形成使所述硅晶片与硅层隔离、具有与所述硅层同一平面的埋置绝缘层。
并且，本发明所提供的SOI基片包括下列部分：
限定了元件分隔区与有源区的硅晶片；在所述硅晶片有源区上部形成的硅层；形成在所述硅晶片内、使所述硅晶片与硅层隔离的绝缘层。
下面，参照附图详细说明本发明最佳实施例。
图1是本发明SOI基片的剖面图；
图2A-2C是说明本发明SOI基片制造方法的剖面图；
图3A-3C是说明现有SOI基片制造方法的剖面图。
参见图1，由支撑SOI基片100的硅晶片1、形成于硅晶片100上部将形成器件的硅层1A和使硅晶片1与硅层1A隔离的埋置绝缘层3A组成SOI基片100，该SOI基片100限定了元件分隔区F和有源区AA。硅层1A形成于SOI基片100的有源区AA。
由氧化膜组成的埋置绝缘层3A形成于硅晶片1上部，包围硅层1A，从而使硅晶片1与硅层1A隔离。在元件分隔区F的埋置绝缘层3A用作元件分隔用的场氧化膜，同时，在置于硅层1A与硅晶片1之间的有源区AA的绝缘层用作SOI基片100的埋置绝缘层。其中，硅层1A深度为0.08～0.3μm，在元件分隔区F用作场氧化膜的埋置绝缘层3A的厚度为0.07～0.45μm。
下面，说明SOI基片100的制造方法。
如图2A所示，例如硅晶片1，不但不掺杂杂质，并且在未掺杂杂质的硅晶片上部形成预定厚度的损耗膜2。其中，损耗膜2不仅可为与光刻胶、聚酰胺相同的树脂，而且可用与硅晶片蚀刻率不同的物质，如SOG(玻璃上旋涂)材料。对该损耗膜2构图，使其存在于硅晶片1的元件分隔区上。
此时，若损耗膜2为感光性树脂，则通过曝光及显影进行构图，若损耗膜2为与SOG膜相同的、与硅晶片1蚀刻率不同的膜时，通过光蚀刻工艺形成光刻胶图形之后，用光刻胶图形作掩模，使损耗膜构图。
如图2B所示，向硅晶片I内注入氧离子。
其中，由下式可求出损耗膜2的厚度H，它与氧离子注入工艺有关。
                  H＝d1+d2/2
其中，d1为向硅晶片1内注入氧离子的深度，d2为硅晶片1内注入了氧原子区域的厚度。此时，若离子注入深度d1约0.08～0.3μm、在有源区AA下段离子注入的氧原子区域3的厚度d2约0.07～0.5μm，则损耗膜2的厚度变为约0.1～0.6μm。
然后，离子注入5×1017～7×1018离子/cm2剂量的氧离子，该氧离子有可穿过损耗膜2的能量。离子注入氧离子，要使其在元件分隔区F位于靠近硅晶片1表面处，在有源区AA，使其位于距硅晶片1表面约0.08～0.3μm深度的硅晶片1中。如上所述，在元件分隔区F离子注入氧离子的深度与损耗膜2的厚度H有关。
参见图2C，在1100～1300℃的温度下，对硅晶片1退火2～7小时，形成用作场氧化膜的埋置绝缘层3A和形成器件的硅层1A。埋置绝缘层3A使支撑埋置绝缘层3A的硅晶片1与形成器件的第一硅层1A隔离。埋置绝缘层3A的SOI基片100元件分隔区F用作场氧化膜，SOI基片100的有源区AA用作埋置绝缘层。
其中，由于仅在硅晶片1内形成埋置绝缘层3A，因而在硅晶片1表面上不会有突出部分。因此，若在其后除去损耗膜2，则可得到这种SOI基片100，即具有由硅晶片1、硅层IA和它们之间的埋置绝缘层3A组成的平坦表面的SOI基片100。在退火工艺前可除去损耗膜2。
这样，通过单一的氧离子注入工序和退火工序，即可形成起场氧化膜作用的埋置绝缘层3A。因此，减少了工序时间及工序量。
在不违背本发明原理和精神的范围内，本领域技术人员理所当然可容易地获得本发明的各种实施例。因此，上述说明并不是对所附权利要求范围的限定，权利要求书所请求保护的范围包括具有本发明在内的专利性的所有新的技术方案，并且是由本领域普通技术人员就可实现的所有技术方案。

Claims (19)

1、一种SOI基片的制造方法，其特征在于包括下列工艺步骤：
在硅晶片的元件分隔区形成损耗膜，以使所述硅晶片的有源区露出；
向所述硅晶片内注入氧离子，形成所述硅晶片内的离子注入区；
对所述硅晶片退火，于是形成埋置绝缘层，该埋置绝缘层使有源区的硅层与所述硅晶片隔离、并形成与所述硅层有同一平面的埋置绝缘层。
2、如权利要求1的SOI基片的制造方法，其特征在于，形成所述损耗膜的步骤包括：在硅晶片上部涂敷感光性树脂；对所述感光性树脂曝光和使其显影，在元件分隔区上部形成感光性树脂图形的步骤。
3、如权利要求2的SOI基片的制造方法，其特征在于，所述损耗膜用感光性树脂是聚酰亚胺。
4、如权利要求2的SOI基片的制造方法，其特征在于，所述损耗膜用感光性树脂是光刻胶。
5、如权利要求1的SOI基片的制造方法，其特征在于，形成所述损耗膜的工艺步骤包括下列步骤：
在晶片上部形成与硅晶片有不同蚀刻率的膜；
在所述膜上涂敷光刻胶膜；
对光刻胶膜构图，使有源区上部的所述膜露出；
用光刻胶膜作掩模，蚀刻所述露出的膜，于是在硅晶片的元件分隔区上部形成损耗膜；
除去光刻胶膜。
6、如权利要求5的SOI基片的制造方法，其特征在于，所述损耗膜是SOI膜。
7、如权利要求1的SOI基片的制造方法，其特征在于，所述氧离子注入工艺中，离子注入5×1017～7×1018离子/cm2剂量的氧离子。
8、如权利要求1的SOI基片的制造方法，其特征在于，所述氧离子通过所述损耗膜的注入层厚度为0.1～0.5μm。
9、如权利要求1的SOI基片的制造方法，其特征在于，所述损耗膜的厚度H为H＝d1+d2/2，其中，d1是氧离子的离子注入深度，d2是离子注入区的厚度。
10、如权利要求9的SOI基片的制造方法，其特征在于，所述氧离子注入工艺中，在没有所述损耗膜的部分离子注入氧离子的深度是0.08～0.3μm。
11、如权利要求9的SOI基片的制造方法，其特征在于，所述离子注入区的厚度是0.07～0.5μm。
12、如权利要求9的SOI基片的制造方法，其特征在于，所述损耗膜的厚度为0.1～0.6μm。
13、如权利要求1的SOI基片的制造方法，其特征在于，所述退火工艺在1100～1300℃温度范围内进行2～7小时。
14、一种SOI基片，其特征在于包括：限定了元件分隔区与有源区的硅晶片；在所述硅晶片有源区上部形成的硅层；形成在所述硅晶片内、并与所述硅层具有同一平面的绝缘层，该绝缘层使所述硅晶片与硅层隔离。
15、如权利要求14的SOI基片，其特征在于，所述绝缘层是埋置氧化膜。
16、如权利要求14的SOI基片，其特征在于，所述绝缘膜中形成于硅晶片的元件分隔区，即与所述硅层有同一平面的部分被用作SOI基片元件分隔用的场氧化膜。
17、如权利要求14的SOI基片，其特征在于，所述绝缘膜中形成于硅晶片有源区的绝缘层起SOI基片的埋置绝缘层的作用。
18、如权利要求17的SOI基片，其特征在于，相当于所述元件分隔区埋置绝缘层的厚度为0.07～0.45μm。
19、如权利要求14的SOI基片，其特征在于，所述硅层的深度是0.08～0.3μm。
CN96123929A 1995-12-30 1996-12-30 Soi基片的制造方法 Expired - Fee Related CN1084524C (zh)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1310306C (zh) * 2002-03-28 2007-04-11 先进微装置公司 形成于多厚度埋入氧化层上的半导体装置以及制造此半导体装置的方法
CN101308782A (zh) * 2007-05-18 2008-11-19 株式会社半导体能源研究所 Soi衬底的制造方法、以及半导体装置的制造方法
CN101510524B (zh) * 2008-02-04 2013-07-24 株式会社半导体能源研究所 Soi衬底的制造方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11204452A (ja) 1998-01-13 1999-07-30 Mitsubishi Electric Corp 半導体基板の処理方法および半導体基板
KR100366923B1 (ko) * 2001-02-19 2003-01-06 삼성전자 주식회사 에스오아이 기판 및 이의 제조방법

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5745947A (en) * 1980-09-03 1982-03-16 Toshiba Corp Mos type semiconductor integrated circuit
GB2183905B (en) * 1985-11-18 1989-10-04 Plessey Co Plc Method of semiconductor device manufacture
JPS6423529A (en) * 1987-07-20 1989-01-26 Fuji Electric Co Ltd Manufacture of semiconductor device
NL8703039A (nl) * 1987-12-16 1989-07-17 Philips Nv Werkwijze voor het patroonmatig vervaardigen van een dunne laag uit een oxidisch supergeleidend materiaal.
JPH03201535A (ja) * 1989-12-28 1991-09-03 Nippon Telegr & Teleph Corp <Ntt> 半導体装置とその製造方法
JPH042120A (ja) * 1990-04-18 1992-01-07 Fujitsu Ltd 半導体装置の製造方法
JPH0467649A (ja) * 1990-07-09 1992-03-03 Fujitsu Ltd 半導体装置の製造方法
JPH0775244B2 (ja) * 1990-11-16 1995-08-09 信越半導体株式会社 誘電体分離基板及びその製造方法
JPH04297055A (ja) * 1991-03-26 1992-10-21 Sharp Corp 半導体装置の製造方法
EP0525256A1 (en) * 1991-07-25 1993-02-03 Motorola, Inc. Method of fabricating isolated device regions
US5270265A (en) * 1992-09-01 1993-12-14 Harris Corporation Stress relief technique of removing oxide from surface of trench-patterned semiconductor-on-insulator structure
JPH06268054A (ja) * 1993-03-10 1994-09-22 Nippondenso Co Ltd 半導体装置
JPH0745713A (ja) * 1993-07-29 1995-02-14 Kawasaki Steel Corp 半導体装置の製造方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1310306C (zh) * 2002-03-28 2007-04-11 先进微装置公司 形成于多厚度埋入氧化层上的半导体装置以及制造此半导体装置的方法
CN101308782A (zh) * 2007-05-18 2008-11-19 株式会社半导体能源研究所 Soi衬底的制造方法、以及半导体装置的制造方法
CN101308782B (zh) * 2007-05-18 2012-10-17 株式会社半导体能源研究所 Soi衬底的制造方法、以及半导体装置的制造方法
US8895407B2 (en) 2007-05-18 2014-11-25 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of SOI substrate and manufacturing method of semiconductor device
TWI478280B (zh) * 2007-05-18 2015-03-21 Semiconductor Energy Lab Ｓｏｉ基板的製造方法、和半導體裝置的製造方法
CN101510524B (zh) * 2008-02-04 2013-07-24 株式会社半导体能源研究所 Soi衬底的制造方法

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