KR980006254A - 반도체 소자의 제조방법 - Google Patents

반도체 소자의 제조방법 Download PDF

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Publication number
KR980006254A
KR980006254A KR1019960026303A KR19960026303A KR980006254A KR 980006254 A KR980006254 A KR 980006254A KR 1019960026303 A KR1019960026303 A KR 1019960026303A KR 19960026303 A KR19960026303 A KR 19960026303A KR 980006254 A KR980006254 A KR 980006254A
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South Korea
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forming
mask pattern
semiconductor substrate
layer
buffer
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KR1019960026303A
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KR100203306B1 (ko
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김광수
유경동
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김주용
현대전자산업 주식회사
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Priority to KR1019960026303A priority Critical patent/KR100203306B1/ko
Priority to TW086108266A priority patent/TW399303B/zh
Priority to JP9180661A priority patent/JPH1065019A/ja
Priority to US08/882,485 priority patent/US5963798A/en
Priority to GB9713538A priority patent/GB2314972A/en
Priority to DE19727425A priority patent/DE19727425A1/de
Publication of KR980006254A publication Critical patent/KR980006254A/ko
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Publication of KR100203306B1 publication Critical patent/KR100203306B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/07—Guard rings and cmos

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
  • Element Separation (AREA)

Abstract

본 발명은 C 모스 트랜지스터의 래치업 현상을 방지하기 위한 반도체 장치 및 그 제조방법이 개시된다. 개시된 본 발명은 래치 업을 방지하기 위한, 반도체 기판 깊숙히 P형 매몰층의 형성 공정시, 이온 주입 마스크로서, 수직단부가 완만한 경사를 갖는 마스크 패턴을 형성한 다음, 이온 주입 공정에 의하여 P형 매몰층을 형성하므로써, 연속적인 P형 매몰층이 형성된다. 따라서, C모스트랜지스터의 래치 업 현상이 방지된다.

Description

반도체 소자의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 2a도 내지 제2e도는 본 발명의 제1실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 단면도

Claims (9)

  1. 반도체 기판상에 N웰 예정 영역이 노출되도록 제1마스크 패턴을 형성하는 단계; 제1마스크 패턴으로부터 노출된 반도체 기판에 N웰을 형성하는 단계; 상기 제1마스크 패턴을 통과할 만큼의 에너지 범위로 결과물 전면에 P형의 불순물을 이온 주입하는 단계; 및 상기 제1마스크 패턴을 제거하는 단계를 포함하며, 상기 제1마스크 패턴의 수직단부는 완만한 경사를 갖도록 형성하는 것을 특징으로 하는 반도체 소자의 제조방법
  2. 제1항에 있어서, 상기 제1마스크 패턴의 형성단계는, 반도체 기판상에 제1 패드막과, 제1 버퍼막을 증착하는 단계; 및 제1버퍼막과 제1패드막을 N웰 예정 영역이 노출되도록 패터닝하는 단계; 결과물 상부에 제2패드막과 제2 버퍼막을 순차적으로 적층하는 단계 상기 제1버퍼막 상단이 노출되도록 제2버퍼막과 제2패드막을 이방성 식각하여 패터닝된 제1버퍼막과 제1패드막의 수직 표면에 스페이서를 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 제조방법
  3. 제2항에 있어서, 상기 제1 및 제2 패드막은 산화막인 것을 특징으로 하는 반도체 소자의 제조방법
  4. 제2항 또는 제3항에 있어서, 상기 제1 및 제2 버퍼막은 폴리실리콘막인 것을 특징으로 하는 반도체 소자의 제조방법
  5. 제2항 또는 제3항에 있어서, 상기 제1 및 제2버퍼막은 질화막인 것을 특징으로 하는 반도체 소자의 제조방법
  6. 제1항에 있어서, 상기 제1마스크 패턴의 형성단계는, 반도체 기판상부에 N웰 예정 영역이 노출되도록 포토레지스트 패턴을 형성하는 단계; 상기 포토레지스트 패턴을 열처리하여, 수직단부가 경사지도록 플로우시키는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 제조방법
  7. 제6항에 있어서, 상기 열처리 공정은 100 내지 200℃온도에서 진행되는 것을 특징으로 하는 반도체 소자의 제조방법
  8. 제1항에 있어서, 상기 N웰을 형성하는 단계 전 또는 후에, N웰 깊이보다 깊지 않도록 노출된 반도체 가판에 P모스형 펀치 스루 방지형 불순물층을 형성하는 단계; 상기 P모스형 펀치 스루 방지형 불순물층 깊이 보다 깊지 않도록 P모스형 문턱 조절형 불순물층을 형성하는 단계를 부가적으로 포함하는 것을 특징으로하는 반도체 소자의 제조방법
  9. 제1항에 있어서, 상기 제1마스크 패턴을 제거하는 단계 이후에, N웰 영역 상부에 제2마스크 패턴을 형성하는 단계; 노출된 반도체 기판에 P형 매몰층 깊이 보다 깊지 않도록 N모스형 펀치 스루 방지형 불순물층을 형성하는 단계; 노출된 반도체 기판에 N모스형 펀치 스루 방지형 불순물층 깊이 보다 깊지 않도록 N모스용 문턱 전압 조절용 불순물층을 형성하는 단계를 부가적으로 포함하는 반도체 소자의 제조방법
KR1019960026303A 1996-06-29 1996-06-29 반도체 소자의 제조방법 KR100203306B1 (ko)

Priority Applications (6)

Application Number Priority Date Filing Date Title
KR1019960026303A KR100203306B1 (ko) 1996-06-29 1996-06-29 반도체 소자의 제조방법
TW086108266A TW399303B (en) 1996-06-29 1997-06-14 Fabrication method of CMOS device
JP9180661A JPH1065019A (ja) 1996-06-29 1997-06-20 Ｃｍｏｓデバイスの製造方法
US08/882,485 US5963798A (en) 1996-06-29 1997-06-25 Fabrication method of CMOS device having buried implanted layers for lateral isolation (BILLI)
GB9713538A GB2314972A (en) 1996-06-29 1997-06-26 Fabrication method of a CMOS device
DE19727425A DE19727425A1 (de) 1996-06-29 1997-06-27 Verfahren zur Herstellung eines CMOS-Bauelementes

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Application Number Priority Date Filing Date Title
KR1019960026303A KR100203306B1 (ko) 1996-06-29 1996-06-29 반도체 소자의 제조방법

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KR980006254A true KR980006254A (ko) 1998-03-30
KR100203306B1 KR100203306B1 (ko) 1999-06-15

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US (1) US5963798A (ko)
JP (1) JPH1065019A (ko)
KR (1) KR100203306B1 (ko)
DE (1) DE19727425A1 (ko)
GB (1) GB2314972A (ko)
TW (1) TW399303B (ko)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100290884B1 (ko) * 1998-05-04 2001-07-12 김영환 반도체소자및그제조방법
US6211023B1 (en) * 1998-11-12 2001-04-03 United Microelectronics Corp. Method for fabricating a metal-oxide semiconductor transistor
DE69833743T2 (de) 1998-12-09 2006-11-09 Stmicroelectronics S.R.L., Agrate Brianza Herstellungmethode einer integrierte Randstruktur für Hochspannung-Halbleiteranordnungen
KR100275962B1 (ko) * 1998-12-30 2001-02-01 김영환 반도체장치 및 그의 제조방법_
US6333532B1 (en) * 1999-07-16 2001-12-25 International Business Machines Corporation Patterned SOI regions in semiconductor chips
JP4540438B2 (ja) * 2004-09-27 2010-09-08 富士通セミコンダクター株式会社 半導体装置及びその製造方法
US7666721B2 (en) * 2006-03-15 2010-02-23 International Business Machines Corporation SOI substrates and SOI devices, and methods for forming the same
US8154078B2 (en) * 2010-02-17 2012-04-10 Vanguard International Semiconductor Corporation Semiconductor structure and fabrication method thereof

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4810664A (en) * 1986-08-14 1989-03-07 Hewlett-Packard Company Method for making patterned implanted buried oxide transistors and structures
KR950015013B1 (ko) * 1987-10-08 1995-12-21 마쯔시다 덴끼 산교 가부시끼가이샤 반도체 장치 및 그 제조 방법
US5292671A (en) * 1987-10-08 1994-03-08 Matsushita Electric Industrial, Co., Ltd. Method of manufacture for semiconductor device by forming deep and shallow regions
JPH0626219B2 (ja) * 1987-11-05 1994-04-06 シャープ株式会社 イオン注入方法
NL8802219A (nl) * 1988-09-09 1990-04-02 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een siliciumlichaam waarin door ionenimplantaties halfgeleidergebieden worden gevormd.
US5501993A (en) * 1994-11-22 1996-03-26 Genus, Inc. Method of constructing CMOS vertically modulated wells (VMW) by clustered MeV BILLI (buried implanted layer for lateral isolation) implantation

Also Published As

Publication number Publication date
GB9713538D0 (en) 1997-09-03
DE19727425A1 (de) 1998-01-02
KR100203306B1 (ko) 1999-06-15
US5963798A (en) 1999-10-05
GB2314972A (en) 1998-01-14
JPH1065019A (ja) 1998-03-06
TW399303B (en) 2000-07-21

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