KR910020842A - Ldd형의 cmos장치 제조방법 - Google Patents
Ldd형의 cmos장치 제조방법 Download PDFInfo
- Publication number
- KR910020842A KR910020842A KR1019910007539A KR910007539A KR910020842A KR 910020842 A KR910020842 A KR 910020842A KR 1019910007539 A KR1019910007539 A KR 1019910007539A KR 910007539 A KR910007539 A KR 910007539A KR 910020842 A KR910020842 A KR 910020842A
- Authority
- KR
- South Korea
- Prior art keywords
- gate
- layer
- protective layer
- silicon nitride
- cmos device
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 238000000034 method Methods 0.000 claims description 4
- 239000010410 layer Substances 0.000 claims 7
- 239000011241 protective layer Substances 0.000 claims 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims 5
- 125000006850 spacer group Chemical group 0.000 claims 4
- 239000004065 semiconductor Substances 0.000 claims 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 239000002019 doping agent Substances 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도 내지 제10도는 본발명의 원리에 따라 CMOS장치의 제작 공정을 단면적 표시로서 공정순서에 따라 나타낸 도면.
Claims (6)
- 상기 웨이퍼에서 p 및 n-형 영역위에 놓이는 각 게이트를 형성하는 단계, 상기 영역위에 놓이는 게이트-스페이서 구조를 형성하도록 상기 게이트의 각면을 따라 스페이서를 형성하는 단계, 한 전도형의 영역과 소스/드레인 영역이 형성되는 상기 한 전도형 부분위에 놓이는 게이트-스페이서 구조를 덮으며, 또다른 전도형의 영역과 소스/드레인 영역이 형성되는 상기 또다른 전도형의 영역 부분위에 놓이는 게이트-스페이서 구조를 덮지 않고 남기는 제1보호층과 제2보호층위에 놓이는 레지스트층으로 구성되는 마스크를 형성하는 단계, 상기 한 전도형의 도펀트로 또다른 전도형의 영역의 노출 표면부분을 주입하는 단계 및, 상기 제1보호층을 가지며 상기 제1보호층에 의해서 덮히지 않는 게이트-스페이서 구조를 수정하는 단계로 이루어진 반도체 웨이퍼에서 LDD형의 CMOS장치 제조방법
- 제1항에 있어서, 각각의 상기 스페이서는 게이트옆에 실리콘 질화물층과 실리콘 2 산화물층과 인접하는 실리콘 질화물층으로 이루어진 반도체 웨이퍼에서 LDD형의 CMOS장치 제조방법.
- 제2항에 있어서, 상기 마스크의 제1 보호층은 실리콘2 산화물 또는 산화 질화물로 이루어지는 반도체 웨이퍼 LDD형의 CMOS장치의 제조방법.
- 제3항에 있어서, 상기 수정 단계는 게이트 옆의 스페이서에서 실리콘 질화물을 제거하는 것으로 이루어진 반도체 LDD형의 CMOS장치 제조방법.
- 제4항에 있어서, 상기 마스크의 제2층을 제거하는 단계를 포함하는 반도체 LDD형의 CMOS장치의 제조방법.
- 제5항에 있어서, 상기 제1 보호층을 제거한 다음, 게이트의 스페이서에서 실리콘 질화물층을 제거하는 단계를 포함하는 반도체 LDD형의 CMOS장치의 제조방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US52243390A | 1990-05-11 | 1990-05-11 | |
US522,433 | 1990-05-11 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR910020842A true KR910020842A (ko) | 1991-12-20 |
KR100199527B1 KR100199527B1 (ko) | 1999-06-15 |
Family
ID=24080830
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019910007539A KR100199527B1 (ko) | 1990-05-11 | 1991-05-10 | 약하게 도핑된 드레인(ldd)형의 cmos장치제조방법 |
Country Status (5)
Country | Link |
---|---|
US (1) | US5766991A (ko) |
EP (1) | EP0456318B1 (ko) |
JP (1) | JP3007437B2 (ko) |
KR (1) | KR100199527B1 (ko) |
DE (1) | DE69132695T2 (ko) |
Families Citing this family (39)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0799315A (ja) * | 1993-06-22 | 1995-04-11 | Motorola Inc | 半導体デバイスの対向するドープ領域のインターフェースにおけるキャリア濃度を制御する方法 |
JP3426043B2 (ja) * | 1994-09-27 | 2003-07-14 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
US5405791A (en) * | 1994-10-04 | 1995-04-11 | Micron Semiconductor, Inc. | Process for fabricating ULSI CMOS circuits using a single polysilicon gate layer and disposable spacers |
US6720627B1 (en) * | 1995-10-04 | 2004-04-13 | Sharp Kabushiki Kaisha | Semiconductor device having junction depths for reducing short channel effect |
US5844276A (en) * | 1996-12-06 | 1998-12-01 | Advanced Micro Devices, Inc. | CMOS integrated circuit and method for implanting NMOS transistor areas prior to implanting PMOS transistor areas to optimize the thermal diffusivity thereof |
US5989964A (en) * | 1997-03-17 | 1999-11-23 | Advanced Micro Devices, Inc. | Post-spacer LDD implant for shallow LDD transistor |
KR100226733B1 (ko) * | 1997-03-17 | 1999-10-15 | 구본준 | 반도체소자 제조방법 |
US6221709B1 (en) | 1997-06-30 | 2001-04-24 | Stmicroelectronics, Inc. | Method of fabricating a CMOS integrated circuit device with LDD N-channel transistor and non-LDD P-channel transistor |
US6057220A (en) * | 1997-09-23 | 2000-05-02 | International Business Machines Corporation | Titanium polycide stabilization with a porous barrier |
US6087234A (en) * | 1997-12-19 | 2000-07-11 | Texas Instruments - Acer Incorporated | Method of forming a self-aligned silicide MOSFET with an extended ultra-shallow S/D junction |
US5904520A (en) * | 1998-01-05 | 1999-05-18 | Utek Semiconductor Corp. | Method of fabricating a CMOS transistor |
US6004878A (en) * | 1998-02-12 | 1999-12-21 | National Semiconductor Corporation | Method for silicide stringer removal in the fabrication of semiconductor integrated circuits |
US6242354B1 (en) * | 1998-02-12 | 2001-06-05 | National Semiconductor Corporation | Semiconductor device with self aligned contacts having integrated silicide stringer removal and method thereof |
US5989965A (en) * | 1998-02-13 | 1999-11-23 | Sharp Laboratories Of America, Inc. | Nitride overhang structures for the silicidation of transistor electrodes with shallow junction |
EP0951061A3 (en) * | 1998-03-31 | 2003-07-09 | Interuniversitair Microelektronica Centrum Vzw | Method for forming a FET |
US6093594A (en) * | 1998-04-29 | 2000-07-25 | Advanced Micro Devices, Inc. | CMOS optimization method utilizing sacrificial sidewall spacer |
US6127234A (en) * | 1999-01-07 | 2000-10-03 | Advanced Micro Devices, Inc. | Ultra shallow extension formation using disposable spacers |
US6437424B1 (en) * | 1999-03-09 | 2002-08-20 | Sanyo Electric Co., Ltd. | Non-volatile semiconductor memory device with barrier and insulating films |
US6218224B1 (en) * | 1999-03-26 | 2001-04-17 | Advanced Micro Devices, Inc. | Nitride disposable spacer to reduce mask count in CMOS transistor formation |
US5981325A (en) * | 1999-04-26 | 1999-11-09 | United Semiconductor Corp. | Method for manufacturing CMOS |
US6342423B1 (en) | 1999-09-24 | 2002-01-29 | Advanced Micro Devices, Inc. | MOS-type transistor processing utilizing UV-nitride removable spacer and HF etch |
US6472283B1 (en) | 1999-09-24 | 2002-10-29 | Advanced Micro Devices, Inc. | MOS transistor processing utilizing UV-nitride removable spacer and HF etch |
GB2362029A (en) * | 1999-10-27 | 2001-11-07 | Lucent Technologies Inc | Multi-layer structure for MOSFET Spacers |
JP2001168323A (ja) * | 1999-12-06 | 2001-06-22 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
JP2001274263A (ja) * | 2000-03-23 | 2001-10-05 | Sharp Corp | 半導体装置の製造方法及び半導体装置 |
US6350665B1 (en) | 2000-04-28 | 2002-02-26 | Cypress Semiconductor Corporation | Semiconductor structure and method of making contacts and source and/or drain junctions in a semiconductor device |
US6483154B1 (en) | 2000-10-05 | 2002-11-19 | Advanced Micro Devices, Inc. | Nitrogen oxide plasma treatment for reduced nickel silicide bridging |
US6730556B2 (en) * | 2001-12-12 | 2004-05-04 | Texas Instruments Incorporated | Complementary transistors with controlled drain extension overlap |
KR100416628B1 (ko) * | 2002-06-22 | 2004-01-31 | 삼성전자주식회사 | 게이트 스페이서를 포함하는 반도체 소자 제조 방법 |
US6777299B1 (en) | 2003-07-07 | 2004-08-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for removal of a spacer |
KR100567529B1 (ko) * | 2003-12-30 | 2006-04-03 | 주식회사 하이닉스반도체 | 반도체 소자의 제조 방법 |
US7091098B2 (en) * | 2004-04-07 | 2006-08-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device with spacer having batch and non-batch layers |
US7371691B2 (en) * | 2004-07-29 | 2008-05-13 | Texas Instruments Incorporated | Silicon recess improvement through improved post implant resist removal and cleans |
US7858458B2 (en) | 2005-06-14 | 2010-12-28 | Micron Technology, Inc. | CMOS fabrication |
US7541234B2 (en) * | 2005-11-03 | 2009-06-02 | Samsung Electronics Co., Ltd. | Methods of fabricating integrated circuit transistors by simultaneously removing a photoresist layer and a carbon-containing layer on different active areas |
DE102007009916B4 (de) * | 2007-02-28 | 2012-02-23 | Advanced Micro Devices, Inc. | Verfahren zum Entfernen unterschiedlicher Abstandshalter durch einen nasschemischen Ätzprozess |
US7923373B2 (en) | 2007-06-04 | 2011-04-12 | Micron Technology, Inc. | Pitch multiplication using self-assembling materials |
USD852303S1 (en) | 2017-07-10 | 2019-06-25 | Parsons Xtreme Golf, LLC | Golf club head |
USD852305S1 (en) | 2018-04-23 | 2019-06-25 | Parsons Xtreme Golf, LLC | Golf club head |
Family Cites Families (40)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54147789A (en) * | 1978-05-11 | 1979-11-19 | Matsushita Electric Ind Co Ltd | Semiconductor divice and its manufacture |
JPS56157024A (en) * | 1980-05-06 | 1981-12-04 | Fujitsu Ltd | Manufacture of semiconductor device |
US4382827A (en) * | 1981-04-27 | 1983-05-10 | Ncr Corporation | Silicon nitride S/D ion implant mask in CMOS device fabrication |
JPS5952849A (ja) * | 1982-09-20 | 1984-03-27 | Fujitsu Ltd | 半導体装置の製造方法 |
JPS59138379A (ja) * | 1983-01-27 | 1984-08-08 | Toshiba Corp | 半導体装置の製造方法 |
JPS6046804B2 (ja) * | 1983-04-22 | 1985-10-18 | 株式会社東芝 | 半導体装置の製造方法 |
JPS60167461A (ja) * | 1984-02-10 | 1985-08-30 | Hitachi Ltd | 半導体装置の製造方法 |
JPS60241267A (ja) * | 1984-05-16 | 1985-11-30 | Hitachi Ltd | 半導体装置の製造方法 |
EP0173953B1 (en) * | 1984-08-28 | 1991-07-17 | Kabushiki Kaisha Toshiba | Method for manufacturing a semiconductor device having a gate electrode |
JPS61160976A (ja) * | 1985-01-09 | 1986-07-21 | Nec Corp | 半導体装置の製造方法 |
SE453547B (sv) * | 1985-03-07 | 1988-02-08 | Stiftelsen Inst Mikrovags | Forfarande vid framstellning av integrerade kretsar der pa en substratplatta ledare och s k gate-strukturer uppbygges |
JPS61295652A (ja) * | 1985-06-25 | 1986-12-26 | Oki Electric Ind Co Ltd | Cmos型半導体装置の製造方法 |
EP0218408A3 (en) * | 1985-09-25 | 1988-05-25 | Hewlett-Packard Company | Process for forming lightly-doped-grain (ldd) structure in integrated circuits |
US4843023A (en) * | 1985-09-25 | 1989-06-27 | Hewlett-Packard Company | Process for forming lightly-doped-drain (LDD) without extra masking steps |
US4722909A (en) * | 1985-09-26 | 1988-02-02 | Motorola, Inc. | Removable sidewall spacer for lightly doped drain formation using two mask levels |
US4745086A (en) * | 1985-09-26 | 1988-05-17 | Motorola, Inc. | Removable sidewall spacer for lightly doped drain formation using one mask level and differential oxidation |
JPS62118578A (ja) * | 1985-11-18 | 1987-05-29 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
JPS62173763A (ja) * | 1986-01-27 | 1987-07-30 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
JPS62190862A (ja) * | 1986-02-18 | 1987-08-21 | Matsushita Electronics Corp | 相補型mos集積回路の製造方法 |
US4760033A (en) * | 1986-04-08 | 1988-07-26 | Siemens Aktiengesellschaft | Method for the manufacture of complementary MOS field effect transistors in VLSI technology |
JPS6346773A (ja) * | 1986-08-15 | 1988-02-27 | Citizen Watch Co Ltd | Mosトランジスタの製造方法 |
US4744859A (en) * | 1986-10-23 | 1988-05-17 | Vitelic Corporation | Process for fabricating lightly doped drain MOS devices |
US4728617A (en) * | 1986-11-04 | 1988-03-01 | Intel Corporation | Method of fabricating a MOSFET with graded source and drain regions |
JPH0834310B2 (ja) * | 1987-03-26 | 1996-03-29 | 沖電気工業株式会社 | 半導体装置の製造方法 |
JPS63219152A (ja) * | 1987-03-06 | 1988-09-12 | Matsushita Electronics Corp | Mos集積回路の製造方法 |
JP2670265B2 (ja) * | 1987-03-27 | 1997-10-29 | 株式会社東芝 | Cmos半導体装置の製造方法 |
US4764477A (en) * | 1987-04-06 | 1988-08-16 | Motorola, Inc. | CMOS process flow with small gate geometry LDO N-channel transistors |
US4850007A (en) * | 1987-06-25 | 1989-07-18 | American Telephone And Telegraph Company | Telephone toll service with advertising |
US4753898A (en) * | 1987-07-09 | 1988-06-28 | Motorola, Inc. | LDD CMOS process |
US4818715A (en) * | 1987-07-09 | 1989-04-04 | Industrial Technology Research Institute | Method of fabricating a LDDFET with self-aligned silicide |
US4837180A (en) * | 1987-07-09 | 1989-06-06 | Industrial Technology Research Institute | Ladder gate LDDFET |
JPS6417552A (en) * | 1987-07-11 | 1989-01-20 | Kiyoyuki Tomidokoro | Emergency telephone number calling and informing telephone set |
DE3723084A1 (de) * | 1987-07-13 | 1989-01-26 | Merck Patent Gmbh | Loesungsmittel fuer die wasserbestimmung nach karl-fischer |
JPS6484659A (en) * | 1987-09-28 | 1989-03-29 | Toshiba Corp | Manufacture of semiconductor device |
US4818714A (en) * | 1987-12-02 | 1989-04-04 | Advanced Micro Devices, Inc. | Method of making a high performance MOS device having LDD regions with graded junctions |
US4855247A (en) * | 1988-01-19 | 1989-08-08 | Standard Microsystems Corporation | Process for fabricating self-aligned silicide lightly doped drain MOS devices |
US4868617A (en) * | 1988-04-25 | 1989-09-19 | Elite Semiconductor & Sytems International, Inc. | Gate controllable lightly doped drain mosfet devices |
GB8820058D0 (en) * | 1988-08-24 | 1988-09-28 | Inmos Ltd | Mosfet & fabrication method |
US4876213A (en) * | 1988-10-31 | 1989-10-24 | Motorola, Inc. | Salicided source/drain structure |
US5082794A (en) * | 1989-02-13 | 1992-01-21 | Motorola, Inc. | Method of fabricating mos transistors using selective polysilicon deposition |
-
1991
- 1991-05-06 DE DE69132695T patent/DE69132695T2/de not_active Expired - Fee Related
- 1991-05-06 EP EP91201066A patent/EP0456318B1/en not_active Expired - Lifetime
- 1991-05-08 JP JP3102830A patent/JP3007437B2/ja not_active Expired - Fee Related
- 1991-05-10 KR KR1019910007539A patent/KR100199527B1/ko not_active IP Right Cessation
-
1996
- 1996-08-29 US US08/705,072 patent/US5766991A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0456318A3 (en) | 1992-03-18 |
EP0456318A2 (en) | 1991-11-13 |
DE69132695D1 (de) | 2001-09-27 |
KR100199527B1 (ko) | 1999-06-15 |
US5766991A (en) | 1998-06-16 |
EP0456318B1 (en) | 2001-08-22 |
JPH04229650A (ja) | 1992-08-19 |
JP3007437B2 (ja) | 2000-02-07 |
DE69132695T2 (de) | 2002-06-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR910020842A (ko) | Ldd형의 cmos장치 제조방법 | |
KR910019246A (ko) | 자동배열된 실리사이드 cmos 처리에서의 esd 보호용 n- 채널 클램프 | |
KR870000763A (ko) | 반도체 장치 및 그 제조방법 | |
KR920022537A (ko) | 감소된 기생 캐패시턴스를 갖는 보호형 프로그램가능 트랜지스터 및 그의 제조방법 | |
KR980700683A (ko) | 비대칭 약간 도프된 드레인 (ldd) mos 소자의 제조방법 (method for fabricating asymmetrical ldd mos devices) | |
KR890003038A (ko) | 페데스탈 구조를 가지는 반도체 제조 공정 | |
KR930005257A (ko) | 박막 전계효과 소자 및 그의 제조방법 | |
KR950030278A (ko) | 절연게이트 전계 효과 트랜지스터의 제조방법 | |
KR960002884A (ko) | 바이폴라 트랜지스터 및 mos 트랜지스터를 포함한 반도체 장치 제조 방법 | |
KR970054083A (ko) | 상보형 모스(cmos) 트랜지스터 및 그 제조방법 | |
KR920022562A (ko) | 반도체 집적 회로 제조방법 | |
KR930005106A (ko) | 마스크롬의 제조방법 | |
KR900015311A (ko) | 반도체장치 및 그 제조방법 | |
KR970030676A (ko) | 반도체 장치 및 그 제조 방법 | |
KR960002889A (ko) | 반도체 장치 및 그 제조방법 | |
KR970054431A (ko) | 모스 트랜지스터 및 그 제조방법 | |
KR910001876A (ko) | 반도체 장치 제조방법 | |
KR920020594A (ko) | Ldd 트랜지스터의 구조 및 제조방법 | |
KR930003430A (ko) | 반도체 장치 및 그 제조방법 | |
KR950021531A (ko) | 반도체장치 및 그 제조방법 | |
KR920020738A (ko) | 씨모스의 제조방법 | |
KR920013601A (ko) | 모스 트랜지스터 제조방법 | |
KR900003999A (ko) | 반도체 장치 및 그 제조 방법 | |
KR920013767A (ko) | 핫 캐리어 방지 트랜지스터의 제조방법 | |
KR970018691A (ko) | 모스 트랜지스터 및 그 제조방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20050304 Year of fee payment: 7 |
|
LAPS | Lapse due to unpaid annual fee |