KR910020842A - Ldd형의 cmos장치 제조방법 - Google Patents

Ldd형의 cmos장치 제조방법 Download PDF

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Publication number
KR910020842A
KR910020842A KR1019910007539A KR910007539A KR910020842A KR 910020842 A KR910020842 A KR 910020842A KR 1019910007539 A KR1019910007539 A KR 1019910007539A KR 910007539 A KR910007539 A KR 910007539A KR 910020842 A KR910020842 A KR 910020842A
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gate
layer
protective layer
silicon nitride
cmos device
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KR1019910007539A
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KR100199527B1 (ko
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테-이첸 제임스
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프레데릭 얀 스미트
엔.브이.필립스 글로아이람펜파브리켄
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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Abstract

내용 없음

Description

LDD형의 CMOS장치 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도 내지 제10도는 본발명의 원리에 따라 CMOS장치의 제작 공정을 단면적 표시로서 공정순서에 따라 나타낸 도면.

Claims (6)

  1. 상기 웨이퍼에서 p 및 n-형 영역위에 놓이는 각 게이트를 형성하는 단계, 상기 영역위에 놓이는 게이트-스페이서 구조를 형성하도록 상기 게이트의 각면을 따라 스페이서를 형성하는 단계, 한 전도형의 영역과 소스/드레인 영역이 형성되는 상기 한 전도형 부분위에 놓이는 게이트-스페이서 구조를 덮으며, 또다른 전도형의 영역과 소스/드레인 영역이 형성되는 상기 또다른 전도형의 영역 부분위에 놓이는 게이트-스페이서 구조를 덮지 않고 남기는 제1보호층과 제2보호층위에 놓이는 레지스트층으로 구성되는 마스크를 형성하는 단계, 상기 한 전도형의 도펀트로 또다른 전도형의 영역의 노출 표면부분을 주입하는 단계 및, 상기 제1보호층을 가지며 상기 제1보호층에 의해서 덮히지 않는 게이트-스페이서 구조를 수정하는 단계로 이루어진 반도체 웨이퍼에서 LDD형의 CMOS장치 제조방법
  2. 제1항에 있어서, 각각의 상기 스페이서는 게이트옆에 실리콘 질화물층과 실리콘 2 산화물층과 인접하는 실리콘 질화물층으로 이루어진 반도체 웨이퍼에서 LDD형의 CMOS장치 제조방법.
  3. 제2항에 있어서, 상기 마스크의 제1 보호층은 실리콘2 산화물 또는 산화 질화물로 이루어지는 반도체 웨이퍼 LDD형의 CMOS장치의 제조방법.
  4. 제3항에 있어서, 상기 수정 단계는 게이트 옆의 스페이서에서 실리콘 질화물을 제거하는 것으로 이루어진 반도체 LDD형의 CMOS장치 제조방법.
  5. 제4항에 있어서, 상기 마스크의 제2층을 제거하는 단계를 포함하는 반도체 LDD형의 CMOS장치의 제조방법.
  6. 제5항에 있어서, 상기 제1 보호층을 제거한 다음, 게이트의 스페이서에서 실리콘 질화물층을 제거하는 단계를 포함하는 반도체 LDD형의 CMOS장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910007539A 1990-05-11 1991-05-10 약하게 도핑된 드레인(ldd)형의 cmos장치제조방법 KR100199527B1 (ko)

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US52243390A 1990-05-11 1990-05-11
US522,433 1990-05-11

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KR910020842A true KR910020842A (ko) 1991-12-20
KR100199527B1 KR100199527B1 (ko) 1999-06-15

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US (1) US5766991A (ko)
EP (1) EP0456318B1 (ko)
JP (1) JP3007437B2 (ko)
KR (1) KR100199527B1 (ko)
DE (1) DE69132695T2 (ko)

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JP3007437B2 (ja) 2000-02-07
DE69132695T2 (de) 2002-06-13
US5766991A (en) 1998-06-16
EP0456318A3 (en) 1992-03-18
KR100199527B1 (ko) 1999-06-15
EP0456318B1 (en) 2001-08-22
JPH04229650A (ja) 1992-08-19
EP0456318A2 (en) 1991-11-13
DE69132695D1 (de) 2001-09-27

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