KR20150119350A - 반도체 장치, 반도체 장치의 제조 방법 - Google Patents
반도체 장치, 반도체 장치의 제조 방법 Download PDFInfo
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- KR20150119350A KR20150119350A KR1020157025408A KR20157025408A KR20150119350A KR 20150119350 A KR20150119350 A KR 20150119350A KR 1020157025408 A KR1020157025408 A KR 1020157025408A KR 20157025408 A KR20157025408 A KR 20157025408A KR 20150119350 A KR20150119350 A KR 20150119350A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 title description 11
- 239000000853 adhesive Substances 0.000 claims abstract description 57
- 230000001070 adhesive effect Effects 0.000 claims abstract description 57
- 230000003746 surface roughness Effects 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims description 35
- 239000000463 material Substances 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 3
- 235000012431 wafers Nutrition 0.000 description 33
- 239000000155 melt Substances 0.000 description 19
- 230000000630 rising effect Effects 0.000 description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- 238000002844 melting Methods 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 229910003460 diamond Inorganic materials 0.000 description 2
- 239000010432 diamond Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000003754 machining Methods 0.000 description 2
- 238000009281 ultraviolet germicidal irradiation Methods 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 230000009194 climbing Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Abstract
본원의 발명과 관련되는 반도체 장치는, 실장 기판과, 상기 실장 기판에 도포된 접착제와, 상기 접착제에 의해 하면이 상기 실장 기판과 접착된 디바이스를 구비하고, 상기 디바이스의 측면 상부는 상기 디바이스의 측면 하부보다 표면 거칠기가 작은 것을 특징으로 한다.
Description
본 발명은, 다이싱한 디바이스를 접착제로 실장 기판에 고정하는 반도체 장치 및 그 반도체 장치의 제조 방법에 관한 것이다.
웨이퍼 등을 세로 및 가로로 커트하여 개개의 디바이스(칩)로 잘라 나누는 작업은 다이싱이라고 불리고 있다. 다이싱에는 주로 3개의 방법이 있다. 제 1 방법으로서, 다이아몬드 블레이드라고 불리는 매우 얇은 원형 칼날을 고속 회전시켜 웨이퍼를 커트하는 블레이드 다이싱이 있다.
제 2 방법으로서, 다이아몬드의 모서리를 사용하여 웨이퍼에 상처를 내고, 그 후 웨이퍼에 기계적 응력을 가하여 웨이퍼를 커트하는 스크라이브 브레이크가 있다. 제 3 방법으로서, 레이저 광을 이용하여 웨이퍼를 커트하는 레이저 다이싱이 있다. 레이저 다이싱은, 레이저 에너지를 집중시켜 웨이퍼 재료의 일부를 승화, 용융, 또는 전리시키는 것에 의해, 웨이퍼를 개개의 디바이스로 분리하는 것이다.
특허 문헌 1에는 레이저 다이싱과 블레이드 다이싱을 조합한 다이싱 기술이 개시되어 있다. 이 기술은, 웨이퍼의 다이싱 스트리트를 따라서 레이저 광선을 조사하여 가공 홈을 형성한 후에, 블레이드를 이용하여 해당 가공 홈을 따라서 웨이퍼를 절삭하는 것이다.
(선행 기술 문헌)
(특허 문헌)
(특허 문헌 1) 일본 특허 공개 2012-4478호 공보
레이저 다이싱은, 블레이드 다이싱 및 스크라이브 브레이크와 비교하여 스루풋이 높고 또한 수율이 높다. 또한, 레이저 다이싱은, 블레이드 다이싱보다 커트 폭(다이싱 스트리트 폭)을 축소할 수 있으므로 사용되는 디바이스 수를 증가시킬 수 있다.
그러나, 레이저 다이싱에 의해 웨이퍼 등을 다이싱하면, 디바이스의 측면에 용융물이 형성된다. 디바이스 하면을 접착제에 접촉시켜 다이 본딩하면, 접착제가 디바이스 측면의 용융물을 따라서 올라가 디바이스 상면에 도달하는 문제가 있었다. 이것에 의해 디바이스 상면의 전극 패드가 오염되어 전극 패드와 와이어의 접합 강도를 저하시키는 문제가 있었다. 또한, 도전성의 접착제를 이용한 경우, 디바이스 상면으로 올라간 접착제가 원인이 되어 전기적 쇼트가 일어나는 문제가 있었다.
또한, 특허 문헌 1에 개시된 기술에서는, 웨이퍼의 대부분을 블레이드 다이싱으로 절삭하고 있으므로, 블레이드의 이동 속도를 빠르게 할 수 없어 생산성을 높일 수 없는 문제가 있었다.
본 발명은, 상술한 바와 같은 과제를 해결하기 위해 이루어진 것으로, 생산성을 높이면서, 접착제가 올라가는 것을 방지할 수 있는 반도체 장치와 그 반도체 장치의 제조 방법을 제공하는 것을 목적으로 한다.
본원의 발명과 관련되는 반도체 장치는, 실장 기판과, 그 실장 기판에 도포된 접착제와, 그 접착제에 의해 하면이 그 실장 기판과 접착된 디바이스를 구비하고, 그 디바이스의 측면 상부는 그 디바이스의 측면 하부보다 표면 거칠기가 작은 것을 특징으로 한다.
본원의 발명과 관련되는 반도체 장치의 제조 방법은, 레이저 다이싱에 의해 웨이퍼에 관통 구멍을 형성하고 개개의 디바이스로 분리하는 레이저 다이싱 공정과, 그 레이저 다이싱 공정에서 그 디바이스의 측면에 형성된 용융물을 블레이드 또는 에칭에 의해 제거하는 제거 공정과, 그 제거 공정 후에, 접착제에 의해 실장 기판과 그 디바이스의 하면을 접착하는 다이 본드 공정과, 그 접착제를 경화시키는 접착제 경화 공정을 구비한 것을 특징으로 한다.
본 발명에 의하면, 생산성을 높이면서, 접착제가 올라가는 것을 방지할 수 있는 반도체 장치를 제공할 수 있다.
도 1은 본 발명의 실시의 형태 1과 관련되는 반도체 장치의 단면도이다.
도 2는 레이저 다이싱의 모습을 나타내는 웨이퍼의 단면도이다.
도 3은 용융물을 제거하는 것을 나타내는 단면도이다.
도 4는 다이 본드 공정을 나타내는 단면도이다.
도 5는 레이저 다이싱 후의 디바이스 측면의 표면 거칠기 Rz와, 블레이드 다이싱 후의 디바이스 측면의 표면 거칠기 Rz를 비교하는 사진이다.
도 6은 디바이스 측면의 표면 거칠기 Rz와 접착제가 디바이스 상면까지 올라갈 때까지 요하는 시간을 다이싱 방식마다 나타내는 표이다.
도 7은 본 발명의 실시의 형태 2와 관련되는 반도체 장치의 단면도이다.
도 8은 웨이퍼에 홈을 형성하는 것을 나타내는 웨이퍼의 단면도이다.
도 9는 레이저 다이싱의 모습을 나타내는 웨이퍼의 단면도이다.
도 2는 레이저 다이싱의 모습을 나타내는 웨이퍼의 단면도이다.
도 3은 용융물을 제거하는 것을 나타내는 단면도이다.
도 4는 다이 본드 공정을 나타내는 단면도이다.
도 5는 레이저 다이싱 후의 디바이스 측면의 표면 거칠기 Rz와, 블레이드 다이싱 후의 디바이스 측면의 표면 거칠기 Rz를 비교하는 사진이다.
도 6은 디바이스 측면의 표면 거칠기 Rz와 접착제가 디바이스 상면까지 올라갈 때까지 요하는 시간을 다이싱 방식마다 나타내는 표이다.
도 7은 본 발명의 실시의 형태 2와 관련되는 반도체 장치의 단면도이다.
도 8은 웨이퍼에 홈을 형성하는 것을 나타내는 웨이퍼의 단면도이다.
도 9는 레이저 다이싱의 모습을 나타내는 웨이퍼의 단면도이다.
본 발명의 실시의 형태와 관련되는 반도체 장치와 반도체 장치의 제조 방법에 대하여 도면을 참조하여 설명한다. 동일한 또는 대응하는 구성 요소에는 동일한 부호를 붙이고, 설명의 반복을 생략하는 경우가 있다.
실시의 형태 1.
도 1은 본 발명의 실시의 형태 1과 관련되는 반도체 장치의 단면도이다. 반도체 장치(10)는 실장 기판(12)을 구비하고 있다. 실장 기판(12)에는 접착제(14)가 도포되어 있다. 접착제(14)에 의해 실장 기판(12)과 디바이스(16)의 하면이 접착하고 있다. 디바이스(16)는 예컨대 GaAs 등의 화합물 반도체로 형성되어 있다. 디바이스(16)의 상면은 전극 패드(18)가 형성된 능동 영역으로 되어 있다.
디바이스(16)의 측면 상부(16A)에는 표면 거칠기 Rz가 1.0㎛ 이하인 다이싱 흔적이 형성되어 있다. 디바이스(16)의 측면 하부(16B)에는 레이저 다이싱에 의해 GaAs가 용융되어 생긴 용융물(20)이 형성되어 있다. 용융물(20)은 레이저 다이싱에 의한 다이싱 흔적이다. 용융물(20)은 미소한 크랙을 갖는 다공질(porous)이기 때문에 디바이스(16)의 측면 하부(16B)는 표면 거칠기 Rz가 4.0㎛ 이상인 거친 면으로 되어 있다.
접착제(14)의 일부(14a)는, 표면 거칠기 Rz가 큰 측면 하부(16B)를 올라가고 있다. 그렇지만 접착제(14)의 일부(14a)는, 표면 거칠기 Rz가 작은 측면 상부(16A)에는 도달하고 있지 않다.
반도체 장치(10)의 제조 방법을 설명한다. 우선 웨이퍼에 레이저 다이싱을 실시한다. 도 2는 레이저 다이싱의 모습을 나타내는 웨이퍼의 단면도이다. 레이저 장치(50) 내에서 증폭된 뒤에 방사되는 레이저 광(52)으로 웨이퍼(60)를 다이싱한다. 레이저 다이싱에 의해 웨이퍼(60)의 다이싱 스트리트를 따라서 관통 구멍(54, 56)을 형성하고 개개의 디바이스(62, 16, 64)로 분리한다. 이 공정을 레이저 다이싱 공정이라고 칭한다. 또 주지와 같이, 웨이퍼(60)의 하면에는 다이싱 테이프(70)를 붙여 레이저 다이싱 공정을 실시한다.
각 디바이스의 측면에는 레이저 다이싱을 할 때에 생긴 용융물(20A)이 형성되어 있다. 관통 구멍(54)의 폭과 그 양측의 용융물(20A)의 폭의 합은 x1이다. x1은 예컨대 10~20㎛의 범위에 있다.
그 다음에, 레이저 다이싱 공정에서 디바이스의 측면에 형성된 용융물(20A)을 블레이드에 의해 제거한다. 이 공정을 제거 공정이라고 칭한다. 도 3은 용융물을 제거하는 것을 나타내는 단면도이다. 폭이 x1인 블레이드(100)를 관통 구멍(54)을 따라서 지면 앞 방향(또는 안쪽 방향)으로 보내 용융물(20A)을 제거한다. 이것에 의해 측면 상부(16A)에 블레이드(100)에 의한 다이싱 흔적을 형성하여, 측면 상부(16A)의 표면 거칠기 Rz를 1.0㎛ 이하로 한다. 여기서는, 용융물(20A) 전부를 제거하지 않고서 측면 하부에 용융물(20)을 남긴다.
그 다음에, 제거 공정 후에, 접착제에 의해 실장 기판과 디바이스의 하면을 접착한다. 이 공정을 다이 본드 공정이라고 칭한다. 도 4는 다이 본드 공정을 나타내는 단면도이다. 접착제(14)는 도전성을 갖는 Ag 페이스트이지만, 예컨대 액상 또는 필름 형상의 재료로 형성하더라도 좋다.
그 다음에, 다이 본드 공정 종료로부터 일정한 「대기 시간」 경과 후에 접착제를 경화시킨다. 이 공정을 접착제 경화 공정이라고 칭한다. 접착제 경화 공정에서는, 가열 또는 UV 조사에 의해 접착제(14)를 경화시킨다. 또, 접착제 경화 공정 후에 전극 패드(18)에 적절하게 와이어 본딩을 실시한다.
도 5는 레이저 다이싱 후의 디바이스 측면의 표면 거칠기 Rz와, 블레이드 다이싱 후의 디바이스 측면의 표면 거칠기 Rz를 비교하는 사진이다. 레이저 다이싱 A~D에는, 발진 주파수가 상이한 4종류의 발진기를 이용하여 레이저 다이싱했을 때의 측면 상태와 표면 거칠기가 나타나 있다. 레이저 다이싱에서는 디바이스 측면의 표면 거칠기 Rz가 4~12㎛로 되어 있다.
블레이드 다이싱에서는 디바이스 측면의 표면 거칠기 Rz는 1㎛ 이하였다. 따라서, 블레이드 다이싱으로 형성한 측면 상부(16A)의 표면 거칠기 Rz는 1.0㎛ 이하이고, 레이저 다이싱으로 형성한 측면 하부(16B)의 표면 거칠기 Rz는 4.0㎛ 이상이다.
도 6은 디바이스 측면의 표면 거칠기 Rz와 접착제가 디바이스 상면까지 올라갈 때까지 요하는 시간을 다이싱 방식마다 나타내는 표이다. 레이저 다이싱의 경우는, 디바이스 측면의 표면 거칠기 Rz가 크기 때문에 접착제가 디바이스 상면까지 올라가는데 요하는 시간이 짧다. 한편, 블레이드 다이싱 또는 스크라이브 브레이크에서는, 디바이스 측면의 표면 거칠기 Rz가 작기 때문에 접착제가 디바이스 상면까지 올라가는데 요하는 시간이 길다.
본 발명의 실시의 형태 1과 관련되는 반도체 장치(10)에 의하면 디바이스의 측면 상부(16A)의 표면 거칠기 Rz가 1.0㎛ 이하로 되어 있다. 따라서, 다이 본드 공정 종료로부터 접착제 경화 공정까지의 대기 시간을 길게 하더라도, 접착제(14)가 디바이스 측면을 올라가 디바이스 상면에 도달하는 것을 방지할 수 있다. 대기 시간을 길게 마련하는 것에 의해, 생산 효율이 좋은 뱃치(batch) 처리를 채용할 수 있다.
또한, 측면 상부(16A)의 표면 거칠기 Rz를 작게 했으므로, 접착제(14)의 양이 크게 달라졌다고 하더라도 접착제(14)가 디바이스 상면에 도달하는 것을 방지할 수 있다. 이와 같이, 측면 상부(16A)에 의해 접착제(14)가 올라가는 것을 방지할 수 있으므로, 접착제의 선택지가 넓어진다. 예컨대, 기능성이 높은 열전도 접착제, 접합 강도를 높일 수 있는 접착제, 습윤성이 높은 접착제, 또는 저점도의 접착제를 이용할 수 있다.
블레이드 다이싱으로 웨이퍼를 풀 커트하고자 하면, 블레이드의 이동 속도를 빠르게 할 수 없어 생산성을 높일 수 없다. 그런데, 본 발명의 실시의 형태 1과 관련되는 반도체 장치의 제조 방법에서는, 우선 고속 다이싱이 가능한 레이저 다이싱으로 웨이퍼를 풀 커트하고, 그 후 블레이드(100)로 용융물(20A)의 일부를 제거한다. 따라서, 블레이드로 웨이퍼를 풀 커트하는 것보다 단시간에 다이싱을 끝낼 수 있으므로, 생산성을 높일 수 있다. 또, 측면 상부의 용융물만 제거하는 것은, 용융물 전체를 제거하는 경우보다 처리를 고속화하기 위해서, 또한 블레이드의 마모량 저감 및 블레이드 교환 작업의 빈도를 저감하기 위해서이다.
그런데, 블레이드 다이싱 방식의 경우, 필요한 다이싱 스트리트의 폭은 50~100㎛ 정도인 경우가 많다. 그런데, 본 발명의 레이저 다이싱에서는 블레이드의 폭 x1을 10~20㎛의 범위 내로 할 수 있으므로, 다이싱 스트리트의 폭을 축소하여 사용되는 디바이스 수를 증가시킬 수 있다.
측면 상부(16A)와 측면 하부(16B)의 표면 거칠기 Rz는 상기의 값으로 한정되지 않는다. 본 발명의 실시의 형태 1과 관련되는 반도체 장치의 제조 방법을 이용하여, 측면 상부(16A)의 표면 거칠기를 측면 하부(16B)의 표면 거칠기보다 작게 하는 한 접착제(14)가 올라가는 것을 방지할 수 있다.
본 발명의 실시의 형태 1과 관련되는 디바이스는, GaAs로 한정되지 않고 여러 가지의 재료를 채용할 수 있다. 예컨대 디바이스를 세라믹으로 형성하더라도 좋다. 용융물(20)은 블레이드(100)로 제거했지만, 웨트 에칭 또는 드라이 에칭으로 제거하더라도 좋다. 제거 공정에서는 디바이스의 측면 상부의 용융물을 제거했지만, 디바이스의 측면 전체의 용융물을 제거하더라도 좋다. 접착제는 실장 기판과 디바이스를 접착할 수 있는 것이면 되고, 도전성의 재료로 한정되지 않는다. 또, 이들의 변형은 이하의 실시의 형태 2에 대해서도 응용할 수 있다.
실시의 형태 2.
본 발명의 실시의 형태 2와 관련되는 반도체 장치와 반도체 장치의 제조 방법은, 실시의 형태 1과의 공통점이 많으므로 실시의 형태 1과의 차이점을 중심으로 설명한다. 도 7은 본 발명의 실시의 형태 2와 관련되는 반도체 장치의 단면도이다. 이 반도체 장치는 접착제(14)에 의해 디바이스(200)의 하면이 실장 기판(12)에 고정된 것이다.
디바이스(200)의 측면 상부(200A)는 경사면으로 되어 있다. 측면 상부(200A)에는 표면 거칠기 Rz가 1.0㎛ 이하인 다이싱 흔적이 형성되어 있다. 측면 하부(200B)에는, 레이저 다이싱에 의해 GaAs가 용융되어 생긴 용융물(20)이 형성되어 있다. 용융물(20)은 레이저 다이싱에 의한 다이싱 흔적이다. 그 때문에, 측면 하부(200B)는 표면 거칠기 Rz가 4.0㎛ 이상인 거친 면으로 되어 있다.
본 발명의 실시의 형태 2와 관련되는 반도체 장치의 제조 방법을 설명한다. 우선 웨이퍼에 홈을 형성한다. 도 8은 웨이퍼에 홈을 형성하는 것을 나타내는 웨이퍼의 단면도이다. 블레이드(100)에 의해 웨이퍼(60)에 홈(102)을 형성한다. 홈(102)은 다이싱 스트리트를 따라서 형성한다.
그 다음에, 레이저 다이싱을 행한다. 도 9는 레이저 다이싱의 모습을 나타내는 웨이퍼의 단면도이다. 평면에서 볼 때 홈(102)이 형성된 부분을, 홈(102)의 일부를 남기면서 레이저 다이싱하여 관통 구멍(201, 202)을 형성한다. 이것에 의해 웨이퍼를 개개의 디바이스(200, 204, 206)로 분리한다. 이 공정을 레이저 다이싱 공정이라고 칭한다. 레이저 다이싱에 의해 측면 하부(200B)에는 용융물(20)이 형성된다.
그 다음에, 접착제(14)에 의해 실장 기판(12)과 디바이스(200)의 하면을 접착한다. 이 공정은 다이 본드 공정이다. 그 다음에, 대기 시간을 거쳐, 접착제 경화 공정으로 진행한다. 접착제 경화 공정에서는 가열 또는 UV 조사에 의해 접착제(14)를 경화시킨다. 그 다음에, 적절히 와이어 본드 공정을 실시한다.
본 발명의 실시의 형태 2와 관련되는 반도체 장치는, 우선 블레이드(100)로 홈(102)을 형성하는 것에 의해 표면 거칠기가 작은 측면 상부(200A)를 형성한다. 그 다음에, 측면 상부(200A)를 남기면서, 레이저 다이싱에 의해 개개의 디바이스로 분리한다. 따라서, 측면 상부(200A)의 표면 거칠기를 낮게 할 수 있으므로, 접착제가 올라가는 것을 방지할 수 있다. 또, 블레이드(100)가 아닌 에칭에 의해 홈(102)을 형성하더라도 좋다.
10 : 반도체 장치
12 : 실장 기판
14 : 접착제
14a : 접착제의 일부
16 : 디바이스
16A : 측면 상부
16B : 측면 하부
18 : 전극 패드
20, 20A : 용융물
50 : 레이저 장치
52 : 레이저 광
54, 56 : 관통 구멍
60 : 웨이퍼
70 : 다이싱 테이프
100 : 블레이드
102 : 홈
200 : 디바이스
200A : 측면 상부
200B : 측면 하부
201, 202 : 관통 구멍
12 : 실장 기판
14 : 접착제
14a : 접착제의 일부
16 : 디바이스
16A : 측면 상부
16B : 측면 하부
18 : 전극 패드
20, 20A : 용융물
50 : 레이저 장치
52 : 레이저 광
54, 56 : 관통 구멍
60 : 웨이퍼
70 : 다이싱 테이프
100 : 블레이드
102 : 홈
200 : 디바이스
200A : 측면 상부
200B : 측면 하부
201, 202 : 관통 구멍
Claims (5)
- 실장 기판과,
상기 실장 기판에 도포된 접착제와,
상기 접착제에 의해 하면이 상기 실장 기판과 접착된 디바이스
를 구비하고,
상기 디바이스의 측면 상부는 상기 디바이스의 측면 하부보다 표면 거칠기가 작은
것을 특징으로 하는 반도체 장치.
- 제 1 항에 있어서,
상기 디바이스의 측면 상부에는 표면 거칠기 Rz가 1.0㎛ 이하인 다이싱 흔적이 형성되고,
상기 디바이스의 측면 하부에는 표면 거칠기 Rz가 4.0㎛ 이상인 다이싱 흔적이 형성된
것을 특징으로 하는 반도체 장치.
- 레이저 다이싱에 의해 웨이퍼에 관통 구멍을 형성하고 개개의 디바이스로 분리하는 레이저 다이싱 공정과,
상기 레이저 다이싱 공정에서 상기 디바이스의 측면에 형성된 용융물을 블레이드 또는 에칭에 의해 제거하는 제거 공정과,
상기 제거 공정 후에, 접착제에 의해 실장 기판과 상기 디바이스의 하면을 접착하는 다이 본드 공정과,
상기 접착제를 경화시키는 접착제 경화 공정
을 구비한 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제 3 항에 있어서,
상기 제거 공정에서는, 상기 디바이스의 측면 상부에 형성된 용융물만을 제거하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 블레이드 또는 에칭에 의해 웨이퍼에 홈을 형성하는 공정과,
평면에서 볼 때 상기 홈이 형성된 부분을, 상기 홈의 일부를 남기면서 레이저 다이싱하여 관통 구멍을 형성하고, 상기 웨이퍼를 개개의 디바이스로 분리하는 레이저 다이싱 공정과,
접착제에 의해 실장 기판과 상기 디바이스의 하면을 접착하는 다이 본드 공정과,
상기 접착제를 경화시키는 접착제 경화 공정
을 구비한 것을 특징으로 하는 반도체 장치의 제조 방법.
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US11233029B2 (en) | 2022-01-25 |
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WO2014167745A1 (ja) | 2014-10-16 |
TWI511239B (zh) | 2015-12-01 |
CN105103278B (zh) | 2018-11-27 |
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EP2985785A1 (en) | 2016-02-17 |
EP2985785A4 (en) | 2017-01-11 |
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TW201440179A (zh) | 2014-10-16 |
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