KR20060054104A - 배선에 접속된 높은 전기적인 접속 신뢰도의 관통 비아를갖는 기판 및 그 제조 방법 - Google Patents

배선에 접속된 높은 전기적인 접속 신뢰도의 관통 비아를갖는 기판 및 그 제조 방법 Download PDF

Info

Publication number
KR20060054104A
KR20060054104A KR1020050098430A KR20050098430A KR20060054104A KR 20060054104 A KR20060054104 A KR 20060054104A KR 1020050098430 A KR1020050098430 A KR 1020050098430A KR 20050098430 A KR20050098430 A KR 20050098430A KR 20060054104 A KR20060054104 A KR 20060054104A
Authority
KR
South Korea
Prior art keywords
layer
substrate
hole
wiring
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1020050098430A
Other languages
English (en)
Korean (ko)
Inventor
다카하루 야마노
Original Assignee
신꼬오덴기 고교 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 신꼬오덴기 고교 가부시키가이샤 filed Critical 신꼬오덴기 고교 가부시키가이샤
Publication of KR20060054104A publication Critical patent/KR20060054104A/ko
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/007—Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H05K3/4605—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated made from inorganic insulating material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0261—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias characterised by the filling method or the material of the conductive fill
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203—Fillers and particles
    • H05K2201/0206—Materials
    • H05K2201/0236—Plating catalyst as filler in insulating material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09563—Metal filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09581—Applying an insulating coating on the walls of holes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10378—Interposers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0723—Electroplating, e.g. finish plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1105—Heating or thermal processing not related to soldering, firing, curing or laminating, e.g. for shaping the substrate or during finish plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
    • H05K2203/1377—Protective layers
    • H05K2203/1383—Temporary protective insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4661—Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1020050098430A 2004-11-08 2005-10-19 배선에 접속된 높은 전기적인 접속 신뢰도의 관통 비아를갖는 기판 및 그 제조 방법 Withdrawn KR20060054104A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2004323939A JP3987521B2 (ja) 2004-11-08 2004-11-08 基板の製造方法
JPJP-P-2004-00323939 2004-11-08

Publications (1)

Publication Number Publication Date
KR20060054104A true KR20060054104A (ko) 2006-05-22

Family

ID=35784728

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020050098430A Withdrawn KR20060054104A (ko) 2004-11-08 2005-10-19 배선에 접속된 높은 전기적인 접속 신뢰도의 관통 비아를갖는 기판 및 그 제조 방법

Country Status (7)

Country Link
US (2) US20060096781A1 (enExample)
EP (1) EP1656006B1 (enExample)
JP (1) JP3987521B2 (enExample)
KR (1) KR20060054104A (enExample)
CN (1) CN100517678C (enExample)
DE (1) DE602005004586T2 (enExample)
TW (1) TWI402956B (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140079311A (ko) * 2012-12-18 2014-06-26 신꼬오덴기 고교 가부시키가이샤 반도체 장치의 제조 방법

Families Citing this family (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4996160B2 (ja) * 2006-07-25 2012-08-08 新光電気工業株式会社 電子部品の製造方法
JP4957123B2 (ja) * 2006-08-25 2012-06-20 大日本印刷株式会社 センサーユニットおよびその製造方法
JP2008192651A (ja) * 2007-01-31 2008-08-21 Elpida Memory Inc 半導体素子ユニットとその複合体及び半導体装置とそのモジュール並びにそれらの組立構造とフィルム基板の接続構造
JP5003940B2 (ja) * 2007-02-02 2012-08-22 日立化成工業株式会社 配線板
JP5194537B2 (ja) * 2007-04-23 2013-05-08 株式会社デンソー 半導体装置およびその製造方法
JP5193503B2 (ja) * 2007-06-04 2013-05-08 新光電気工業株式会社 貫通電極付き基板及びその製造方法
KR100956688B1 (ko) * 2008-05-13 2010-05-10 삼성전기주식회사 인쇄회로기판 및 그 제조방법
JP5297139B2 (ja) 2008-10-09 2013-09-25 新光電気工業株式会社 配線基板及びその製造方法
WO2010041165A1 (en) * 2008-10-10 2010-04-15 Nxp B.V. Method of plating through wafer vias in a wafer for 3d packaging
JP5246103B2 (ja) 2008-10-16 2013-07-24 大日本印刷株式会社 貫通電極基板の製造方法
JP5350745B2 (ja) 2008-10-21 2013-11-27 新光電気工業株式会社 配線基板
JP5193809B2 (ja) * 2008-11-05 2013-05-08 新光電気工業株式会社 配線基板及びその製造方法
TWI392069B (zh) 2009-11-24 2013-04-01 日月光半導體製造股份有限公司 封裝結構及其封裝製程
TWI446420B (zh) 2010-08-27 2014-07-21 日月光半導體製造股份有限公司 用於半導體製程之載體分離方法
TWI445152B (zh) 2010-08-30 2014-07-11 日月光半導體製造股份有限公司 半導體結構及其製作方法
US9007273B2 (en) 2010-09-09 2015-04-14 Advances Semiconductor Engineering, Inc. Semiconductor package integrated with conformal shield and antenna
TWI434387B (zh) 2010-10-11 2014-04-11 日月光半導體製造股份有限公司 具有穿導孔之半導體裝置及具有穿導孔之半導體裝置之封裝結構及其製造方法
TWI527174B (zh) 2010-11-19 2016-03-21 日月光半導體製造股份有限公司 具有半導體元件之封裝結構
US9077344B2 (en) * 2010-12-07 2015-07-07 Atmel Corporation Substrate for electrical component and method
KR20120077876A (ko) * 2010-12-31 2012-07-10 삼성전자주식회사 이종 기판 접합 구조 및 방법
TWI445155B (zh) 2011-01-06 2014-07-11 日月光半導體製造股份有限公司 堆疊式封裝結構及其製造方法
US8853819B2 (en) 2011-01-07 2014-10-07 Advanced Semiconductor Engineering, Inc. Semiconductor structure with passive element network and manufacturing method thereof
JP2012195465A (ja) * 2011-03-17 2012-10-11 Canon Inc 貫通電極基板及びその製造方法
US8541883B2 (en) 2011-11-29 2013-09-24 Advanced Semiconductor Engineering, Inc. Semiconductor device having shielded conductive vias
US8975157B2 (en) 2012-02-08 2015-03-10 Advanced Semiconductor Engineering, Inc. Carrier bonding and detaching processes for a semiconductor wafer
US8963316B2 (en) 2012-02-15 2015-02-24 Advanced Semiconductor Engineering, Inc. Semiconductor device and method for manufacturing the same
US8786060B2 (en) 2012-05-04 2014-07-22 Advanced Semiconductor Engineering, Inc. Semiconductor package integrated with conformal shield and antenna
US9153542B2 (en) 2012-08-01 2015-10-06 Advanced Semiconductor Engineering, Inc. Semiconductor package having an antenna and manufacturing method thereof
US8937387B2 (en) 2012-11-07 2015-01-20 Advanced Semiconductor Engineering, Inc. Semiconductor device with conductive vias
US8952542B2 (en) 2012-11-14 2015-02-10 Advanced Semiconductor Engineering, Inc. Method for dicing a semiconductor wafer having through silicon vias and resultant structures
US9406552B2 (en) 2012-12-20 2016-08-02 Advanced Semiconductor Engineering, Inc. Semiconductor device having conductive via and manufacturing process
US8841751B2 (en) 2013-01-23 2014-09-23 Advanced Semiconductor Engineering, Inc. Through silicon vias for semiconductor devices and manufacturing method thereof
US9978688B2 (en) 2013-02-28 2018-05-22 Advanced Semiconductor Engineering, Inc. Semiconductor package having a waveguide antenna and manufacturing method thereof
US9089268B2 (en) 2013-03-13 2015-07-28 Advanced Semiconductor Engineering, Inc. Neural sensing device and method for making the same
US9173583B2 (en) 2013-03-15 2015-11-03 Advanced Semiconductor Engineering, Inc. Neural sensing device and method for making the same
US8987734B2 (en) 2013-03-15 2015-03-24 Advanced Semiconductor Engineering, Inc. Semiconductor wafer, semiconductor process and semiconductor package
CN104659017A (zh) * 2013-11-20 2015-05-27 宏启胜精密电子(秦皇岛)有限公司 中介板及其制作方法
US10418256B2 (en) * 2014-10-22 2019-09-17 Nippon Sheet Glass Company, Limited Method for producing glass substrate and glass sheet
US9633930B2 (en) * 2014-11-26 2017-04-25 Kookmin University Industry Academy Cooperation Foundation Method of forming through-hole in silicon substrate, method of forming electrical connection element penetrating silicon substrate and semiconductor device manufactured thereby
JP2016213283A (ja) * 2015-05-01 2016-12-15 ソニー株式会社 製造方法、および貫通電極付配線基板
CN105070682B (zh) * 2015-07-17 2018-05-29 上海交通大学 一种高效制备硅转接板的方法
JP6191728B2 (ja) * 2015-08-10 2017-09-06 大日本印刷株式会社 イメージセンサモジュール
JP2017199854A (ja) 2016-04-28 2017-11-02 Tdk株式会社 貫通配線基板
JP6790847B2 (ja) * 2017-01-13 2020-11-25 凸版印刷株式会社 配線基板、多層配線基板および配線基板の製造方法
JP7105549B2 (ja) * 2017-04-28 2022-07-25 日東電工株式会社 配線回路基板、および、撮像装置
WO2018199017A1 (ja) * 2017-04-28 2018-11-01 日東電工株式会社 配線回路基板、および、撮像装置

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63137498A (ja) * 1986-11-28 1988-06-09 松下電工株式会社 スル−ホ−ルプリント板の製法
JPH01258457A (ja) 1988-04-08 1989-10-16 Nec Corp 半導体集積回路の実装構造およびその製造方法
US5071359A (en) * 1990-04-27 1991-12-10 Rogers Corporation Array connector
US5819406A (en) * 1990-08-29 1998-10-13 Canon Kabushiki Kaisha Method for forming an electrical circuit member
JP3213037B2 (ja) 1992-01-07 2001-09-25 日東電工株式会社 加工フィルムの製造方法
US5638598A (en) * 1993-06-17 1997-06-17 Hitachi Chemical Company, Ltd. Process for producing a printed wiring board
US6055723A (en) * 1998-06-01 2000-05-02 Trw Inc. Process of fabricating high frequency connections to high temperature superconductor circuits
JP2002064270A (ja) * 2000-08-17 2002-02-28 Matsushita Electric Ind Co Ltd 回路基板とその製造方法
US6518514B2 (en) * 2000-08-21 2003-02-11 Matsushita Electric Industrial Co., Ltd. Circuit board and production of the same
JP4703061B2 (ja) * 2001-08-30 2011-06-15 富士通株式会社 薄膜回路基板の製造方法およびビア形成基板の形成方法
JP3826007B2 (ja) * 2001-10-11 2006-09-27 シャープ株式会社 配線接続構造およびこれを用いた送信機
JP3807312B2 (ja) * 2002-01-18 2006-08-09 富士通株式会社 プリント基板とその製造方法
TW523842B (en) * 2002-03-22 2003-03-11 Advanced Chip Eng Tech Inc Method for manufacturing i/o terminals and the structure thereof
JP2004146742A (ja) 2002-10-28 2004-05-20 Shinko Electric Ind Co Ltd 配線基板の製造方法
GB2420912B (en) * 2002-12-11 2006-07-26 Dainippon Printing Co Ltd Multilayer wiring board and manufacture method thereof
JP4287133B2 (ja) * 2002-12-11 2009-07-01 大日本印刷株式会社 スルーホール配線基板の製造方法
JP4019960B2 (ja) * 2003-01-31 2007-12-12 三菱電機株式会社 基板の製造方法
US6839965B2 (en) * 2003-02-06 2005-01-11 R-Tec Corporation Method of manufacturing a resistor connector

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140079311A (ko) * 2012-12-18 2014-06-26 신꼬오덴기 고교 가부시키가이샤 반도체 장치의 제조 방법

Also Published As

Publication number Publication date
TWI402956B (zh) 2013-07-21
DE602005004586D1 (de) 2008-03-20
CN100517678C (zh) 2009-07-22
EP1656006B1 (en) 2008-01-30
JP3987521B2 (ja) 2007-10-10
TW200635021A (en) 2006-10-01
DE602005004586T2 (de) 2009-03-19
US20080261396A1 (en) 2008-10-23
EP1656006A1 (en) 2006-05-10
US7772118B2 (en) 2010-08-10
CN1783472A (zh) 2006-06-07
US20060096781A1 (en) 2006-05-11
JP2006135174A (ja) 2006-05-25

Similar Documents

Publication Publication Date Title
US7772118B2 (en) Substrate having high electrical connection reliability of a penetrating via connected to wirings and a method for manufacturing the same
JP4369348B2 (ja) 基板及びその製造方法
US5527741A (en) Fabrication and structures of circuit modules with flexible interconnect layers
RU2297736C2 (ru) Способ встраивания компонента в основание и формирования электрического контакта с компонентом
US9247644B2 (en) Wiring board and method for manufacturing the same
KR101627574B1 (ko) 배선 기판 및 그 제조 방법
US6461892B2 (en) Methods of making a connection component using a removable layer
KR100702018B1 (ko) 반도체 장치의 제조 방법 및 반도체 장치
US10249561B2 (en) Printed wiring board having embedded pads and method for manufacturing the same
KR101242998B1 (ko) 집적 회로용 범프 응력 완화 층
CN100461357C (zh) 贯通电极及其形成方法
KR20080106013A (ko) 배선 기판 및 그 제조 방법
KR20040051310A (ko) 도금 인입선을 사용하지 않는 패키지 기판 및 그 제조 방법
JP2010219503A (ja) 半導体素子実装基板及び半導体素子実装基板の製造方法
EP2162909A1 (en) Circuit assembly including a metal core substrate and process for preparing the same
JP4055015B2 (ja) 半導体装置の製造方法
US8658905B2 (en) Multilayer wiring substrate
US11749596B2 (en) Wiring substrate
KR100393271B1 (ko) 다층 전자부품탑재용 기판의 제조 방법
KR20110129446A (ko) 반도체 소자용 기판의 제조 방법 및 반도체 장치
HK1077151B (en) Method for embedding a component in a base and forming a contact

Legal Events

Date Code Title Description
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

PC1203 Withdrawal of no request for examination

St.27 status event code: N-1-6-B10-B12-nap-PC1203

WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid
P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000