KR20040060781A - 반도체 장치 및 그의 제작방법 - Google Patents
반도체 장치 및 그의 제작방법 Download PDFInfo
- Publication number
- KR20040060781A KR20040060781A KR1020030097231A KR20030097231A KR20040060781A KR 20040060781 A KR20040060781 A KR 20040060781A KR 1020030097231 A KR1020030097231 A KR 1020030097231A KR 20030097231 A KR20030097231 A KR 20030097231A KR 20040060781 A KR20040060781 A KR 20040060781A
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- South Korea
- Prior art keywords
- substrate
- semiconductor
- semiconductor element
- film
- metal oxide
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 497
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- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 72
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
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- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
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- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68368—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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Abstract
Description
Claims (24)
- 절연성 기판 상에, 배선부, 제1 반도체 소자, 제2 반도체 소자를 차례로 적층한 반도체 장치를 제작하는 방법으로서,반도체 기판을 사용하여 상기 제1 반도체 소자의 집적회로를 형성하는 공정;상기 배선부를 사이에 두고 상기 절연성 기판에 상기 제1 반도체 소자를 접착하는 공정;제1 기판의 표면에, 금속막, 금속 산화막, 절연막, 및 반도체 박막을 차례로 적층하는 공정;가열처리에 의해 상기 금속 산화막과 상기 반도체 박막을 결정화하는 공정;이 결정화된 반도체 박막을 이용하여 상기 제2 반도체 소자의 집적회로를 형성하는 공정;상기 제1 기판과 서로 마주보도록, 제1 접착 부재를 사용하여 상기 제2 반도체 소자 위에 제2 기판을 붙이는 공정;상기 결정화된 금속 산화막으로부터 상기 금속막을, 또는 상기 절연막으로부터 상기 결정화된 금속 산화막을, 또는 상기 결정화된 금속 산화막을 물리적 수단에 의해 분리하는 공정;상기 제1 반도체 소자 위에 상기 제2 반도체 소자를 접착하는 공정;상기 제1 접착 부재를 제거하는 공정;상기 제2 반도체 소자로부터 상기 제2 기판을 분리하는 공정; 및상기 제1 반도체 소자와 상기 배선부를 전기적으로 접속한 후, 상기 제2 반도체 소자와 상기 배선부를 전기적으로 접속하는 공정을 포함하는 것을 특징으로 하는 반도체 장치의 제작방법.
- 절연성 기판 상에, 배선부, 제1 반도체 소자, 제2 반도체 소자를 차례로 적층한 반도체 장치를 제작하는 방법으로서,반도체 기판을 사용하여 상기 제1 반도체 소자의 집적회로를 형성하는 공정;상기 절연성 기판 위에 형성된 상기 배선부와 상기 제1 반도체 소자를 전기적으로 접속하는 공정;제1 기판의 표면에, 금속막, 금속 산화막, 절연막, 반도체 박막을 차례로 적층하는 공정;가열처리에 의해 상기 금속 산화막과 상기 반도체 박막을 결정화하는 공정;이 결정화된 반도체 박막을 사용하여 상기 제2 반도체 소자의 집적회로를 형성하는 공정;상기 제1 기판과 마주보도록, 제1 접착 부재를 사용하여 상기 제2 반도체 소자 위에 제2 기판을 붙이는 공정;상기 결정화된 금속 산화막으로부터 상기 금속막을, 또는 상기 절연막으로부터 상기 결정화된 금속 산화막을, 또는 상기 결정화된 금속 산화막을 물리적 수단에 의해 분리하는 공정;상기 제1 반도체 소자 위에 상기 제2 반도체 소자를 접착하는 공정;상기 제1 접착 부재를 제거하는 공정;상기 제2 반도체 소자로부터 상기 제2 기판을 분리하는 공정; 및상기 제2 반도체 소자와 상기 배선부를 전기적으로 접속하는 공정을 포함하는 것을 특징으로 하는 반도체 장치의 제작방법.
- 절연성 기판 상에, 제1 배선부, 제1 반도체 소자, 제2 배선부, 제2 반도체 소자를 차례로 적층한 반도체 장치를 제작하는 방법으로서,반도체 기판을 이용하여 상기 제1 반도체 소자의 집적회로를 형성하는 공정;상기 절연성 기판 위에 형성된 상기 제1 배선부와 상기 제1 반도체 소자를 전기적으로 접속한 후 절연막을 사이에 두고 상기 제1 반도체 소자 위에 제2 배선부를 형성하는 공정;제1 기판의 표면에, 금속막, 금속 산화막, 절연막, 반도체 박막을 차례로 적층하는 공정;가열처리에 의해 상기 금속 산화막과 상기 반도체 박막을 결정화하는 공정;이 결정화된 반도체 박막을 이용하여 상기 제2 반도체 소자의 집적회로를 형성하는 공정;상기 제1 기판과 마주보도록, 제1 접착 부재를 사용하여 상기 제2 반도체 소자 위에 제2 기판을 붙이는 공정;상기 결정화된 금속 산화막으로부터 상기 금속막을, 또는 상기 절연막으로부터 상기 결정화된 금속 산화막을, 또는 상기 결정화된 금속 산화막을 물리적 수단에 의해 분리하는 공정;상기 제2 기판과 마주보도록 상기 제2 반도체 소자에 제3 기판을 접착하는 공정;상기 제1 접착 부재를 제거하는 공정;상기 제2 반도체 소자로부터 상기 제2 기판을 분리하는 공정; 및상기 제2 배선부와 상기 제2 반도체 소자를 전기적으로 접속하는 공정을 포함하는 것을 특징으로 하는 반도체 장치의 제작방법.
- 절연성 기판 위에, 배선부, 제2 반도체 소자, 제1 반도체 소자를 차례로 적층한 반도체 장치를 제작하는 방법으로서,반도체 기판을 이용하여 상기 제1 반도체 소자의 집적회로를 형성하는 공정;제1 기판의 표면에, 금속막, 금속 산화막, 절연막, 반도체 박막을 차례로 적층하는 공정;가열처리에 의해 상기 금속 산화막과 상기 반도체 박막을 결정화하는 공정;이 결정화된 반도체 박막을 이용하여 상기 제2 반도체 소자의 집적회로를 형성하는 공정;상기 제1 기판과 마주보도록, 제1 접착 부재를 사용하여 상기 제2 반도체 소자 위에 제2 기판을 붙이는 공정;상기 결정화된 금속 산화막으로부터 상기 금속막을, 또는 상기 절연막으로부터 상기 결정화된 금속 산화막을, 또는 상기 결정화된 금속 산화막을 물리적 수단에 의해 분리하는 공정;상기 제1 반도체 소자 위에 상기 제2 반도체 소자를 접착하는 공정;상기 제1 접착 부재를 제거하는 공정;상기 제2 반도체 소자로부터 상기 제2 기판을 분리하는 공정;상기 배선부를 사이에 두고 상기 절연성 기판에 상기 제2 반도체 소자를 붙이는 공정; 및상기 배선부와 상기 제2 반도체 소자를 전기적으로 접속한 후 상기 배선부와 상기 제1 반도체 소자를 전기적으로 접속하는 공정을 포함하는 것을 특징으로 하는 반도체 장치의 제작방법.
- 절연성 기판 위에, 배선부, 제2 반도체 소자, 제1 반도체 소자를 차례로 적층한 반도체 장치를 제작하는 방법으로서,반도체 기판을 이용하여 상기 제1 반도체 소자의 집적회로를 형성하는 공정;제1 기판의 표면에, 금속막, 금속 산화막, 절연막, 반도체 박막을 차례로 적층하는 공정;가열처리에 의해 상기 금속 산화막과 상기 반도체 박막을 결정화하는 공정;이 결정화된 반도체 박막을 이용하여 상기 제2 반도체 소자의 집적회로를 형성하는 공정;상기 제1 기판과 마주보도록, 제1 접착 부재를 사용하여 상기 제2 반도체 소자 위에 제2 기판을 붙이는 공정;상기 결정화된 금속 산화막으로부터 상기 금속막을, 또는 상기 절연막으로부터 상기 결정화된 금속 산화막을, 또는 상기 결정화된 금속 산화막을 물리적 수단에 의해 분리하는 공정;상기 제1 반도체 소자 위에 상기 제2 반도체 소자를 붙이는 공정;상기 제1 접착 부재를 제거하는 공정;상기 제2 반도체 소자로부터 상기 제2 기판을 분리하는 공정;상기 절연성 기판 위에 형성된 상기 배선부와 상기 제2 반도체 소자를 전기적으로 접속하는 공정; 및상기 배선부와 상기 제1 반도체 소자를 전기적으로 접속하는 공정을 포함하는 것을 특징으로 하는 반도체 장치의 제작방법.
- 절연성 기판 위에, 제1 배선부, 제2 반도체 소자, 제2 배선부, 제1 반도체 소자를 차례로 적층한 반도체 장치를 제작하는 방법으로서,반도체 기판을 이용하여 상기 제1 반도체 소자의 집적회로를 형성하는 공정;제1 기판의 표면에, 금속막, 금속 산화막, 절연막, 반도체 박막을 차례로 적층하는 공정;가열처리에 의해 상기 금속 산화막과 상기 반도체 박막을 결정화하는 공정;이 결정화된 반도체 박막을 이용하여 상기 제2 반도체 소자의 집적회로를 형성하는 공정;상기 제1 기판과 마주보도록, 제1 접착 부재를 사용하여 상기 제2 반도체 소자 위에 제2 기판을 붙이는 공정;상기 결정화된 금속 산화막으로부터 상기 금속막을, 또는 상기 절연막으로부터 상기 결정화된 금속 산화막을, 또는 상기 결정화된 금속 산화막을 물리적 수단에 의해 분리하는 공정;상기 제2 기판과 마주보도록 상기 제2 반도체 소자에 제3 기판을 붙이는 공정;상기 제1 접착 부재를 제거하는 공정;상기 제2 반도체 소자로부터 상기 제2 기판을 분리하는 공정;상기 절연성 기판 위에 형성된 상기 제1 배선부와 상기 제2 반도체 소자를 전기적으로 접속한 후 상기 제3 기판을 사이에 두고 상기 제2 반도체 소자 위에 제2 배선부를 형성하는 공정; 및상기 제2 배선부와 상기 제1 반도체 소자를 전기적으로 접속하는 공정을 포함하는 것을 특징으로 하는 반도체 장치의 제작방법.
- 제 1 항 내지 제 6 항 중 어느 한 항에 있어서, 상기 반도체 기판은, 단결정 실리콘 기판 또는 화합물 반도체 기판인 것을 특징으로 하는 반도체 장치의 제작방법.
- 제 1 항 내지 제 6 항 중 어느 한 항에 있어서, 상기 반도체 기판은, N형 또는 P형 단결정 실리콘 기판, GaAs 기판, InP 기판, GaN 기판, SiC 기판, ZnSe 기판, GaP 기판, 및 InSb 기판으로 이루어진 군으로부터 선택된 기판인 것을 특징으로 하는 반도체 장치의 제작방법.
- 제 1 항 내지 제 6 항 중 어느 한 항에 있어서, 상기 반도체 박막이 실리콘을 포함하는 것을 특징으로 하는 반도체 장치의 제작방법.
- 제 1 항 내지 제 6 항 중 어느 한 항에 있어서, 상기 제1 반도체 소자는, 전원 회로, 송수신 회로, 메모리, 및 음성 처리 회로의 증폭기로 이루어진 군으로부터 선택된 적어도 하나인 것을 특징으로 하는 반도체 장치의 제작방법.
- 제 1 항 내지 제 6 항 중 어느 한 항에 있어서, 상기 제2 반도체 소자는, 화소부의 주사선 구동회로, 신호선 구동회로, 콘트롤러, CPU, 및 음성 처리 회로의 컨버터로 이루어진 군으로부터 선택된 적어도 하나인 것을 특징으로 하는 반도체 장치의 제작방법.
- 제 1 항 내지 제 6 항 중 어느 한 항에 있어서, 상기 제1 접척 부재가 박리 가능한 접작재로 되어 있는 것을 특징으로 하는 반도체 장치의 제작방법.
- 제 1 항 내지 제 6 항 중 어느 한 항에 있어서, 상기 절연성 기판은 폴리이미드, 알루미나, 세라믹, 및 유리 에폭시 수지로부터 선택된 재료로 형성되어 있는것을 특징으로 하는 반도체 장치의 제작방법.
- 반도체 기판을 이용하여 집적회로를 형성한 제1 반도체 소자와, 반도체 박막을 이용하여 집적회로를 형성한 제2 반도체 소자를 포함하고,상기 제1 반도체 소자와 상기 제2 반도체 소자가 유기 수지 또는 접착 부재를 사이에 두고 절연성 기판 위에 적층되어 있는 것을 특징으로 하는 반도체 장치.
- 제 14 항에 있어서, 상기 제1 반도체 소자가 상기 제2 반도체 소자와 상기 절연성 기판 사이에 끼워져 있는 것을 특징으로 하는 반도체 장치.
- 제 14 항에 있어서, 상기 제2 반도체 소자가 상기 제1 반도체 소자와 상기 절연성 기판 사이에 끼워져 있는 것을 특징으로 하는 반도체 장치.
- 제 14 항에 있어서, 상기 제2 반도체 소자의 막 두께가 50 ㎛ 이하인 것을 특징으로 하는 반도체 장치.
- 제 14 항에 있어서, 상기 제2 반도체 소자의 막 두께가 0.1 ㎛ 내지 1 ㎛인 것을 특징으로 하는 반도체 장치.
- 제 14 항에 있어서, 상기 반도체 기판은 단결정 실리콘 기판 또는 화합물 반도체 기판인 것을 특징으로 하는 반도체 장치.
- 제 14 항에 있어서, 상기 반도체 기판은, N형 또는 P형 단결정 실리콘 기판, GaAs 기판, InP 기판, GaN 기판, SiC 기판, ZnSe 기판, GaP 기판, 및 InSb 기판으로 이루어진 군으로부터 선택된 기판인 것을 특징으로 하는 반도체 장치.
- 제 14 항에 있어서, 상기 반도체 박막이 실리콘을 포함하는 것을 특징으로 하는 반도체 장치.
- 제 14 항에 있어서, 상기 제1 반도체 소자는, 전원 회로, 송수신 회로, 메모리, 및 음성 처리 회로의 증폭기로 이루어진 군으로부터 선택된 적어도 하나인 것을 특징으로 하는 반도체 장치.
- 제 14 항에 있어서, 상기 제2 반도체 소자는, 화소부의 주사선 구동회로, 신호선 구동회로, 콘트롤러, CPU, 및 음성 처리 회로의 컨버터로 이루어진 군으로부터 선택된 적어도 하나인 것을 특징으로 하는 반도체 장치.
- 제 14 항에 있어서, 상기 절연성 기판은, 폴리이미드, 알루미나, 세라믹, 및 유리 에폭시 수지로부터 선택된 재료로 형성되어 있는 것을 특징으로 하는 반도체 장치.
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JP3831593B2 (ja) * | 2000-09-21 | 2006-10-11 | 三洋電機株式会社 | マルチチップモジュール |
US6599818B2 (en) * | 2000-10-10 | 2003-07-29 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device manufacturing method, heat treatment apparatus, and heat treatment method |
JP4061846B2 (ja) * | 2001-01-23 | 2008-03-19 | セイコーエプソン株式会社 | 積層体の製造方法及び半導体装置の製造方法 |
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JP4449258B2 (ja) * | 2001-06-15 | 2010-04-14 | ソニー株式会社 | 電子回路装置およびその製造方法 |
US7030488B2 (en) * | 2001-10-30 | 2006-04-18 | Intel Corporation | Packaged combination memory for electronic devices |
US6833287B1 (en) * | 2003-06-16 | 2004-12-21 | St Assembly Test Services Inc. | System for semiconductor package with stacked dies |
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2003
- 2003-12-19 EP EP03029476.3A patent/EP1434264A3/en not_active Withdrawn
- 2003-12-22 US US10/740,422 patent/US7037752B2/en not_active Expired - Fee Related
- 2003-12-23 TW TW092136581A patent/TWI318782B/zh not_active IP Right Cessation
- 2003-12-23 TW TW095143759A patent/TWI359468B/zh not_active IP Right Cessation
- 2003-12-26 KR KR1020030097231A patent/KR101013482B1/ko active IP Right Grant
- 2003-12-26 CN CN2009101475149A patent/CN101577271B/zh not_active Expired - Fee Related
- 2003-12-26 CN CNB200310123567XA patent/CN100530576C/zh not_active Expired - Fee Related
-
2006
- 2006-03-14 US US11/374,037 patent/US7863754B2/en not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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KR100853136B1 (ko) * | 2005-06-09 | 2008-08-20 | 엔이씨 일렉트로닉스 가부시키가이샤 | 반도체 디바이스 및 반도체 디바이스를 제조하는 방법 |
US7687803B2 (en) | 2005-06-09 | 2010-03-30 | Nec Electronics Corporation | Semiconductor device and method for manufacturing semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
TW200416905A (en) | 2004-09-01 |
CN101577271B (zh) | 2012-08-08 |
US20060163710A1 (en) | 2006-07-27 |
TWI318782B (en) | 2009-12-21 |
US7037752B2 (en) | 2006-05-02 |
CN100530576C (zh) | 2009-08-19 |
CN1516253A (zh) | 2004-07-28 |
US20040130020A1 (en) | 2004-07-08 |
US7863754B2 (en) | 2011-01-04 |
TW200709309A (en) | 2007-03-01 |
TWI359468B (en) | 2012-03-01 |
CN101577271A (zh) | 2009-11-11 |
EP1434264A2 (en) | 2004-06-30 |
EP1434264A3 (en) | 2017-01-18 |
KR101013482B1 (ko) | 2011-02-14 |
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