JP4649198B2 - 配線基板の製造方法 - Google Patents
配線基板の製造方法 Download PDFInfo
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- JP4649198B2 JP4649198B2 JP2004367945A JP2004367945A JP4649198B2 JP 4649198 B2 JP4649198 B2 JP 4649198B2 JP 2004367945 A JP2004367945 A JP 2004367945A JP 2004367945 A JP2004367945 A JP 2004367945A JP 4649198 B2 JP4649198 B2 JP 4649198B2
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Description
200 配線基板
101 支持体
102 支持体剥離層
103 第1の電極層
104,106 バリア層
104A,104B,106A,106B 金属層
105 誘電体層
107 第2の電極層
108,109,110,201,205,206,211 絶縁層
111,202,207,209,212 ビア配線
112,203,204,208,210,213 パターン配線
113,214 ソルダーレジスト層
114,215 メッキ層
115 ソルダーバンプ
400 半導体チップ
Claims (7)
- 半導体チップに接続されるキャパシタを形成する工程と、
前記キャパシタと前記半導体チップを接続する配線部を形成する工程と、を有する半導体チップが接続される配線基板の製造方法であって、
前記配線部は、前記キャパシタを構成する第1の電極層および第2の電極層を貫通するビア配線を含み、
前記キャパシタを形成する工程は、
当該キャパシタを支持する支持体上に支持体剥離層を形成する工程と、
前記支持体剥離層上に前記第1の電極層、誘電体層、前記第2の電極層を含む複数の層を形成する工程と、
前記第1の電極層および前記第2の電極層に、前記ビア配線が貫通する穴部を形成する穴部形成工程と、を有し、
前記穴部形成工程は、前記第2の電極層に第1の穴部を形成する工程と、当該第1の穴部を形成後、当該第2の電極層上に絶縁層を形成する工程と、当該絶縁層を形成後、前記支持体を前記第1の電極層より剥離し、前記第1の電極層に、前記第1の穴部に対応する第2の穴部を形成する工程と、を含み、かつ、前記第1の穴部及びそれに対応する前記第2の穴部の何れか一方の穴部を他方の穴部より小径に形成し、
前記配線部を形成する工程は、前記第1の穴部と前記第2の穴部を貫通すると共に、前記第1の穴部と前記第2の穴部の内、前記一方の穴部を含み前記他方の穴部よりも小径の第3の穴部を形成する工程と、前記第3の穴部内に前記第1の電極層又は前記第2の電極層と接続する前記ビア配線を形成する工程と、を有し、
前記支持体剥離層と前記第1の電極層との密着力は、前記複数の層の間の密着力よりも小さいことを特徴とする配線基板の製造方法。 - 基板のパターン配線上に前記キャパシタを搭載し、前記キャパシタを被覆する絶縁層を形成する工程と、
前記絶縁層及び前記キャパシタに、前記パターン配線に到達する穴部を形成する工程と、
前記穴部内にビア配線を形成すると共に、前記絶縁層上に前記ビア配線と接続された他のパターン配線を形成する工程と、を更に有することを特徴とする請求項1記載の配線基板の製造方法。 - 前記第1の電極層、および第2の電極層は、Cuよりなることを特徴とする請求項1又は2記載の配線基板の製造方法。
- 前記支持体剥離層は、Mo,Ta,またはPtよりなることを特徴とする請求項1乃至3のうち、いずれか1項記載の配線基板の製造方法。
- 前記穴部形成工程の後、
前記穴部を貫通するビア配線を形成する工程と、
前記ビア配線に接続され、前記半導体チップが接続される第1の側と、当該第1の側の反対側の第2の側を電気的に接続する多層配線を形成する工程をさらに有することを特徴とする請求項1乃至4のうち、いずれか1項記載の配線基板の製造方法。 - 前記ビア配線を形成する工程は、前記第1の電極層と電気的に接続し前記第2の電極層と電気的に接続しない第1のビア配線と、前記第2の電極層と電気的に接続し前記第1の電極層と電気的に接続しない第2のビア配線とを隣接して形成する工程を含む請求項5記載の配線基板の製造方法。
- 前記誘電体層は、Ta2O5,STO,BST,PZT,または、BTOよりなることを特徴とする請求項1乃至6のうち、いずれか1項記載の配線基板の製造方法。
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