CN101577271A - 半导体器件以及其制作方法 - Google Patents

半导体器件以及其制作方法 Download PDF

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Publication number
CN101577271A
CN101577271A CNA2009101475149A CN200910147514A CN101577271A CN 101577271 A CN101577271 A CN 101577271A CN A2009101475149 A CNA2009101475149 A CN A2009101475149A CN 200910147514 A CN200910147514 A CN 200910147514A CN 101577271 A CN101577271 A CN 101577271A
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semiconductor element
substrate
semiconductor
semiconductor device
circuit
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CN101577271B (zh
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桑原秀明
高山彻
后藤裕吾
丸山纯矢
大野由美子
山崎舜平
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Abstract

本发明提供一种半导体器件以及其制作方法，本发明的目的是提供一种低成本，小体积，并且高集成化的半导体器件。本发明利用转移技术，将用半导体薄膜形成的半导体元件转移到用半导体衬底形成的半导体元件之上，从而制作半导体器件。跟常规的MCP相比，本发明可以用更低成本，并更高产量地大量生产半导体器件，而且可以减少每个半导体器件的生产成本。

Description

半导体器件以及其制作方法
本发明申请是本发明申请人于2003年12月26日提交的、申请号为200310123567.X、发明名称为“半导体器件以及其制作方法”的发明申请的分案申请。
技术领域
本发明涉及高集成化的半导体器件以及其制作方法。确切地说，本发明涉及一种通过层叠叠加其电路被集成的半导体元件(IC芯片)而获得的半导体器件以及其制作方法。
背景技术
以移动电话和电子笔记本为典型的便携用电子器具被要求具有各种各样的包括电子邮件的收发，声频识别，由小型照相机收录图像，利用互联网等功能。所以，便携用电子器具需求电路规模和存储量更大的半导体器件(封装)。
另一方面，便携用电子器具从携带方便的角度，对电子器具体积的小型化，轻巧化，以及价格的低廉化的需求更加深入了一步。这样就等于对半导体器件(封装)，电阻等的被动部件，装载用衬底等提出了小型化和价格低廉化的要求，而且，做到几乎和裸芯片相同尺寸的半导体器件(封装)，即芯片级封装CSP(Chip Size Package)也被开发出来了。(专利文件1)
所以，就有了提高半导体集成的多芯片封装MCP(Multi ChipPackage)，该MCP将在多个半导体衬底上集成的集成电路(IC芯片)搭载到一个封装。(专利文件2)
专利文件1
专利公开Hei No.9-121002(P8-P10，图1)
专利文件2
专利公开Hei No.5-90486(P2-P3，图1)
多芯片封装MCP包括将使用多个半导体衬底形成的集成电路(IC芯片)横向排列从而来提高集成的MCP。然而，横向排列多个IC芯片造成了封装面积增大，这样就妨碍了装载用衬底的缩小。
另外，专利文件2中提出的半导体器件(封装)是将用硅片(半导体衬底)形成的集成电路(IC芯片)多个层叠而获得。用硅片形成的IC芯片的厚度相对较厚，如将这些芯片层叠叠加，虽然封装的面积会减少，但封装的体积却会增大，其结果是，妨碍了使用该封装的电子器具的轻巧化。
因此，在多芯片封装MCP中，为了减小封装的体积，采用了将用硅片形成的IC芯片研磨薄的工艺(背面研磨(back grind))。但是，由于这个背面研磨的研磨工艺会在硅片的背面留下深几十nm的研磨痕迹，并成为导致半导体元件的机械强度降低的一个原因。其结果，该半导体元件的研磨工艺导致了成品率降低的问题。
而且，硅片比玻璃衬底的价格高，所以层叠多层使用硅片的半导体元件还有一个每封装单位的成本增高的问题。
发明内容
针对上述问题，本发明的目的是提供低成本，小体积，并且高集成化的半导体器件。
本发明提供一种在绝缘性衬底上按顺序层叠布线部分，第一半导体元件，第二半导体元件的半导体器件的制作方法，它包括以下步骤：
用半导体衬底形成所述第一半导体元件的集成电路；
在所述绝缘性衬底上粘合所述第一半导体元件，二者中间夹所述布线部分；
在第一衬底的表面上按顺序层叠金属膜，金属氧化膜，绝缘膜，半导体薄膜；
执行热处理来晶化所述金属氧化膜和所述半导体薄膜；
用该晶化过的半导体薄膜形成所述第二半导体元件的集成电路；
用第一粘合剂在所述第二半导体元件上粘合第二衬底，并使该第二衬底和所述第一衬底互相面对；
在所述金属膜和所述晶化过的金属氧化膜之间，在所述晶化过的金属氧化膜和所述绝缘膜之间，或在所述晶化过的金属氧化膜中用物理方法执行剥离；
在所述第一半导体元件上粘合所述第二半导体元件；
去除所述第一粘合剂；
从所述第二半导体元件剥离所述第二衬底；
电连接所述第一半导体元件和所述布线部分，然后电连接所述第二半导体元件和所述布线部分。
另外，本发明提供一种在绝缘性衬底上按顺序层叠布线部分，第一半导体元件，第二半导体元件的半导体器件的制作方法，它包括以下步骤：
用半导体衬底形成所述第一半导体元件的集成电路；
电连接在所述绝缘性衬底上形成的所述布线部分和所述第一半导体元件；
在第一衬底的表面上按顺序层叠金属膜，金属氧化膜，绝缘膜，半导体薄膜；
执行热处理来晶化所述金属氧化膜和所述半导体薄膜；
用该晶化过的半导体薄膜形成所述第二半导体元件的集成电路；
用第一粘合剂在所述第二半导体元件上粘合第二衬底，并使该第二衬底和所述第一衬底互相面对；
在所述金属膜和所述晶化过的金属氧化膜之间，在所述晶化过的金属氧化膜和所述绝缘膜之间，或在所述晶化过的金属氧化膜中用物理方法执行剥离；
在所述第一半导体元件上粘合所述第二半导体元件；
去除所述第一粘合剂；
从所述第二半导体元件剥离所述第二衬底；
电连接所述第二半导体元件和所述布线部分。
另外，本发明提供一种在绝缘性衬底上按顺序层叠第一布线部分，第一半导体元件，第二布线部分，第二半导体元件的半导体器件的制作方法，它包括以下步骤：
用半导体衬底形成所述第一半导体元件的集成电路；
电连接在所述绝缘性衬底上形成的所述第一布线部分和所述第一半导体元件，然后，在所述第一半导体元件上形成第二布线部分，二者中间夹绝缘膜；
在第一衬底的表面上按顺序层叠金属膜，金属氧化膜，绝缘膜，半导体薄膜；
执行热处理来晶化所述金属氧化膜和所述半导体薄膜；
用该晶化过的半导体薄膜形成所述第二半导体元件的集成电路；
用第一粘合剂在所述第二半导体元件上粘合第二衬底，并使该第二衬底和所述第一衬底互相面对；
在所述金属膜和所述晶化过的金属氧化膜之间，在所述晶化过的金属氧化膜和所述绝缘膜之间，或在所述晶化过的金属氧化膜中用物理方法执行剥离；
在所述第二半导体元件上粘合第三衬底，并使该第三衬底和所述第二衬底互相面对，
去除所述第一粘合剂；
从所述第二半导体元件剥离所述第二衬底；
电连接所述第二半导体元件和所述第二布线部分。
另外，本发明提供一种在绝缘性衬底上按顺序层叠布线部分，第二半导体元件，第一半导体元件的半导体器件的制作方法，它包括以下步骤：
用半导体衬底形成所述第一半导体元件的集成电路；
在第一衬底的表面上按顺序层叠金属膜，金属氧化膜，绝缘膜，半导体薄膜；
执行热处理来晶化所述金属氧化膜和所述半导体薄膜；
用该晶化过的半导体薄膜形成所述第二半导体元件的集成电路；
用第一粘合剂在所述第二半导体元件上粘合第二衬底，并使该第二衬底和所述第一衬底互相面对；
在所述金属膜和所述晶化过的金属氧化膜之间，在所述晶化过的金属氧化膜和所述绝缘膜之间，或在所述晶化过的金属氧化膜中用物理方法执行剥离；
在所述第一半导体元件上粘合所述第二半导体元件；
去除所述第一粘合剂；
从所述第二半导体元件剥离第二衬底；
在所述绝缘性衬底上粘合所述第二半导体元件，二者中间夹所述布线部分；
电连接所述第二半导体元件和所述布线部分，然后电连接所述第一半导体元件和所述布线部分。
另外，本发明提供一种在绝缘性衬底上按顺序层叠布线部分，第二半导体元件，第一半导体元件的半导体器件的制作方法，它包括以下步骤：
用半导体衬底形成所述第一半导体元件的集成电路；
在第一衬底的表面上按顺序层叠金属膜，金属氧化膜，绝缘膜，半导体薄膜；
执行热处理来晶化所述金属氧化膜和所述半导体薄膜；
用该晶化过的半导体薄膜形成所述第二半导体元件的集成电路；
用第一粘合剂在所述第二半导体元件上粘合第二衬底，并使该第二衬底和所述第一衬底互相面对；
在所述金属膜和所述晶化过的金属氧化膜之间，在所述晶化过的金属氧化膜和所述绝缘膜之间，或在所述晶化过的金属氧化膜中用物理方法执行剥离；
在所述第一半导体元件上粘合所述第二半导体元件；
去除所述第一粘合剂；
从所述第二半导体元件剥离所述第二衬底；
电连接在所述绝缘性衬底上形成的所述布线部分和所述第二半导体元件；
电连接所述第一半导体元件和所述布线部分。
另外，本发明提供一种在绝缘性衬底上按顺序层叠第一布线部分，第二半导体元件，第二布线部分，第一半导体元件的半导体器件的制作方法，它包括以下步骤：
用半导体衬底形成所述第一半导体元件的集成电路；
在第一衬底的表面上按顺序层叠金属膜，金属氧化膜，绝缘膜，半导体薄膜；
执行热处理来晶化所述金属氧化膜和所述半导体薄膜；
用该晶化过的半导体薄膜形成所述第二半导体元件的集成电路；
用第一粘合剂在所述第二半导体元件上粘合第二衬底，并使该第二衬底和所述第一衬底互相面对；
在所述金属膜和所述晶化过的金属氧化膜之间，在所述晶化过的金属氧化膜和所述绝缘膜之间，或在所述晶化过的金属氧化膜中用物理方法执行剥离；
在所述第二半导体元件上粘合第三衬底，并使该第三衬底和所述第二衬底互相面对；
去除所述第一粘合剂；
从所述第二半导体元件剥离所述第二衬底；
电连接在所述绝缘性衬底上形成的所述第一布线部分和所述第二半导体元件，然后，在所述第二半导体元件上形成第二布线部分，二者中间夹所述第三衬底；
电连接所述第一半导体元件和所述第二布线部分。
注意，上述半导体衬底是单晶硅衬底或化合物半导体衬底，典型的是选自N型或P型单晶硅衬底，GaAs衬底，InP衬底，GaN衬底，SiC衬底，ZnSe衬底，GaP衬底，或InSb衬底中的一种。
另外，上述半导体薄膜包含硅。
本发明中的所述第一半导体元件至少包括电源电路，收发信电路，存储器，或声频处理电路的放大器中之一种。并且，本发明中的所述第二半导体元件至少包括像素部分的扫描线驱动电路，信号线驱动电路，控制器，CPU，或声频处理电路的变换器中之一种。
另外，本发明的所述第一粘合剂是能够剥离的粘合剂。
注意，上述绝缘性衬底包括选自聚酰亚胺，铝氧，陶瓷，玻璃环氧树脂的材料。
本发明提供一种半导体器件，它包括：
用半导体衬底形成集成电路的第一半导体元件；
用半导体薄膜形成集成电路的第二半导体元件，其中，
在绝缘性衬底上将所述第一半导体元件和所述第二半导体元件层叠在一起，并且二者中间夹有机树脂或粘合剂。
注意，上述第一半导体元件夹在所述第二半导体元件和所述绝缘性衬底之间。
另外，所述第二半导体元件夹在所述第一半导体元件和所述绝缘性衬底之间。
注意，上述第二半导体元件的膜的厚度等于或少于50μm，优选在0.1μm-1μm的范围内。
另外，根据本实施方案模式制成的半导体器件能够减少用于每个半导体器件的由半导体衬底形成其集成电路的半导体元件的，典型的为单晶硅集成电路的数量。所以，跟常规的MCP相比，可以用更低成本，并更高产量地大量生产半导体器件，并且可以减少每个半导体器件的生产成本。
通过将本发明的半导体器件用于电子器具，可以使电路规模或存储容量更大的半导体器件被更多地装载到电子器具有限的体积中，这样不但可以实现电子器具的多功能化，而且可以实现电子器具的小体积化，轻巧化。特别是便携用电子器具，由于其小体积化，轻巧化被重视，所以利用本发明的半导体器件是有效的。
本发明的半导体器件可以被利用于控制驱动液晶显示器件，在其各个像素中提供有以有机发光元件为典型的发光元件的发光器件，DMD(数字微镜器件，Digital Micromirror Device)，PDP(等离子体显示屏板，Plasma Display Panel)，FED(场致发光显示器，FieldEmission Display)等的显示器件的各种电路。
例如，在有源矩阵型液晶显示器件，发光器件的情形中，选择各个像素的扫描线驱动电路，控制馈送视频信号到被选中的像素的时间的信号线驱动电路，生成馈送到扫描线驱动电路以及信号线驱动电路的信号的控制器，声频处理电路的转换器等都用TFT来形成，并且，将这些电路层叠在最好用硅片等半导体衬底制成的电路(典型的是电源电路，收发信电路，存储器，声频处理电路的放大器)上，从而获得层叠结构的半导体器件。
本发明的电子器具不仅包括上述显示器件，还包括摄像机，数码相机，护目镜式显示器(头戴式显示器)，导航系统，声频重播装置(汽车音响，音响组合等)，个人计算机，游戏机，便携式信息终端(便携式计算机，移动电话，便携式游戏机，或电子书等)，搭载有记录介质的图像重播装置(具体地说是DVD(数字通用盘，DigitalVersatile Disc)等重播记录介质并可以显示其图像的装配有显示器的装置)。特别是，本发明在被用于以笔记本计算机，便携式摄像机，便携式数码相机，护目镜式显示器(头戴式显示器)，便携式信息终端(便携式计算机，移动电话，便携式游戏机，或电子书等)为典型的便携式电子器具时有效。
附图说明
图1是本发明的半导体器件的横截面图；
图2是表示本发明的布线部分的视图；
图3A和3B分别是应用本发明的半导体器件的电子器具的模块的俯视图，以及其方框图；
图4A-4F是本发明的实施方案模式1的示意图；
图5A-5D是本发明的实施方案模式2的示意图；
图6A-6G是本发明的实施方案模式3的示意图；
图7A-7E是本发明的实施例1的示意图；
图8A-8D是本发明的实施例1的示意图；
图9是本发明的半导体器件的横截面图。
本发明的选择图为图1
具体实施方案模式
下文，将参考附图详细描述本发明的实施方案模式。本发明可以以各种不同实施方案来实现，如果是本领域的技术人员，就不难发现在不脱离本发明的宗旨及其范围的情况下，本发明的方案模式和细节可以被改为各种各样的形式。因此，本发明不能理解为被限定于本发明的实施方案模式中描述的内容范围内。
实施方案模式1
实施方案模式1
本实施方案模式用图1对本发明的半导体器件进行说明。图1示出本发明的半导体器件的横截面图。在绝缘性衬底(内插板)101上，中间夹布线层102以及热压片等的粘合层103，提供用半导体衬底制成其集成电路的半导体元件104，并且，在该半导体元件104上，中间夹热压片等的粘合层105，提供用半导体薄膜制成其集成电路的半导体元件106。在绝缘性衬底上形成了接触孔(contact hole)107，通过该接触孔连接布线层102和焊锡球等的外部终端108。
可以采用聚酰亚胺衬底，铝氧衬底，陶瓷衬底，玻璃环氧衬底等众所周知的材料作为绝缘性衬底101。另外，为了扩散产生在层叠的集成电路内的热，该绝缘性衬底的材料最好具有2-30W/mK左右的高导热率。
另外，在半导体元件的表面上形成电极垫109，110，并且该电极垫109，110和布线部分102的端子分别通过电线111，113连接在一起。另外，电极垫用铝或铝合金形成。
图2是表示布线部分102的俯视图。布线部分102包括：在绝缘性衬底101上的用于连接外部终端的金属垫221；以及通过电线(图1的111，113)与半导体元件上的电极垫(图1的109，110)连接的端子222，且该金属垫221和端子222通过布线223连接在一起。另外，布线部分是对由铜，金，铝，镍或锡制作的薄膜按所希望的图形实施蚀刻而形成。另外，半导体元件的电极垫和布线部分的端子通过使用热压法或超声波粘合法的线路接合法来实现连接。该情况下的电线是用由金，含有金的合金，铜或含有铜的合金形成的金属细线。另外，外部终端是用来连接装载用衬底的布线和半导体器件的布线部分，也就是用来连接装载用衬底和半导体元件的端子。
用半导体衬底形成其集成电路的半导体元件104使用单晶硅衬底或化合物半导体衬底形成场效应晶体管的FET(Field EffectTransistor)，双极晶体管，存储元件，二极管，光电转换元件，电阻元件，线圈(coil)，电容元件以及电感器等的元件，并用该元件构成集成电路。另外，典型的单晶硅衬底包括N型或P型单晶硅衬底(<100>衬底、<110>衬底、<111>衬底等)，而且，典型的化合物半导体衬底包括GaAs衬底、InP衬底、用于GaN系统外延的GaN衬底、SiC衬底、ZnSe衬底、GaP衬底、InSb衬底。用半导体衬底形成其集成电路的典型的半导体元件包括电源电路，收发信电路，存储器，声频处理电路的放大器。
用半导体薄膜形成其集成电路的半导体元件106是用多晶硅膜制成集成电路。具体地说，使用薄膜晶体管(TFT)，存储元件，二极管，光电转换元件，电阻元件，线圈，电容元件以及电感器等构成集成电路。另外，在显示器件的情形中，用半导体薄膜形成其集成电路的半导体元件包括选择各个像素的扫描线驱动电路，控制馈送视频信号到被选中的像素的计时的信号线驱动电路，控制器，CPU，声频处理电路的转换器等。
并且，如图9所示，也可以在绝缘性衬底(内插板)101上，中间夹布线层102以及热压片等的粘合层103，提供使用半导体薄膜形成其集成电路的半导体元件106，并且在该半导体元件106上，中间夹热压片等的粘合层105，提供使用半导体衬底形成其集成电路的半导体元件104。
注意，本实施方案模式中，描述了层叠两层半导体元件形成半导体器件的例子，但是本发明并不限于此，使用半导体衬底形成的半导体元件104以及使用半导体薄膜形成的半导体元件106可以是被层叠三层或更多层的结构。
另外，在图1中，描述了多个半导体元件分别通过电线连接到提供在绝缘性衬底的布线部分(端子)的例子，但也可以用电线将各个半导体元件彼此连接在一起。
实施方案模式2
本实施方案模式将说明有关在实施方案模式1示出的半导体器件的制作方法。本实施方案模式的半导体器件中的所有半导体元件是面朝上(face up)类型。
首先，用图4A示出使用半导体衬底形成其集成电路的半导体元件(第一半导体元件)的制作方法。在绝缘性衬底411上形成布线部分412，然后通过热压片等的粘合层414粘合使用半导体衬底形成其集成电路的半导体元件(第一半导体元件)413。注意，为了实现外部终端和半导体元件的连接，在绝缘性衬底411上形成接触孔(图1A的107)。另外，外部终端是用于电连接装载用衬底的布线和半导体元件的端子。将绝缘性衬底411，布线部分412，用粘合剂414固定的由单晶硅构成的半导体元件413等表示为A1。
其次，用图4B-4D示出使用半导体薄膜形成其集成电路的半导体元件(第二半导体元件)的制作方法。首先，如图4B所示那样，在衬底401上形成金属层402。作为金属层402的材料可以使用从W，Ti，Ta，Mo，Cr，Nd，Fe，Ni，Co，Zr，Zn，Ru，Rh，Pd，Os，Ir中选出的元素，或用上述元素作主要成分的合金材料或化合物材料制成的单层，或者上述元素或材料的叠层，或以上述的氮化物，比如氮化钛，氮化钨，氮化钽，氮化钼制成的单层或该单层的叠层。另外，在后面的剥离工艺时的条件根据金属层合金成分的比例或包含有在金属层的氧或氮成分的比例而不同。所以，通过调节上述成分的比例，可以使剥离工艺适用于各种各样的处理。氮化物层或金属层402的膜的厚度在10nm-200nm的范围内，优选在50nm-75nm的范围内。
接着，在金属层或氮化物层402上形成氧化物层403。在此，在金属膜402与氧化物层403之间形成厚度约为2nm-5nm的非晶态的氧化金属膜(氧化钨膜)405。在后继的剥离工艺中，氧化金属膜中，氧化金属膜和氧化物层的接触面或者氧化金属膜和金属膜的接触面产生分离。氧化物层403采用氧化硅，氧化氮化硅，氧化金属材料作材料，并用溅射法形成。氧化物层403的膜的厚度最好是氮化物层或金属层402的大约两倍或更厚。此处，通过用氧化硅靶的溅射法形成厚150nm-200nm的氧化硅膜。
接着，在氧化物层403上形成含有氢的层。可以采用半导体层或氮化物层作为含有氢的层。在本实施方案模式中，形成第一半导体层404作为含有氢的层。然后，实施热处理以扩散含有氢的材料膜中含有的氢。此热处理可以与形成晶质半导体薄膜的工艺分别地进行，或为节省该加热处理工序可以与形成晶质半导体薄膜的工艺兼用。例如，在含有氢的非晶硅膜被用作含有氢的膜并被加热以形成多晶硅膜的情况下，500℃或更高温度下的用于晶化的热处理能够同时实现多晶硅膜的形成和氢的扩散。此时，形成在金属层402和氧化物层403之间的金属氧化物层405作为具有结晶性的金属氧化物层间绝缘膜435。
接着，如图4C所示，用众所周知的方法，按所希望的形状蚀刻第一半导体层404，以便形成第二半导体层434，第二半导体层434由TFT(图中没有表示出)构成。此时，第二半导体层434的膜的厚度为50μm或更薄，优选在0.1μm-1μm的范围内。
随后，用能够被剥离的粘合剂407粘合用作固定第2半导体层434的作为支架的第二衬底406。另外，第二衬底406最好采用其强度高于第一衬底401的衬底，优选典型的石英衬底，金属衬底，陶瓷衬底。作为能够被剥离的粘合剂407的材料，可以采用由有机材料制成的粘合剂，诸如反应剥离型粘合剂，热剥离型粘合剂，UV剥离型粘合剂等的光剥离型粘合剂，厌氧剥离型粘合剂等各种剥离型粘合剂。另外，粘合剂407也可以使用双面都具有粘合层的材料，且该粘合层是由能够被剥离的粘合剂形成(典型的比如双面胶带，双面薄板)。
在图4C中，将第一衬底401以及在其上形成的金属层402称为剥离体450。而且，将从氧化物层403到第二半导体层434(亦即，夹在金属层402和用于固定第二衬底406的能够被剥离的粘合剂407之间的层)称为待剥离体451。
其次，如图4D所示，用物理方法撕剥剥离体450和待剥离体451。在金属氧化物层435中，氧化物层403和金属氧化层435的接触面，或者金属氧化层435和金属层402的接触面产生分离，因此用比较小的力就可以将剥离体450和待剥离体451撕剥下来。
根据上述工艺，可以从剥离体450上分离待剥离体451。在此，将使用待剥离体451以及能够从其上剥离下来的粘合剂407被固定的第二衬底404表示为B1。
其次，分割第二衬底以及固定在其上的待剥离层B1，形成芯片状的待剥离层(下文中表示为C1)。芯片状的待剥离层包括第二半导体元件。第二半导体元件1434是被分割了的第二半导体层434。另外，用粘合剂1407在被分割了的第二衬底(下文中表示为第三衬底1406)上固定第二半导体元件1434。另外，粘合剂1407的与固定有第二半导体元件的相反侧形成有氧化物层1403(被分割了的氧化物层403)。
接着，如图4E所示，在图4A所示的A1上固定图4D所示的C1。确切地说，形成在绝缘性衬底411上的第一半导体元件413的表面上，用粘合剂421粘合待剥离体451，具体地说是粘合形成有第二半导体元件的氧化物层。另外，在氧化物层403和粘合剂421之间如夹导热性好的材料，可以提高散热性。
重要的是，用粘合剂421粘合的待剥离体451和第一半导体元件413的粘合性高于用由有机材料制成的能够剥离的粘合剂407粘合的第二衬底406和待剥离体451的粘合性。另外，反应硬化型粘合剂，热硬化型粘合剂、紫外线硬化型等的光硬化型粘合剂，厌氧型粘合剂等各种硬化型粘合剂可以作为粘合剂421。另外，粘合剂421也可以使用双面都具有粘合层的材料，且该粘合层是由能够被剥离的粘合剂形成(典型的比如双面胶带，双面薄板)。
接着，如图4F所示，从第二半导体元件1434剥离作为支架的第三衬底1406和能够剥离的粘合剂1407。使由有机材料制成的能够剥离的粘合剂1407因热，光，湿度而产生反应，或化学反应(例如，水，氧)，这样，就可以从第二半导体元件1434将第三衬底1406和能够剥离的粘合剂1407剥离下来。
接下来，用电线426，427连接各个半导体元件的电极垫422，423和布线部分的端子424，425。首先，用线路接合方式将提供在第一半导体元件上的电极垫423和布线部分的端子424连接在一起，然后，通过同样的工艺将提供在第二半导体元件上的电极垫422和布线部分的端子425连接在一起。
接着，也可以用真空密封方式或树脂密封方式对半导体元件和电线进行密封。当使用真空密封方式时，一般使用陶瓷，金属或玻璃等的盒子进行密封。当使用树脂密封方式时，具体使用成形树脂(moldresin)。在本实施方案模式中，因第二半导体元件也作为保护第一半导体元件的保护层发挥作用，所以不一定必须要密封半导体元件和电线，但通过密封，可以增加半导体元件的机械强度，并且阻挡来自邻接电路的电磁噪音。这之后，通过绝缘性衬底的接触孔连接布线部分412的端子和外部终端429。
根据上述工艺，可以制成叠层结构的半导体器件，该叠层包括使用半导体衬底形成其集成电路的半导体元件，典型的是使用单晶硅衬底形成其集成电路的半导体元件，以及使用半导体薄膜形成其集成电路的半导体元件，典型的是使用多晶硅薄膜形成其集成电路的半导体元件。
另外，使用相同的工艺，在第二半导体元件上进一步层叠第三半导体元件，第四半导体元件，这样，可以制作更加高集成化的半导体器件。另外，将第二半导体元件转移到第一半导体元件的方法不局限于上述工序，也可以应用其他工序。
根据本实施方案模式制成的半导体器件是层叠由集成电路形成的半导体元件而形成的半导体器件，因由集成电路形成的半导体元件的一部分是用半导体薄膜而形成，所以该半导体器件具有高集成化而且小体积的特征。
另外，根据本实施方案模式制成的半导体器件能够减少用于每个半导体器件的由半导体衬底形成其集成电路的半导体元件的，典型的为单晶硅集成电路的数量。所以，跟常规的MCP相比，可以用更低成本，并更高产量地大量生产半导体器件，并且可以减少每个半导体器件的生产成本。
实施方案模式3
本实施方案模式中将说明其结构和实施方案模式1以及实施方案模式2不同的半导体器件。本实施方案模式的第一半导体元件是倒装芯片结构(flip chip结构，又称face down结构)，从这一点看，其和实施方案模式2不同。
首先，用图5A-5D示出本实施方案模式的半导体器件的横截面图。在绝缘性衬底501上的布线部分502，由半导体衬底制成的第一半导体元件503的电极垫504，用凸块等的连接端子505连接在一起。另外，用树脂等固定第一半导体元件503和绝缘性衬底501以及绝缘性衬底上形成的布线部分502。另外，绝缘性衬底501上形成有连接外部终端和半导体元件的接触孔(没有图示出)，在该接触孔处布线部分502和外部终端连接在一起。另外，外部终端和装载用衬底的布线连接在一起。将绝缘性衬底501，布线部分502，第一半导体元件503的电极垫504，凸块505，固定这些的树脂506等表示为A2。
接着，执行和实施方案模式2相同的工艺，用固定在第三衬底1406上的半导体膜形成图4E所示的第二半导体元件1434。这时的第二半导体元件1434的膜的厚度不多于50μm，最好是0.1-1μm。另外，用能够剥离的粘合剂1407固定第三衬底1406和用半导体膜形成的第二半导体元件1434。(将第三衬底以及固定在第三衬底的第二半导体元件表示为C1)(图5B)。
其次，用粘合剂511将图5B的C1固定在图5A的A2上。具体地说，用粘合剂511在形成于绝缘性衬底501上的第一半导体元件503的表面上粘合形成有第二半导体元件的氧化膜层1403。另外，如在氧化物层1403和粘合剂511中间夹导热率高的材料，可以提高散热性。这之后，执行和实施方案模式1相同的工艺，从第二半导体元件1434剥离作为支架的第三衬底1406和能够剥离的粘合剂1407。(图5C)
然后，如图5D所示，第二半导体元件1434的电极垫512和布线部分502的端子513由电线514连接在一起。之后，也可以执行和实施方案模式2相同的工艺，对绝缘性衬底501上层叠的集成电路434，503以及电线514进行密封。然后，在绝缘性衬底501的接触孔处连接布线部分502的电极垫和外部终端516。
根据上述工艺，可以制成叠层结构的半导体器件，该叠层包括使用半导体衬底形成其集成电路的半导体元件，典型的是使用单晶硅衬底形成其集成电路的半导体元件，以及使用半导体膜形成其集成电路的半导体元件，典型的是使用多晶硅薄膜形成其集成电路的半导体元件。
根据本实施方案模式制成的半导体器件是层叠集成电路而形成的半导体器件，因由集成电路形成的半导体元件的一部分是用半导体薄膜而形成，所以该半导体器件具有高集成化而且小体积的特征。
另外，根据本实施方案模式制成的半导体器件能够减少用于每个半导体器件的由半导体衬底形成其集成电路的半导体元件的，典型的为单晶硅集成电路的数量。所以，跟常规的MCP相比，可以用更低成本，并更高产量地大量生产半导体器件，并且可以减少每个半导体器件的生产成本。
还有，因使用半导体衬底制成的集成电路是倒装芯片形式，所以用于连接集成电路的电极垫和布线部分的端子的电线数量可以被减少，因此可以制作体积更小的半导体器件。
实施方案模式4
本实施方案模式中将说明其结构和实施方案模式1至实施方案模式3不同的半导体器件的制作方法。本实施方案模式的所有集成电路都是倒装芯片形式，从这一点看，其和实施方案模式2以及实施方案模式3不同。
首先，用图6A-6G示出本实施方案模式的半导体器件的横截面图。在图6A示出的用半导体衬底形成集成电路的第一半导体元件503具有和实施方案模式3相同的结构(图5A中的A2)，其具有绝缘性衬底501，第一布线部分502，第一半导体元件503的电极垫504，凸块505，以及固定上述部件的树脂506等。
其次，如图6B所示，在第一半导体元件上中间夹绝缘层601形成第二布线部分602。
接着，执行和实施方案模式2相同的工艺，用固定在第二衬底406上的半导体膜形成由集成电路构成的第二半导体层434。另外，用能够剥离的粘合剂407固定第二衬底406和用半导体膜形成由集成电路构成的第二半导体层434。(将第二衬底以及固定在第二衬底的第二半导体元件表示为B1)(图6C)。
其次，如图6D所示，用粘合剂604将图6C的B1固定在第四衬底603。具体地说，用粘合剂604在第四衬底603上粘合形成有第二半导体层434的氧化膜层403。第四衬底603可以采用玻璃，有机树脂，金属，塑料，或陶瓷等作为衬底材料。通过使用膜厚度薄的膜作为第四衬底，可以减小半导体器件的体积。另外，为了提高散热性，第四衬底最好采用诸如类金刚石碳的DLC(Diamond Like Carbon)，铜，铝等导热率高的材料。
接着，从第二半导体层434剥离作为支架的第二衬底406和能够剥离的粘合剂407。这之后，最好对从第二集成电路的表面暴露出来的电极布线等的表面执行清洗处理或氧等离子处理来清洁其表面。然后，分割第四衬底，从而形成芯片状的半导体元件。在此，将芯片状的第四衬底(下文中将其称为第五衬底1604)，以及转移到其上的第二半导体元件1434表示为C2(图6E)。另外，在第二半导体元件1434上用粘合层粘合在其表面形成的氧化膜层1403和第五衬底1604。
然后，如图6F所示，在第一半导体元件A3上粘合第二半导体元件C2。具体地说，一边对准第二布线部分602和第二半导体元件表面的电极垫605的位置一边用粘合剂进行粘合。在本实施方案模式中，用各向异性导电膜的ACF(Anisotropic Conductive Film)或者各向异性导电聚合物(Anisotropic Conductive Polymer)606施压于在第一半导体元件的表面形成的第二布线部分602和第二半导体元件表面的电极垫605。
然后，如图6G所示，在绝缘性衬底501的接触孔处连接布线部分502的电极垫和外部终端608。
根据上述工艺，可以制成叠层结构的半导体器件，该叠层包括使用半导体衬底形成其集成电路的半导体元件，以及使用半导体薄膜形成其集成电路的半导体元件。
根据本实施方案模式制成的半导体器件是层叠集成电路而形成的半导体器件，因由集成电路形成的半导体元件的一部分是用半导体薄膜而形成，所以该半导体器件具有高集成化而且小体积的特征。
另外，根据本实施方案模式制成的半导体器件能够减少用于每个半导体器件的由半导体衬底形成其集成电路的半导体元件的，典型的为单晶硅集成电路的数量。所以，跟常规的MCP相比，可以用更低成本，并更高产量地大量生产半导体器件，并且可以减少每个半导体器件的生产成本。
还有，因所有在本实施方案模式制成的半导体器件的半导体元件都是倒装芯片形式，不使用连接半导体元件的电极垫和布线部分的端子的电线，因此可以制作体积更小的半导体器件。第三衬底采用具有绝缘性的诸如玻璃，有机树脂，或陶瓷等作为衬底材料时，因半导体器件的表面绝缘，所以不用使用成形树脂来密封。因此，可以制作体积更小的半导体器件。
实施例
实施例1
本实施例用图7和图8说明根据实施方案模式1所示的工艺获得的半导体器件的制作方法的例子，该半导体器件是层叠由单晶硅衬底制作的集成电路(第一集成电路)和由多晶硅膜制作的集成电路(第二集成电路)而构成的叠层。
如图7A所示，用溅射法在玻璃衬底(第一衬底700)上形成钨膜(膜的厚度为10nm-200nm，优选50nm-75nm)作为金属膜701，然后，在不暴露于大气的情况下，形成并叠加氧化硅膜(膜的厚度为150nm-200nm)702作为氧化膜。此处，在钨膜701与氧化硅膜702之间形成厚度约为2nm-5nm的非晶态的氧化钨膜703。注意，因为溅射法会在衬底边缘形成膜，优选用O2灰化等选择性地清除掉形成在衬底边缘的钨膜和氧化硅膜。在后继的剥离工艺中，钨膜和氧化钨膜的接触面，氧化钨膜中或者氧化钨膜和氧化硅膜的接触面产生分离。
另外，金属膜701也可以利用含有钨的合金，例如W-Mo合金来代替钨膜，调节该合金的成分比例来控制剥离的容易程度。另外，也可以用离子注入技术或离子掺杂技术，将氮元素掺杂到氧化物膜中从而使剥离变得困难，或将氧元素掺杂到氧化物膜中从而使剥离变得容易。
接着，用PCVD法形成作为基底绝缘膜的氧氮化硅膜(膜的厚度为100nm，图中没有表示出)，形成并层叠非晶硅膜704(膜的厚度为54nm)而不于暴露于大气。
接着，可以采用已知的晶化技术(例如固相生长或激光晶化，以及利用金属催化剂的晶化方法)来形成多晶硅膜。然后，按所希望的形状实施图案从而形成多晶硅区域，然后制作以该多晶硅区域作为激活区的TFT(p沟道型TFT 705，708和n沟道型TFT 706，707)。此处，适当地形成栅绝缘膜，形成栅电极，并通过掺杂杂质到激活区形成源区/漏区，然后形成层间绝缘膜，形成源电极或漏电极，并实施激活处理。
本实施例采用利用金属催化剂的晶化方法来获得多晶硅膜。确切地说，掺杂金属元素Ni到非晶硅膜，并进行550℃下4小时的热处理。该热处理工艺同时也实现了氧化钨膜703的晶化。然后，用连续振荡型激光器辐照多晶硅膜来提高该多晶硅膜的结晶性，并且，按所希望的形状蚀刻多晶硅膜并使TFT的沟道长方向和激光束的扫描方向一致。使用这样的多晶硅膜作为激活区的TFT能够获取高场效应迁移度。另外，互相组合p沟道型TFT 705和n沟道型TFT 706，以及p沟道型TFT 708和n沟道型TFT 707从而构成CMOS电路(图7B)。
接着，形成层间绝缘膜709，然后形成接触孔并且形成连接于TFT的布线710，711作为电极垫(图7C)。
然后，如图7D所示，将可溶于水或醇类的粘合材料721涂敷在整个表面，并进行焙烧。环氧树脂、丙烯酸树脂、硅树脂等中任何一种可以构成上述粘合剂。在此，用旋涂涂敷由水溶性树脂(东亚合成制：VL-WSHL10)制成的膜(膜的厚度为30μm)721，进行初步固化后实现正式固化。
为了使后面的剥离工艺容易被实施，下述工艺用于部分降低钨膜701和氧化硅膜702的粘合性。用于部分降低粘合性的处理是激光照射，其中用激光沿着要剥离区域的周边部分照射钨膜701或氧化硅膜702，或沿着要剥离区域的周边部分从外部施加局部压力，以损坏氧化硅膜702的层内的一部分或交接面的一部分。具体地说，用金刚石笔等垂直压下硬针，并且边移动所述层边施加负荷。最好使用划线器装置并且将下压量设在1mm，以便边移动所述层边施加压力。以这种方式在剥离之前对容易发生剥离现象的部分，实施选择性(部分地)降低粘合性的预处理，即引发机制是重要的，从而避免了剥离失败并且提高了成品率。
然后，使用能够剥离的粘合介质(双面薄板)722粘贴由水溶性树脂制成的膜721到第二衬底723。并且，使用能够剥离的粘合介质(双面薄板)722粘贴第三衬底到第一衬底700(图中没有表示出)。第三衬底保护第一衬底700在后面的工艺中不受损伤。第二衬第723和第三衬第最好采用强度比第一衬底700更高的衬底，比如，石英衬底等。
然后，如图7E所示，从部分降低粘合性的区域开始剥离，用物理方法剥离提供有钨膜701的第一衬底700。利用较小的力就可剥离衬底(例如，利用人的手，利用喷嘴吹出气体的吹压，利用超声，等等)。在本实施例中，氧化硅膜和氧化钨膜的接触面产生分离。根据上述步骤，可以从第一衬底700上分离氧化硅膜702上形成的由多晶硅膜制成的集成电路。另外，氧化钨如残留在氧化硅膜702的表面，氧化硅膜702和第一集成电路之间的粘合力有可能因此而变小，所以，用蚀刻等方法完全清除该残留物从而提高粘合力。这之后，分割第二衬底723，形成第二集成电路。
接着，如图8A所示，在绝缘性衬底730上形成布线部分731，然后用粘合剂在该绝缘性衬底和布线部分之上安装由单晶硅衬底制成的第一集成电路734。注意，为了实现连接布线部分731和焊料球等外部终端，在绝缘性衬底730上形成接触孔。
所述布线部分是根据光刻方式用金的合金形成图案。
而且，第一集成电路采用已知的技术形成场效应晶体管的FET，并用该FET形成集成电路。本实施例在单晶硅衬底750上形成并互相组合N沟道金属氧化物半导体场效应晶体管的NMOSFET(N-channel metaloxide semiconductor FET)735，736和P沟道金属氧化物半导体场效应晶体管的PMOSFET(P-channel metal oxide semiconductor FET)737，738，从而构成互补型MOS的CMOS(Complementary MOS)电路。注意，本实施例示出的NMOSFET 735，736和PMOSFET 737，738是由源区/漏区752，753，栅电极754和层间绝缘膜755，756构成的(在此，以NMOSFET735为典型来举例说明)，而且，用于与各个FET连接的布线的电极垫(图8A中的739，740)暴露出于层间绝缘膜缘膜的表面。并且，各个FET被氧化膜751分离。所述氧化膜的形成方法可以用选择氧化法(又称局部氧化法，即LOCOS法：Local Oxidation of Silicon method)或沟槽隔离法(trench isolation)。
注意，在同一半导体衬底上形成NMOSFET和PMOSFET的情况下，就需要提供具有不同于衬底的导电性的导电性区域(阱)，其方法包括P阱系统，其中在N型衬底上形成P阱，在P阱上形成N沟道晶体管以及在N型衬底上形成P沟道晶体管；N阱系统，其中在P型衬底上形成N阱，在N阱上形成P沟道晶体管以及在P型衬底上形成N沟道晶体管；以及双阱系统，在N型或P型衬底上形成N阱和P阱，在N阱上形成P沟道晶体管以及在P阱上形成N沟道晶体管。而且，虽然示出具有一个沟道形成区的PET，但并不限制于此，并且FET可以具有多个沟道。
然后，如图8B所示，用粘合材料741在用硅衬底制成的第一集成电路734上粘合形成有第二集成电路的氧化硅层1702。另外，第二集成电路是在氧化硅层1702上形成的CMOS电路，形成有电极垫。还有，该表面上固定有用水溶性粘合剂1721和能够剥离的粘合介质1722分离了的第二衬底(下文中称为第三衬底1723)。重要的是，用粘合材料741粘合的氧化硅层1702和第一集成电路734的粘合性高于用水溶性树脂1721以及能够剥离的粘合介质1722粘合的第三衬底1723和第二集成电路的粘合性。本实施例使用粘合薄板作为粘合材料741，而且一边对准第一和第二集成电路的位置使其不覆盖电极垫739，740，一边实施粘合。
接着，如图8C所示，从能够剥离的粘合介质(双面薄板)1722分离第三衬底1723后，从水溶性树脂1721剥离能够剥离的粘合介质(双面薄板)1722。另外，也可以将双面薄板和第三衬底二者同时一起从水溶性树脂剥离。
然后，用水溶化水溶性树脂1721并清除掉该水溶性树脂1721。如果在此有水溶性树脂被残留，会成为次品的原因，所以优选通过清洗处理或O2等离子处理来清洁电极垫710，711的表面。
接着，图8D所示，第一集成电路上的电极垫739，740和布线部分的端子741，742分别通过电线743，744电连接在一起，然后，第二集成电路上的电极垫710，711和布线部分的端子745，746分别通过电线747，748电连接在一起。
通过以上步骤，可以制作由单晶硅衬底制成的集成电路(第一集成电路)和多晶硅膜制成的集成电路(第二集成电路)层叠而形成的半导体器件。
实施例2
本实施例以本发明的电子器具之一的移动电话为例，用图3A说明封装实际被搭载到电子器具的情况。
图3A表示的移动电话的模块是在印刷线路板816上搭载层叠于存储器811上的CPU 802(图3A中的区域802/811)，电源电路803，层叠于声频处理电路829上的控制器801(图3A中的领域801/829)，收发信电路804，以及其他的，电阻，缓冲器，电容元件等元件。另外，屏板(panel)800通过FPC 808(柔性印刷电路，Flexible PrintedCircuit)和印刷线路板816粘附在一起。屏板800上安装有发光元件提供在各个像素的像素单元805，选择该像素单元805具有的像素的扫描线驱动电路806，馈送声频信号到被选中的像素的信号线驱动电路807。
电源电压以及从键盘输入的各种信号通过配备有多个输入终端的印刷线路板用的程序接口(interface，I/F)809馈送到印刷线路板816。另外，用于和天线之间的信号收发信的天线端口(antenna port)810提供在印刷线路板816上。
另外，本实施例用FPC 808将屏板800连接到印刷线路板816上，然而不一定必须是该结构。也可以采用玻璃底板上载芯片的COG(ChipOn Glass)方式，在屏板800上直接搭载控制器801，声频处理电路829，存储器811，CPU 802或电源电路803。
而且，在印刷线路板816中，存在着形成在各个布线之间的电容器以及布线本身具有的电阻，由此会引起电源电压和信号的噪声或使信号传递变得迟钝。因此，在印刷线路板816上提供诸如电容器或缓冲器之类的各种元件，以便防止电源电压和信号的噪声或防止信号传递变得迟钝。
图3B是图3A所示的模块的方框图。
本实施例中，存储器811包含VRAM 832，DRAM 825，快闪存储器(flash memory)826。VRAM 832存储显示在屏板上的图像数据，DRAM825存储图像数据或声频数据，快闪存储器826存储各种程序。随着存储器容量的提高，装载的面积也扩大，所以，最好用单晶硅片制造存储器。
电源电路803给屏板800，控制器801，CPU 802，声频处理电路829，存储器811，收发信电路804提供电源电压。另外，依据屏板的规格，电源电路803也可以装备有电源。电源电路具有稳定控制向屏板，控制器，CPU等供给电流的功能。所以，能够通过大量电流的双极晶体管适合作为该元件，其结果是电源电路最好用硅片制造。
CPU 802具有控制信号生成电路820，译码器821，寄存电路822，演算电路823，RAM 824，CPU用的接口(interface)835等。通过接口835输入到CPU 802的各种信号暂时存储在寄存电路822后，被输入到演算电路823，译码器821等。演算电路823根据输入来的信号进行演算，然后指定传送各种命令的场所。另一方面，输入到译码器821的信号在译码器821处被破译后，被馈送到控制信号生成电路820中。控制信号生成电路820根据输入来的信号生成包含各种指令的信号，该信号被馈送到由演算电路823指定的场所，具体地说，馈送到存储器811，收发信电路804，声频处理电路829以及控制器801等等。通过使用以多晶硅作为激活区的TFT来制作CPU，可以使其厚度减薄。
存储器811，收发信电路804，声频处理电路829以及控制器801各自依据接收到的指令进行运作。下文将就其运作进行简单说明。
从键盘831输入的信号通过程序接口809被馈送到搭载在印刷线路板816上的CPU 802。控制信号生成电路820依据从键盘831输入的信号，将存储在VRAM 832的图像数据转换为预定格式，并馈送到控制器801。
控制器801配合屏板的规格对从CPU 802馈送来的包括图像数据的信号执行数据处理，然后将处理过的信号馈送到屏板800。控制器801依据从电源电路803输入的电源电压或从CPU输入的各种信号，生成Hsync信号，Vsync信号，时钟信号CLK，交流电压(AC Cont)，并馈送到屏板800。控制器可以使用以多晶硅作为激活区的TFT来制作。
收发信电路804处理天线833收发到的作为电波的信号，收发信电路804具体包括隔离器，带通滤波器，VCO(压控振荡器，VoltageControlled Oscillator)，LPF(低通滤光片，Low Pass Filter)，耦合器，平衡-不平衡转换器(balun)等的高频电路。收发信电路804依据CPU802的指令，将收发信号中包含声频信息的信号，馈送到声频处理电路829。收发信电路因其中包括高频电路，所以是用GaAs半导体衬底或硅片制成。
依据CPU802的指令被馈送来的包含声频信息的信号在声频处理电路829中被解调成声频信号，并被馈送到扬声器828。另外，从传声器827传送来的声频信号在声频处理电路829中被调制，并依据CPU802的指令被传送到收发信电路804。声频处理电路是由放大器和转换器来形成。因放大器的特性的不均匀会严重影响到从扬声器输出的音质，所以放大器优选采用其不均匀特性少的硅片。另一方面，可以用多晶硅形成的TFT来制作转换器，这样可以使其厚度减薄。
根据实施例1制作的半导体器件可以应用于层叠在存储器811上的CPU 802(图3A中的区域802/811)，或应用于层叠在声频处理电路829上的控制器801(图3A中的区域801/829)。注意，本实施例虽然示出了具有上述结构的半导体器件，但本发明并不局限于这种结构。例如，也可以采用以下的层叠结构，即将能够用TFT形成的电路(控制器801，CPU 802，声频处理电路829的转换器，选择像素部分的像素的扫描线驱动电路806，馈送声频信号到被选中的像素的信号线驱动电路807)任意层叠在最好用硅片等半导体衬底制成的电路(典型的是电源电路803，收发信电路804，存储器811，声频处理电路829的放大器)之上。
根据本发明制造的半导体器件是将由集成电路形成的半导体元件层叠而形成，因其用半导体薄膜形成该半导体元件的一部分，所以该半导体器件的特征是高集成化和小体积。
另外，根据本实施方案模式制成的半导体器件能够减少用于每个半导体器件的由半导体衬底形成其集成电路的半导体元件的，典型的为单晶硅集成电路的数量。所以，跟常规的MCP相比，可以用更低成本，并更高产量地大量生产半导体器件，并且可以减少每个半导体器件的生产成本。
而且，通过将用半导体衬底形成其集成电路的半导体元件适用于电源电路，收发信电路，存储器或声频处理电路的放大器等的高频电路，高集成电路或者高容量电路，并且，通过将用半导体薄膜形成其集成电路的半导体元件适用于控制器，CPU，声频处理电路的转换器，选择像素部分的像素的扫描线驱动电路或馈送声频信号到被选中的像素的信号线驱动电路等的能够用TFT形成的电路，可以制作体积更加小(也就是小面积加上低高度)，功能更加高(典型的是增加存储器的容量等)的半导体器件，所以可以在电子器具有限的体积中更多地搭载该半导体器件，这样不但可以实现电子器具的多功能化，而且可以实现电子器具的小体积化，轻巧化。特别是便携用电子器具，因其小体积化，轻巧化被重视，所以利用本发明的半导体器件是有效的。

Claims (38)

1.一种半导体器件，包括：
包括布线部分的绝缘性衬底；
包括半导体衬底的第一半导体元件，其中所述第一半导体元件形成在所述绝缘性衬底上；和
包括多个薄膜晶体管的第二半导体元件，其中所述第二半导体元件形成在所述第一半导体元件上，
其中所述第一半导体元件和第二半导体元件电连接到所述布线部分。
2.根据权利要求1的半导体器件，其中所述半导体衬底至少是单晶硅衬底和化合物半导体衬底之一。
3.根据权利要求1的半导体器件，其中所述第一半导体元件至少包括电源电路，收发信电路，存储器，或声频处理电路的放大器中之一种。
4.根据权利要求1的半导体器件，其中第二半导体元件至少包括像素部分的扫描线驱动电路，信号线驱动电路，控制器，CPU，或声频处理电路的变换器中之一种。
5.根据权利要求1的半导体器件，其中所述绝缘性衬底包括选自聚酰亚胺，铝氧，陶瓷，玻璃环氧树脂的材料。
6.一种半导体器件，包括：
包括布线部分的绝缘性衬底；
包括半导体衬底的第一半导体元件，其中所述第一半导体元件形成在该绝缘性衬底上；和
包括多个薄膜晶体管的第二半导体元件，其中所述第二半导体元件形成在所述第一半导体元件上；
其中所述第一半导体元件和所述第二半导体元件通过电线电连接到布线部分。
7.根据权利要求6的半导体器件，其中所述半导体衬底至少是单晶硅衬底和化合物半导体衬底之一。
8.根据权利要求6的半导体器件，其中所述第一半导体元件至少包括电源电路，收发信电路，存储器和声频处理电路的放大器中之一种。
9.根据权利要求6的半导体器件，其中所述第二半导体元件至少包括像素部分的扫描线驱动电路，信号线驱动电路，控制器，CPU，或声频处理电路的变换器中之一种。
10.根据权利要求6的半导体器件，其中所述绝缘性衬底包括选自聚酰亚胺，铝氧，陶瓷，玻璃环氧树脂的材料。
11.一种半导体器件，包括：
包括布线部分的绝缘性衬底；
包括半导体衬底的第一半导体元件，其中所述第一半导体元件形成在所述绝缘性衬底上，并且在二者中间夹有第一粘合剂；和
包括多个薄膜晶体管的第二半导体元件，其中所述第二半导体元件形成在所述第一半导体元件上，并且在二者中间夹有第二粘合剂，
其中第一半导体元件和第二半导体元件电连接到布线部分。
12.根据权利要求11的半导体器件，其中该半导体衬底至少是单晶硅衬底和化合物半导体衬底之一。
13.根据权利要求11的半导体器件，其中所述第一半导体元件至少包括电源电路，收发信电路，存储器，或声频处理电路的放大器中之一种。
14.根据权利要求11的半导体器件，其中所述第二半导体元件至少包括像素部分的扫描线驱动电路，信号线驱动电路，控制器，CPU，或声频处理电路的变换器中之一种。
15.根据权利要求11的半导体器件，其中所述绝缘性衬底包括选自聚酰亚胺，铝氧，陶瓷，玻璃环氧树脂的材料。
16.一种半导体器件，包括：
包括布线部分和多个接触孔的绝缘性衬底；
包括半导体衬底的第一半导体元件，其中所述第一半导体元件形成在所述绝缘性衬底上；和
包括多个薄膜晶体管的第二半导体元件，其中第二半导体元件形成在该第一半导体元件上，
其中第一半导体元件和第二半导体元件电连接到布线部分。
17.根据权利要求16的半导体器件，其中该半导体衬底至少是单晶硅衬底和化合物半导体衬底之一。
18.根据权利要求16的半导体器件，其中所述第一半导体元件至少包括电源电路，收发信电路，存储器和声频处理电路的放大器中之一种。
19.根据权利要求16的半导体器件，其中所述第二半导体元件至少包括像素部分的扫描线驱动电路，信号线驱动电路，控制器，CPU，声频处理电路的变换器中之一种。
20.根据权利要求16的半导体器件，其中所述绝缘性衬底包括选自聚酰亚胺，铝氧，陶瓷，玻璃环氧树脂的材料。
21.根据权利要求16的半导体器件，其中所述多个接触孔充满多个焊料球。
22.一种半导体器件，包括：
包括布线部分的绝缘性衬底；
包括半导体衬底的第一半导体元件，其中所述第一半导体元件形成在所述绝缘性衬底上，并且二者中间夹有第一粘合剂；和
包括多个薄膜晶体管的第二半导体元件，其中所述第二半导体元件形成在所述第一半导体元件上，并且在二者中间夹有第二粘合剂，
其中所述第一半导体元件和第二半导体元件通过电线电连接到布线部分。
23.根据权利要求22的半导体器件，其中该半导体衬底至少是单晶硅衬底和化合物半导体衬底之一。
24.根据权利要求22的半导体器件，其中所述第一半导体元件至少包括电源电路，收发信电路，存储器和声频处理电路的放大器中之一种。
25.根据权利要求22的半导体器件，其中所述第二半导体元件至少包括像素部分的扫描线驱动电路，信号线驱动电路，控制器，CPU，声频处理电路的变换器中之一种。
26.根据权利要求22的半导体器件，其中所述绝缘性衬底包括选自聚酰亚胺，铝氧，陶瓷，玻璃环氧树脂的材料。
27.一种半导体器件，包括：
包括布线部分和多个接触孔的绝缘性衬底；
包括半导体衬底的第一半导体元件，其中所述第一半导体元件形成在所述绝缘性衬底上；和
包括多个薄膜晶体管的第二半导体元件，其中第二半导体元件形成在该第一半导体元件上，
其中所述第一半导体元件和第二半导体元件通过电线电连接到布线部分。
28.根据权利要求27的半导体器件，其中该半导体衬底至少是单晶硅衬底和化合物半导体衬底之一。
29.根据权利要求27的半导体器件，其中所述第一半导体元件至少包括电源电路，收发信电路，存储器和声频处理电路的放大器中之一种。
30.根据权利要求27的半导体器件，其中所述第二半导体元件至少包括像素部分的扫描线驱动电路，信号线驱动电路，控制器，CPU，声频处理电路的变换器中之一种。
31.根据权利要求27的半导体器件，其中所述绝缘性衬底包括选自聚酰亚胺，铝氧，陶瓷，玻璃环氧树脂的材料。
32.根据权利要求27的半导体器件，其中所述多个接触孔充满多个焊料球。
33.一种半导体器件，包括：
包括布线部分和多个接触孔的绝缘性衬底；
包括半导体衬底的第一半导体元件，其中所述第一半导体元件形成在所述绝缘性衬底上，并且二者中间夹有第一粘合剂；和
包括多个薄膜晶体管的第二半导体元件，其中所述第二半导体元件形成在所述第一半导体元件上，并且在二者中间夹有第二粘合剂，
其中第一半导体元件和第二半导体元件电连接到布线部分。
34.根据权利要求33的半导体器件，其中该半导体衬底至少是单晶硅衬底和化合物半导体衬底之一。
35.根据权利要求33的半导体器件，其中所述第一半导体元件至少包括电源电路，收发信电路，存储器和声频处理电路的放大器中之一种。
36.根据权利要求33的半导体器件，其中所述第二半导体元件至少包括像素部分的扫描线驱动电路，信号线驱动电路，控制器，CPU，声频处理电路的变换器中之一种。
37.根据权利要求33的半导体器件，其中所述绝缘性衬底包括选自聚酰亚胺，铝氧，陶瓷，玻璃环氧树脂的材料。
38.根据权利要求33的半导体器件，其中所述多个接触孔充满多个焊料球。
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KR20040060781A (ko) 2004-07-06
EP1434264A2 (en) 2004-06-30
US20040130020A1 (en) 2004-07-08
TWI359468B (en) 2012-03-01
US7863754B2 (en) 2011-01-04
US20060163710A1 (en) 2006-07-27
TW200709309A (en) 2007-03-01
KR101013482B1 (ko) 2011-02-14
TW200416905A (en) 2004-09-01
EP1434264A3 (en) 2017-01-18
TWI318782B (en) 2009-12-21
CN101577271B (zh) 2012-08-08
CN100530576C (zh) 2009-08-19
US7037752B2 (en) 2006-05-02

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