KR100448428B1 - 자기 기억 장치 및 자성체 기판 - Google Patents

자기 기억 장치 및 자성체 기판 Download PDF

Info

Publication number
KR100448428B1
KR100448428B1 KR10-2001-0057198A KR20010057198A KR100448428B1 KR 100448428 B1 KR100448428 B1 KR 100448428B1 KR 20010057198 A KR20010057198 A KR 20010057198A KR 100448428 B1 KR100448428 B1 KR 100448428B1
Authority
KR
South Korea
Prior art keywords
mram
cell array
memory cell
lines
magnetic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR10-2001-0057198A
Other languages
English (en)
Korean (ko)
Other versions
KR20020065323A (ko
Inventor
구니끼요다쯔야
에이뀨가쯔미
마에다시게노부
Original Assignee
미쓰비시덴키 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 미쓰비시덴키 가부시키가이샤 filed Critical 미쓰비시덴키 가부시키가이샤
Publication of KR20020065323A publication Critical patent/KR20020065323A/ko
Application granted granted Critical
Publication of KR100448428B1 publication Critical patent/KR100448428B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
    • G11C11/15—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1675—Writing or programming circuits or methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01021—Scandium [Sc]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01025—Manganese [Mn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01039—Yttrium [Y]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01077—Iridium [Ir]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Physics & Mathematics (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Hall/Mr Elements (AREA)
  • Semiconductor Memories (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Thin Magnetic Films (AREA)
KR10-2001-0057198A 2001-02-06 2001-09-17 자기 기억 장치 및 자성체 기판 Expired - Fee Related KR100448428B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001029426A JP4818519B2 (ja) 2001-02-06 2001-02-06 磁気記憶装置
JPJP-P-2001-00029426 2001-02-06

Publications (2)

Publication Number Publication Date
KR20020065323A KR20020065323A (ko) 2002-08-13
KR100448428B1 true KR100448428B1 (ko) 2004-09-13

Family

ID=18893780

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-2001-0057198A Expired - Fee Related KR100448428B1 (ko) 2001-02-06 2001-09-17 자기 기억 장치 및 자성체 기판

Country Status (6)

Country Link
US (3) US6567299B2 (enExample)
JP (1) JP4818519B2 (enExample)
KR (1) KR100448428B1 (enExample)
CN (4) CN100458968C (enExample)
DE (1) DE10164283A1 (enExample)
TW (1) TW548656B (enExample)

Families Citing this family (132)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4780878B2 (ja) * 2001-08-02 2011-09-28 ルネサスエレクトロニクス株式会社 薄膜磁性体記憶装置
JP4780874B2 (ja) * 2001-09-04 2011-09-28 ルネサスエレクトロニクス株式会社 薄膜磁性体記憶装置
JP2003124538A (ja) * 2001-10-16 2003-04-25 Sony Corp 情報記憶装置およびその情報記憶装置を実装した電子機器
KR100641667B1 (ko) * 2001-10-31 2006-11-08 인터내셔널 비지네스 머신즈 코포레이션 반도체 장치 및 그 제조 방법
US6876567B2 (en) * 2001-12-21 2005-04-05 Intel Corporation Ferroelectric memory device and method of reading a ferroelectric memory
US6781578B2 (en) * 2002-01-02 2004-08-24 Hewlett-Packard Development Company, L.P. Stylus based input devices utilizing a magnetic random access momory array
US6798404B2 (en) * 2002-01-02 2004-09-28 Hewlett-Packard Development Company, L.P. Integrated digitizing tablet and display apparatus and method of operation
JP2003272389A (ja) * 2002-03-20 2003-09-26 Sony Corp データ記憶回路及び同データ記憶回路におけるデータ書込み方法及びデータ記憶装置
DE10218785A1 (de) * 2002-04-26 2003-11-13 Infineon Technologies Ag Halbleiterspeichereinrichtung und Betriebsverfahren für eine Halbleiterspeichereinrichtung
US6801450B2 (en) * 2002-05-22 2004-10-05 Hewlett-Packard Development Company, L.P. Memory cell isolation
US6885576B2 (en) * 2002-08-13 2005-04-26 Micron Technology, Inc. Closed flux magnetic memory
JP4219134B2 (ja) * 2002-09-03 2009-02-04 株式会社ルネサステクノロジ 薄膜磁性体記憶装置
JP4063035B2 (ja) 2002-10-08 2008-03-19 ソニー株式会社 強磁性トンネル接合素子を用いた磁気記憶装置
US7002249B2 (en) * 2002-11-12 2006-02-21 Primarion, Inc. Microelectronic component with reduced parasitic inductance and method of fabricating
JP2004179483A (ja) * 2002-11-28 2004-06-24 Hitachi Ltd 不揮発性磁気メモリ
KR100506932B1 (ko) * 2002-12-10 2005-08-09 삼성전자주식회사 기준 셀들을 갖는 자기 램 소자 및 그 구조체
JP3987924B2 (ja) 2002-12-13 2007-10-10 国立大学法人大阪大学 磁性メモリアレイ、磁性メモリアレイの書き込み方法及び磁性メモリアレイの読み出し方法
JP4096302B2 (ja) * 2002-12-16 2008-06-04 ソニー株式会社 磁気メモリ装置
US7660181B2 (en) * 2002-12-19 2010-02-09 Sandisk 3D Llc Method of making non-volatile memory cell with embedded antifuse
US8008700B2 (en) * 2002-12-19 2011-08-30 Sandisk 3D Llc Non-volatile memory cell with embedded antifuse
US7800932B2 (en) * 2005-09-28 2010-09-21 Sandisk 3D Llc Memory cell comprising switchable semiconductor memory element with trimmable resistance
US6946882B2 (en) * 2002-12-20 2005-09-20 Infineon Technologies Ag Current sense amplifier
US7433253B2 (en) * 2002-12-20 2008-10-07 Qimonda Ag Integrated circuit, method of operating an integrated circuit, method of manufacturing an integrated circuit, memory module, stackable memory module
US7251178B2 (en) * 2004-09-07 2007-07-31 Infineon Technologies Ag Current sense amplifier
JP2004207364A (ja) 2002-12-24 2004-07-22 Toshiba Corp 半導体装置及びその半導体装置のデータ書き込み方法
US6818549B2 (en) * 2003-03-05 2004-11-16 Hewlett-Packard Development Company, L.P. Buried magnetic tunnel-junction memory cell and methods
JP2004363527A (ja) * 2003-04-11 2004-12-24 Toshiba Corp 磁気記憶装置、データ複写装置、データ複写システム、データ複写プログラム、及びデータ複写方法
KR100542743B1 (ko) 2003-04-22 2006-01-11 삼성전자주식회사 자기 랜덤 엑세스 메모리
US6888771B2 (en) * 2003-05-09 2005-05-03 Micron Technology, Inc. Skewed sense AMP for variable resistance memory sensing
JP4835974B2 (ja) * 2003-06-20 2011-12-14 日本電気株式会社 磁気ランダムアクセスメモリ
US6937509B2 (en) * 2003-09-08 2005-08-30 Hewlett-Packard Development Company, L.P. Data storage device and method of forming the same
JP2005108304A (ja) 2003-09-29 2005-04-21 Toshiba Corp 半導体記憶装置及びその制御方法
KR100615089B1 (ko) * 2004-07-14 2006-08-23 삼성전자주식회사 낮은 구동 전류를 갖는 자기 램
US6982902B2 (en) * 2003-10-03 2006-01-03 Infineon Technologies Ag MRAM array having a segmented bit line
US7611911B2 (en) * 2003-10-08 2009-11-03 International Business Machines Corporation Method and system for patterning of magnetic thin films using gaseous transformation to transform a magnetic portion to a non-magnetic portion
US7166881B2 (en) * 2003-10-13 2007-01-23 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-sensing level MRAM structures
JP4533701B2 (ja) * 2004-08-25 2010-09-01 株式会社東芝 磁気メモリ
US20050141148A1 (en) 2003-12-02 2005-06-30 Kabushiki Kaisha Toshiba Magnetic memory
WO2005086170A1 (ja) * 2004-03-05 2005-09-15 Nec Corporation トグル型磁気ランダムアクセスメモリ
US6946698B1 (en) 2004-04-02 2005-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. MRAM device having low-k inter-metal dielectric
JP4553620B2 (ja) * 2004-04-06 2010-09-29 ルネサスエレクトロニクス株式会社 薄膜磁性体記憶装置
US7099176B2 (en) * 2004-04-19 2006-08-29 Taiwan Semiconductor Manufacturing Company, Ltd. Non-orthogonal write line structure in MRAM
JP4415745B2 (ja) * 2004-04-22 2010-02-17 ソニー株式会社 固体メモリ装置
US7265053B2 (en) * 2004-04-26 2007-09-04 Taiwan Semiconductor Manufacturing Company, Ltd. Trench photolithography rework for removal of photoresist residue
US7532203B2 (en) * 2004-04-26 2009-05-12 Samsung Electronic Co., Ltd. Data input device that utilizes a layer of magnetic particles to store non-volatile input data that is magnetically coupled to an underlying MRAM array
JP2005317739A (ja) * 2004-04-28 2005-11-10 Toshiba Corp 磁気記憶装置およびその製造方法
US20060039183A1 (en) * 2004-05-21 2006-02-23 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-sensing level MRAM structures
US7372116B2 (en) * 2004-06-16 2008-05-13 Hitachi Global Storage Technologies Netherlands B.V. Heat assisted switching in an MRAM cell utilizing the antiferromagnetic to ferromagnetic transition in FeRh
FR2871921A1 (fr) * 2004-06-16 2005-12-23 St Microelectronics Sa Architecture de memoire a lignes d'ecriture segmentees
US7221584B2 (en) * 2004-08-13 2007-05-22 Taiwan Semiconductor Manufacturing Company, Ltd. MRAM cell having shared configuration
US7337270B2 (en) * 2004-09-10 2008-02-26 Wistron Corporation Apparatus, system, and method for servicing a data storage device using work-in-process (WIP) maps
US7355884B2 (en) 2004-10-08 2008-04-08 Kabushiki Kaisha Toshiba Magnetoresistive element
JP2006135292A (ja) * 2004-10-08 2006-05-25 Toshiba Corp 磁気抵抗効果素子
JP2006120824A (ja) * 2004-10-21 2006-05-11 Renesas Technology Corp 磁気記憶装置
RU2310928C2 (ru) * 2004-10-27 2007-11-20 Самсунг Электроникс Ко., Лтд. Усовершенствованное многоразрядное магнитное запоминающее устройство с произвольной выборкой и способы его функционирования и производства
KR100590563B1 (ko) * 2004-10-27 2006-06-19 삼성전자주식회사 멀티 비트 자기 메모리 소자와 그 동작 및 제조 방법
US7200033B2 (en) * 2004-11-30 2007-04-03 Altis Semiconductor MRAM with coil for creating offset field
JP2006156844A (ja) * 2004-11-30 2006-06-15 Toshiba Corp 半導体記憶装置
US7170775B2 (en) * 2005-01-06 2007-01-30 Taiwan Semiconductor Manufacturing Company, Ltd. MRAM cell with reduced write current
US20070263430A1 (en) * 2006-05-15 2007-11-15 Siu-Tat Chui Method for switching magnetic random access memory elements and magnetic element structures
US20130082232A1 (en) 2011-09-30 2013-04-04 Unity Semiconductor Corporation Multi Layered Conductive Metal Oxide Structures And Methods For Facilitating Enhanced Performance Characteristics Of Two Terminal Memory Cells
US7154773B2 (en) * 2005-03-31 2006-12-26 Infineon Technologies Ag MRAM cell with domain wall switching and field select
US7800934B2 (en) * 2005-09-28 2010-09-21 Sandisk 3D Llc Programming methods to increase window for reverse write 3D cell
US7606007B2 (en) * 2006-02-17 2009-10-20 Hitachi Global Storage Technologies Netherlands B.V. Shield stabilization for magnetoresistive sensors
US8147531B2 (en) * 2006-03-17 2012-04-03 Tornier, Inc. Compression pin with opposed threaded regions
JP4444257B2 (ja) 2006-09-08 2010-03-31 株式会社東芝 スピンｆｅｔ
US7728384B2 (en) 2006-05-30 2010-06-01 Macronix International Co., Ltd. Magnetic random access memory using single crystal self-aligned diode
US7719874B2 (en) * 2006-07-31 2010-05-18 Sandisk 3D Llc Systems for controlled pulse operations in non-volatile memory
WO2008016833A2 (en) * 2006-07-31 2008-02-07 Sandisk 3D Llc Increasing write voltage pulse operations in non-volatile memory
US7522448B2 (en) * 2006-07-31 2009-04-21 Sandisk 3D Llc Controlled pulse operations in non-volatile memory
US20080023790A1 (en) * 2006-07-31 2008-01-31 Scheuerlein Roy E Mixed-use memory array
US7450414B2 (en) * 2006-07-31 2008-11-11 Sandisk 3D Llc Method for using a mixed-use memory array
US20080025069A1 (en) * 2006-07-31 2008-01-31 Scheuerlein Roy E Mixed-use memory array with different data states
US7486537B2 (en) * 2006-07-31 2009-02-03 Sandisk 3D Llc Method for using a mixed-use memory array with different data states
US7652915B2 (en) * 2006-12-19 2010-01-26 Hitachi Global Storage Technologies Netherlands B.V. High density spin torque three dimensional (3D) memory arrays addressed with microwave current
JP2008211058A (ja) 2007-02-27 2008-09-11 Toshiba Corp 磁気ランダムアクセスメモリ及びその書き込み方法
US7447061B1 (en) * 2007-03-02 2008-11-04 The United States Of America As Represented By The Secretary Of The Navy Magnetoresistive memory array circuit
US7508700B2 (en) * 2007-03-15 2009-03-24 Magic Technologies, Inc. Method of magnetic tunneling junction pattern layout for magnetic random access memory
JP5072967B2 (ja) * 2007-07-18 2012-11-14 パナソニック株式会社 電流制限素子とそれを用いたメモリ装置およびその製造方法
US7995371B2 (en) * 2007-07-26 2011-08-09 Unity Semiconductor Corporation Threshold device for a memory array
US7768812B2 (en) 2008-01-15 2010-08-03 Micron Technology, Inc. Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices
JPWO2009110119A1 (ja) * 2008-03-06 2011-07-14 富士電機ホールディングス株式会社 強磁性トンネル接合素子および強磁性トンネル接合素子の駆動方法
US8034655B2 (en) 2008-04-08 2011-10-11 Micron Technology, Inc. Non-volatile resistive oxide memory cells, non-volatile resistive oxide memory arrays, and methods of forming non-volatile resistive oxide memory cells and memory arrays
US8211743B2 (en) 2008-05-02 2012-07-03 Micron Technology, Inc. Methods of forming non-volatile memory cells having multi-resistive state material between conductive electrodes
US7738279B2 (en) 2008-06-02 2010-06-15 Qimonda Ag Integrated circuit and method of operating an integrated circuit
DE102008026432A1 (de) * 2008-06-02 2009-12-10 Qimonda Ag Integrierte Schaltung, Speichermodul sowie Verfahren zum Betreiben einer integrierten Schaltung
US8134137B2 (en) 2008-06-18 2012-03-13 Micron Technology, Inc. Memory device constructions, memory cell forming methods, and semiconductor construction forming methods
US9343665B2 (en) 2008-07-02 2016-05-17 Micron Technology, Inc. Methods of forming a non-volatile resistive oxide memory cell and methods of forming a non-volatile resistive oxide memory array
KR101539402B1 (ko) * 2008-10-23 2015-07-27 삼성전자주식회사 반도체 패키지
KR101019893B1 (ko) * 2008-12-23 2011-03-04 주식회사 하이닉스반도체 플로팅 바디 효과를 이용한 자기저항 메모리셀, 이를 포함하는 메모리 소자 및 그 동작 방법
JP5526707B2 (ja) * 2009-10-27 2014-06-18 ソニー株式会社 情報記憶素子の駆動方法
US8427859B2 (en) * 2010-04-22 2013-04-23 Micron Technology, Inc. Arrays of vertically stacked tiers of non-volatile cross point memory cells, methods of forming arrays of vertically stacked tiers of non-volatile cross point memory cells, and methods of reading a data value stored by an array of vertically stacked tiers of non-volatile cross point memory cells
US8411477B2 (en) 2010-04-22 2013-04-02 Micron Technology, Inc. Arrays of vertically stacked tiers of non-volatile cross point memory cells, methods of forming arrays of vertically stacked tiers of non-volatile cross point memory cells, and methods of reading a data value stored by an array of vertically stacked tiers of non-volatile cross point memory cells
JP2010186559A (ja) * 2010-06-04 2010-08-26 Renesas Electronics Corp 薄膜磁性体記憶装置
US8289763B2 (en) 2010-06-07 2012-10-16 Micron Technology, Inc. Memory arrays
JP5521850B2 (ja) * 2010-07-21 2014-06-18 ソニー株式会社 抵抗変化型メモリデバイスおよびその駆動方法
KR101194939B1 (ko) * 2010-08-30 2012-10-25 에스케이하이닉스 주식회사 비휘발성 메모리 장치
US8351242B2 (en) 2010-09-29 2013-01-08 Micron Technology, Inc. Electronic devices, memory devices and memory arrays
US8759809B2 (en) 2010-10-21 2014-06-24 Micron Technology, Inc. Integrated circuitry comprising nonvolatile memory cells having platelike electrode and ion conductive material layer
US8526213B2 (en) 2010-11-01 2013-09-03 Micron Technology, Inc. Memory cells, methods of programming memory cells, and methods of forming memory cells
US8796661B2 (en) 2010-11-01 2014-08-05 Micron Technology, Inc. Nonvolatile memory cells and methods of forming nonvolatile memory cell
US8415775B2 (en) 2010-11-23 2013-04-09 Honeywell International Inc. Magnetic shielding for multi-chip module packaging
US9454997B2 (en) 2010-12-02 2016-09-27 Micron Technology, Inc. Array of nonvolatile memory cells having at least five memory cells per unit cell, having a plurality of the unit cells which individually comprise three elevational regions of programmable material, and/or having a continuous volume having a combination of a plurality of vertically oriented memory cells and a plurality of horizontally oriented memory cells; array of vertically stacked tiers of nonvolatile memory cells
US8431458B2 (en) 2010-12-27 2013-04-30 Micron Technology, Inc. Methods of forming a nonvolatile memory cell and methods of forming an array of nonvolatile memory cells
US8791447B2 (en) 2011-01-20 2014-07-29 Micron Technology, Inc. Arrays of nonvolatile memory cells and methods of forming arrays of nonvolatile memory cells
CN102610749B (zh) * 2011-01-25 2014-01-29 中国科学院微电子研究所 阻变型随机存储单元及存储器
US8488365B2 (en) 2011-02-24 2013-07-16 Micron Technology, Inc. Memory cells
US8537592B2 (en) 2011-04-15 2013-09-17 Micron Technology, Inc. Arrays of nonvolatile memory cells and methods of forming arrays of nonvolatile memory cells
US8816455B2 (en) 2012-10-22 2014-08-26 Crocus Technology Inc. Memory devices with magnetic random access memory (MRAM) cells and associated structures for connecting the MRAM cells
JP6010005B2 (ja) 2013-09-09 2016-10-19 株式会社東芝 半導体装置及びその製造方法
JP6074345B2 (ja) * 2013-09-24 2017-02-01 株式会社東芝 半導体装置及びその製造方法
KR102189684B1 (ko) 2013-12-05 2020-12-11 삼성전자주식회사 반도체 메모리 장치의 동작 방법
KR102173431B1 (ko) 2014-05-02 2020-11-03 삼성전자주식회사 동작 전류가 감소된 메모리 장치
KR20160122885A (ko) * 2015-04-14 2016-10-25 에스케이하이닉스 주식회사 전자장치
CN107534018B (zh) * 2015-04-27 2020-06-16 东芝存储器株式会社 磁性存储器装置
KR102354370B1 (ko) 2015-04-29 2022-01-21 삼성전자주식회사 쉴딩 구조물을 포함하는 자기 저항 칩 패키지
CN106328370A (zh) * 2015-06-30 2017-01-11 贵州雅光电子科技股份有限公司 各向异性磁阻坡膜合金及其固定易磁化轴的制备方法
US9397139B1 (en) * 2015-09-23 2016-07-19 Globalfoundries Singapore Pte. Ltd. Integrated inductor and magnetic random access memory device
WO2017221896A1 (ja) * 2016-06-20 2017-12-28 国立大学法人東北大学 トンネル磁気抵抗素子及びその製造方法
US12262644B2 (en) 2016-07-29 2025-03-25 Tdk Corporation Spin current magnetization reversal element, element assembly, and method for producing spin current magnetization reversal element
US10418545B2 (en) 2016-07-29 2019-09-17 Tdk Corporation Spin current magnetization reversal element, element assembly, and method for producing spin current magnetization reversal element
US11276815B2 (en) 2016-10-27 2022-03-15 Tdk Corporation Spin-orbit torque type magnetization reversal element, magnetic memory, and high frequency magnetic device
US10319901B2 (en) 2016-10-27 2019-06-11 Tdk Corporation Spin-orbit torque type magnetization reversal element, magnetic memory, and high frequency magnetic device
US10439130B2 (en) 2016-10-27 2019-10-08 Tdk Corporation Spin-orbit torque type magnetoresistance effect element, and method for producing spin-orbit torque type magnetoresistance effect element
US9997239B1 (en) * 2017-05-02 2018-06-12 Everspin Technologies, Inc. Word line overdrive in memory and method therefor
CN112913341B (zh) 2018-10-25 2023-09-05 株式会社村田制作所 电子部件模块以及电子部件模块的制造方法
JP7258332B2 (ja) * 2018-11-21 2023-04-17 国立研究開発法人産業技術総合研究所 スピントルク発振素子
CN112652337B (zh) * 2019-10-10 2024-03-12 上海磁宇信息科技有限公司 存储器的行译码器
KR102432163B1 (ko) * 2020-10-30 2022-08-12 한양대학교 산학협력단 고신뢰성의 자기 메모리 시스템 및 그 동작 방법
US20230165155A1 (en) * 2021-11-19 2023-05-25 International Business Machines Corporation Inverted wide base double magnetic tunnel junction device
US20230207552A1 (en) * 2021-12-24 2023-06-29 Intel Corporation Transition cells between design blocks on a wafer
US12148459B2 (en) 2022-02-22 2024-11-19 Sandisk Technologies Llc Cross-point array IHOLD read margin improvement

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58211393A (ja) * 1982-06-02 1983-12-08 Mitsubishi Electric Corp 半導体メモリ装置
JPS6344398A (ja) 1986-08-08 1988-02-25 Fujitsu Ltd 磁気バブルメモリ装置
JPH01171194A (ja) * 1987-12-25 1989-07-06 Nec Ic Microcomput Syst Ltd 半導体記憶装置
JPH03235290A (ja) 1990-02-09 1991-10-21 Mitsubishi Electric Corp 階層的な行選択線を有する半導体記憶装置
JPH0595055A (ja) 1991-10-01 1993-04-16 Seiko Epson Corp 半導体集積回路
JP3364549B2 (ja) * 1995-02-22 2003-01-08 三菱電機株式会社 半導体記憶装置
US5640343A (en) 1996-03-18 1997-06-17 International Business Machines Corporation Magnetic memory array using magnetic tunnel junction devices in the memory cells
JP3392657B2 (ja) * 1996-09-26 2003-03-31 株式会社東芝 半導体記憶装置
JP4059951B2 (ja) * 1997-04-11 2008-03-12 株式会社ルネサステクノロジ 半導体記憶装置
US5852574A (en) * 1997-12-24 1998-12-22 Motorola, Inc. High density magnetoresistive random access memory device and operating method thereof
US5946228A (en) 1998-02-10 1999-08-31 International Business Machines Corporation Limiting magnetic writing fields to a preferred portion of a changeable magnetic region in magnetic devices
JPH11289186A (ja) 1998-04-02 1999-10-19 Canon Inc 半導体のノイズ低減装置及び半導体のノイズ低減方法
US6097625A (en) * 1998-07-16 2000-08-01 International Business Machines Corporation Magnetic random access memory (MRAM) array with magnetic tunnel junction (MTJ) cells and remote diodes
US5982660A (en) 1998-08-27 1999-11-09 Hewlett-Packard Company Magnetic memory cell with off-axis reference layer orientation for improved response
US6609174B1 (en) 1999-10-19 2003-08-19 Motorola, Inc. Embedded MRAMs including dual read ports
US6473336B2 (en) * 1999-12-16 2002-10-29 Kabushiki Kaisha Toshiba Magnetic memory device
US6335890B1 (en) * 2000-11-01 2002-01-01 International Business Machines Corporation Segmented write line architecture for writing magnetic random access memories
JP3812805B2 (ja) * 2001-01-16 2006-08-23 日本電気株式会社 トンネル磁気抵抗素子を利用した半導体記憶装置
US6445612B1 (en) * 2001-08-27 2002-09-03 Motorola, Inc. MRAM with midpoint generator reference and method for readout

Also Published As

Publication number Publication date
JP4818519B2 (ja) 2011-11-16
CN100458968C (zh) 2009-02-04
US20030210591A1 (en) 2003-11-13
US6741495B2 (en) 2004-05-25
US20040174756A1 (en) 2004-09-09
DE10164283A1 (de) 2002-08-29
US6567299B2 (en) 2003-05-20
CN1368735A (zh) 2002-09-11
KR20020065323A (ko) 2002-08-13
CN1577618A (zh) 2005-02-09
US6950369B2 (en) 2005-09-27
US20020145902A1 (en) 2002-10-10
CN1577619A (zh) 2005-02-09
TW548656B (en) 2003-08-21
CN1577617A (zh) 2005-02-09
JP2002231904A (ja) 2002-08-16
CN1193374C (zh) 2005-03-16

Similar Documents

Publication Publication Date Title
KR100448428B1 (ko) 자기 기억 장치 및 자성체 기판
US10923650B2 (en) Magneto-resistive chip package including shielding structure
US6163477A (en) MRAM device using magnetic field bias to improve reproducibility of memory cell switching
JP4646485B2 (ja) 薄膜磁性体記憶装置
JP4096302B2 (ja) 磁気メモリ装置
US6498747B1 (en) Magnetoresistive random access memory (MRAM) cross-point array with reduced parasitic effects
US7227774B2 (en) MRAM integrated circuits, MRAM circuits, and systems for testing MRAM integrated circuits
KR20050096838A (ko) 자기 메모리장치
JP2003115578A (ja) 不揮発固体磁気メモリ装置、該不揮発固体磁気メモリ装置の製造方法およびマルチ・チップ・パッケージ
US6980464B2 (en) Magnetic random access memory
JP2005158985A (ja) 磁気メモリ装置の実装構造及び実装基板
US6842361B2 (en) Memory cell, memory circuit block, data writing method and data reading method
JP2010093277A (ja) 半導体集積回路装置
EP1692704B1 (en) Method and device for performing active field compensation during programming of a magnetoresistive memory device
JP2004193247A (ja) 磁気メモリ装置
JPWO2004088754A1 (ja) メモリセルとこれを用いたメモリおよびメモリセルの製造方法ならびにメモリの記録／読出方法
CN1525486B (zh) 抑制电源配线的磁场噪声影响的薄膜磁性体存储装置
JP2002170375A (ja) 強磁性体不揮発性記憶素子ならびにその情報再生方法
JP2013088886A (ja) 半導体集積回路およびその動作方法

Legal Events

Date Code Title Description
A201 Request for examination
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

R17-X000 Change to representative recorded

St.27 status event code: A-5-5-R10-R17-oth-X000

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 8

FPAY Annual fee payment

Payment date: 20120821

Year of fee payment: 9

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 9

FPAY Annual fee payment

Payment date: 20130822

Year of fee payment: 10

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 10

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20140903

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20140903