KR100282974B1 - 테스트 모드를 확실하게 리세트하는 것이 가능한 회로를 구비하는 동기형 반도체 장치 - Google Patents

테스트 모드를 확실하게 리세트하는 것이 가능한 회로를 구비하는 동기형 반도체 장치 Download PDF

Info

Publication number
KR100282974B1
KR100282974B1 KR1019980028029A KR19980028029A KR100282974B1 KR 100282974 B1 KR100282974 B1 KR 100282974B1 KR 1019980028029 A KR1019980028029 A KR 1019980028029A KR 19980028029 A KR19980028029 A KR 19980028029A KR 100282974 B1 KR100282974 B1 KR 100282974B1
Authority
KR
South Korea
Prior art keywords
signal
test mode
command
circuit
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1019980028029A
Other languages
English (en)
Korean (ko)
Other versions
KR19990044766A (ko
Inventor
미키오 사쿠라이
스스무 다니다
야스히코 츠키카와
마사야 나카노
다카히코 후키아게
Original Assignee
다니구찌 이찌로오, 기타오카 다카시
미쓰비시덴키 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 다니구찌 이찌로오, 기타오카 다카시, 미쓰비시덴키 가부시키가이샤 filed Critical 다니구찌 이찌로오, 기타오카 다카시
Publication of KR19990044766A publication Critical patent/KR19990044766A/ko
Application granted granted Critical
Publication of KR100282974B1 publication Critical patent/KR100282974B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31701—Arrangements for setting the Unit Under Test [UUT] in a test mode

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
KR1019980028029A 1997-11-14 1998-07-11 테스트 모드를 확실하게 리세트하는 것이 가능한 회로를 구비하는 동기형 반도체 장치 Expired - Fee Related KR100282974B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP31373997A JP4141520B2 (ja) 1997-11-14 1997-11-14 同期型半導体記憶装置
JP97-313739 1997-11-14

Publications (2)

Publication Number Publication Date
KR19990044766A KR19990044766A (ko) 1999-06-25
KR100282974B1 true KR100282974B1 (ko) 2001-03-02

Family

ID=18044953

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019980028029A Expired - Fee Related KR100282974B1 (ko) 1997-11-14 1998-07-11 테스트 모드를 확실하게 리세트하는 것이 가능한 회로를 구비하는 동기형 반도체 장치

Country Status (5)

Country Link
US (1) US5905690A (enExample)
JP (1) JP4141520B2 (enExample)
KR (1) KR100282974B1 (enExample)
CN (1) CN1107958C (enExample)
TW (1) TW392167B (enExample)

Families Citing this family (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100267781B1 (ko) * 1998-03-04 2000-10-16 김영환 테스트 모드를 셋업하기 위한 반도체 소자
JP3169071B2 (ja) * 1998-04-27 2001-05-21 日本電気株式会社 同期型半導体記憶装置
US6253340B1 (en) * 1998-06-08 2001-06-26 Micron Technology, Inc. Integrated circuit implementing internally generated commands
TW463174B (en) 1999-02-16 2001-11-11 Fujitsu Ltd Semiconductor device having test mode entry circuit
JP2001126498A (ja) * 1999-10-29 2001-05-11 Mitsubishi Electric Corp 半導体記憶装置
KR20020006556A (ko) * 2000-07-03 2002-01-23 윤종용 반도체 메모리 장치의 모드 선택 회로
US6735640B1 (en) * 2000-08-16 2004-05-11 Kabushiki Kaisha Toshiba Computer system and method for operating a computer unit and a peripheral unit
KR100652362B1 (ko) 2000-09-20 2006-11-30 삼성전자주식회사 정상동작에서는 고정된 카스 레이턴시를 갖고테스트시에는 다양한 카스 레이턴시로 테스트 가능한반도체 메모리 장치
DE10110627A1 (de) * 2001-03-06 2002-09-19 Infineon Technologies Ag Verfahren und Schaltungsanordnung zum Steuern von Testfunktionen in einem Speicherbaustein
JP4794059B2 (ja) * 2001-03-09 2011-10-12 富士通セミコンダクター株式会社 半導体装置
JP4707255B2 (ja) * 2001-04-26 2011-06-22 ルネサスエレクトロニクス株式会社 半導体記憶装置
KR100401506B1 (ko) 2001-05-10 2003-10-17 주식회사 하이닉스반도체 비동기 프리차지 기능을 갖는 싱크로노스 메모리 디바이스
JP2002343099A (ja) * 2001-05-14 2002-11-29 Toshiba Corp 半導体記憶装置
US6693837B2 (en) * 2002-04-23 2004-02-17 Micron Technology, Inc. System and method for quick self-refresh exit with transitional refresh
JP2004087040A (ja) * 2002-08-28 2004-03-18 Renesas Technology Corp 半導体装置とそのテスト方法
KR100434513B1 (ko) * 2002-09-11 2004-06-05 삼성전자주식회사 클럭 인에이블 신호를 이용한 데이터 경로의 리셋 회로,리셋 방법 및 이를 구비하는 반도체 메모리 장치
TWM241942U (en) * 2003-01-24 2004-08-21 Delta Electronics Inc A casing structure for an electronic apparatus
JP2004272638A (ja) * 2003-03-10 2004-09-30 Renesas Technology Corp マイクロコンピュータ
US7155644B2 (en) * 2003-05-08 2006-12-26 Micron Technology, Inc. Automatic test entry termination in a memory device
KR100557948B1 (ko) 2003-06-20 2006-03-10 주식회사 하이닉스반도체 메모리 장치의 테스트 방법
JP4213605B2 (ja) * 2004-02-26 2009-01-21 東芝エルエスアイシステムサポート株式会社 動作モード設定回路
US7332928B2 (en) * 2004-03-05 2008-02-19 Finisar Corporation Use of a third state applied to a digital input terminal of a circuit to initiate non-standard operational modes of the circuit
KR100625293B1 (ko) * 2004-06-30 2006-09-20 주식회사 하이닉스반도체 높은 신뢰성을 갖는 반도체메모리소자 및 그를 위한구동방법
DE102004051345B9 (de) * 2004-10-21 2014-01-02 Qimonda Ag Halbleiter-Bauelement, Verfahren zum Ein- und/oder Ausgeben von Testdaten, sowie Speichermodul
JP4620504B2 (ja) 2005-03-10 2011-01-26 富士通セミコンダクター株式会社 半導体メモリおよびシステム装置
KR100724626B1 (ko) * 2005-08-29 2007-06-04 주식회사 하이닉스반도체 테스트 모드 제어 회로
JP4669518B2 (ja) * 2005-09-21 2011-04-13 ルネサスエレクトロニクス株式会社 半導体装置
US7586350B2 (en) 2005-09-28 2009-09-08 Hynix Semiconductor Inc. Circuit and method for initializing an internal logic unit in a semiconductor memory device
JP2007200504A (ja) 2006-01-30 2007-08-09 Fujitsu Ltd 半導体メモリ、メモリコントローラ及び半導体メモリの制御方法
KR100695435B1 (ko) 2006-04-13 2007-03-16 주식회사 하이닉스반도체 반도체 메모리 소자
KR100723889B1 (ko) 2006-06-30 2007-05-31 주식회사 하이닉스반도체 직렬 입/출력 인터페이스를 가진 멀티 포트 메모리 소자
KR100924579B1 (ko) * 2007-06-21 2009-11-02 삼성전자주식회사 리던던시 메모리 셀 억세스 회로, 이를 포함하는 반도체메모리 장치, 및 반도체 메모리 장치의 테스트 방법
JP2009087526A (ja) * 2007-09-28 2009-04-23 Hynix Semiconductor Inc 半導体メモリ装置およびその駆動方法
KR100942940B1 (ko) * 2007-09-28 2010-02-22 주식회사 하이닉스반도체 반도체 메모리 장치 및 그 구동방법
US7626884B2 (en) * 2007-10-30 2009-12-01 Intel Corporation Optimizing mode register set commands
JP5096131B2 (ja) * 2007-12-27 2012-12-12 ルネサスエレクトロニクス株式会社 半導体記憶装置
KR100951666B1 (ko) * 2008-08-08 2010-04-07 주식회사 하이닉스반도체 테스트 모드를 제어하는 반도체 집적 회로
KR101187642B1 (ko) * 2011-05-02 2012-10-08 에스케이하이닉스 주식회사 집적 회로의 모니터링 장치
KR101903520B1 (ko) * 2012-01-06 2018-10-04 에스케이하이닉스 주식회사 반도체 장치
US8830780B2 (en) * 2013-01-15 2014-09-09 Qualcomm Incorporated System and method of performing power on reset for memory array circuits
US9891277B2 (en) * 2014-09-30 2018-02-13 Nxp Usa, Inc. Secure low voltage testing
KR20160123843A (ko) * 2015-04-17 2016-10-26 에스케이하이닉스 주식회사 반도체 장치
KR102375054B1 (ko) * 2015-12-11 2022-03-17 에스케이하이닉스 주식회사 테스트 모드 설정회로 및 이를 포함하는 반도체 장치
JP2022044114A (ja) * 2020-09-07 2022-03-17 キオクシア株式会社 半導体集積回路およびその試験方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3421760B2 (ja) * 1994-10-11 2003-06-30 三菱電機株式会社 Ｓｄｒａｍのパワーオンリセット信号発生回路
US5572470A (en) * 1995-05-10 1996-11-05 Sgs-Thomson Microelectronics, Inc. Apparatus and method for mapping a redundant memory column to a defective memory column

Also Published As

Publication number Publication date
CN1217545A (zh) 1999-05-26
KR19990044766A (ko) 1999-06-25
US5905690A (en) 1999-05-18
JPH11149771A (ja) 1999-06-02
TW392167B (en) 2000-06-01
JP4141520B2 (ja) 2008-08-27
CN1107958C (zh) 2003-05-07

Similar Documents

Publication Publication Date Title
KR100282974B1 (ko) 테스트 모드를 확실하게 리세트하는 것이 가능한 회로를 구비하는 동기형 반도체 장치
KR100408615B1 (ko) 스탠바이시에 소비 전류를 삭감 가능한 반도체 장치
JP3535788B2 (ja) 半導体記憶装置
US6442095B1 (en) Semiconductor memory device with normal mode and power down mode
US8089817B2 (en) Precise tRCD measurement in a semiconductor memory device
KR100315347B1 (ko) 반도체 메모리 장치의 동작모드 세팅회로 및 방법
US7466623B2 (en) Pseudo SRAM capable of operating in continuous burst mode and method of controlling burst mode operation thereof
US7251171B2 (en) Semiconductor memory and system apparatus
JP2003346497A (ja) 半導体記憶装置
US6707735B2 (en) Semiconductor memory device
KR100301645B1 (ko) 테스트모드에있어서워드선을임의로또한고속으로선택상태로하는선택회로를갖는반도체기억장치
US8274854B2 (en) Semiconductor storage device and method for producing semiconductor storage device
US7349266B2 (en) Memory device with a data hold latch
KR100368105B1 (ko) 반도체메모리장치
US20030086320A1 (en) Semiconductor device having integrated memory and logic
US6651022B2 (en) Semiconductor device capable of test mode operation
JP2001243797A (ja) 半導体装置及びその試験方法
KR100337206B1 (ko) 모드 레지스터 세팅장치
JP3948592B2 (ja) 半導体装置
JP2004281002A (ja) 半導体記憶装置
KR100303994B1 (ko) 이디오 디램의 스페셜 테스트 모드 진입 회로
JP2000030442A (ja) 同期型半導体記憶装置
KR100924017B1 (ko) 오토 프리차지 회로 및 오토 프리차지 방법
JP2007018710A (ja) 半導体装置及びその試験方法
JP2001036009A (ja) 半導体装置

Legal Events

Date Code Title Description
A201 Request for examination
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

PN2301 Change of applicant

St.27 status event code: A-3-3-R10-R13-asn-PN2301

St.27 status event code: A-3-3-R10-R11-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-3-3-R10-R13-asn-PN2301

St.27 status event code: A-3-3-R10-R11-asn-PN2301

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

PN2301 Change of applicant

St.27 status event code: A-3-3-R10-R13-asn-PN2301

St.27 status event code: A-3-3-R10-R11-asn-PN2301

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 8

FPAY Annual fee payment

Payment date: 20081126

Year of fee payment: 9

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 9

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20091205

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20091205

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000