TW392167B - Synchronous semiconductor storage device - Google Patents
Synchronous semiconductor storage device Download PDFInfo
- Publication number
- TW392167B TW392167B TW087107783A TW87107783A TW392167B TW 392167 B TW392167 B TW 392167B TW 087107783 A TW087107783 A TW 087107783A TW 87107783 A TW87107783 A TW 87107783A TW 392167 B TW392167 B TW 392167B
- Authority
- TW
- Taiwan
- Prior art keywords
- signal
- test
- test mode
- command
- modal
- Prior art date
Links
- 230000001360 synchronised effect Effects 0.000 title claims abstract description 111
- 239000004065 semiconductor Substances 0.000 title claims abstract description 99
- 238000003860 storage Methods 0.000 title abstract description 6
- 238000012360 testing method Methods 0.000 claims abstract description 426
- 230000004044 response Effects 0.000 claims abstract description 25
- 230000000875 corresponding effect Effects 0.000 claims description 64
- 230000004913 activation Effects 0.000 claims description 60
- 230000007246 mechanism Effects 0.000 claims description 52
- 230000015654 memory Effects 0.000 claims description 48
- 230000036316 preload Effects 0.000 claims description 46
- 238000001514 detection method Methods 0.000 claims description 35
- 230000002079 cooperative effect Effects 0.000 claims description 15
- 230000009471 action Effects 0.000 claims description 12
- 235000015170 shellfish Nutrition 0.000 claims description 10
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 239000003638 chemical reducing agent Substances 0.000 claims description 3
- PCTMTFRHKVHKIS-BMFZQQSSSA-N (1s,3r,4e,6e,8e,10e,12e,14e,16e,18s,19r,20r,21s,25r,27r,30r,31r,33s,35r,37s,38r)-3-[(2r,3s,4s,5s,6r)-4-amino-3,5-dihydroxy-6-methyloxan-2-yl]oxy-19,25,27,30,31,33,35,37-octahydroxy-18,20,21-trimethyl-23-oxo-22,39-dioxabicyclo[33.3.1]nonatriaconta-4,6,8,10 Chemical compound C1C=C2C[C@@H](OS(O)(=O)=O)CC[C@]2(C)[C@@H]2[C@@H]1[C@@H]1CC[C@H]([C@H](C)CCCC(C)C)[C@@]1(C)CC2.O[C@H]1[C@@H](N)[C@H](O)[C@@H](C)O[C@H]1O[C@H]1/C=C/C=C/C=C/C=C/C=C/C=C/C=C/[C@H](C)[C@@H](O)[C@@H](C)[C@H](C)OC(=O)C[C@H](O)C[C@H](O)CC[C@@H](O)[C@H](O)C[C@H](O)C[C@](O)(C[C@H](O)[C@H]2C(O)=O)O[C@H]2C1 PCTMTFRHKVHKIS-BMFZQQSSSA-N 0.000 claims 1
- 101000905241 Mus musculus Heart- and neural crest derivatives-expressed protein 1 Proteins 0.000 claims 1
- 230000000937 inactivator Effects 0.000 claims 1
- 238000005259 measurement Methods 0.000 claims 1
- 230000008520 organization Effects 0.000 claims 1
- 239000000126 substance Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 28
- 102100034033 Alpha-adducin Human genes 0.000 description 13
- 101000799076 Homo sapiens Alpha-adducin Proteins 0.000 description 13
- 101000629598 Rattus norvegicus Sterol regulatory element-binding protein 1 Proteins 0.000 description 13
- 238000000034 method Methods 0.000 description 8
- 230000002441 reversible effect Effects 0.000 description 5
- 239000007858 starting material Substances 0.000 description 5
- 238000009434 installation Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- VZSRBBMJRBPUNF-UHFFFAOYSA-N 2-(2,3-dihydro-1H-inden-2-ylamino)-N-[3-oxo-3-(2,4,6,7-tetrahydrotriazolo[4,5-c]pyridin-5-yl)propyl]pyrimidine-5-carboxamide Chemical compound C1C(CC2=CC=CC=C12)NC1=NC=C(C=N1)C(=O)NCCC(N1CC2=C(CC1)NN=N2)=O VZSRBBMJRBPUNF-UHFFFAOYSA-N 0.000 description 1
- 241000723353 Chrysanthemum Species 0.000 description 1
- 235000007516 Chrysanthemum Nutrition 0.000 description 1
- 101100256746 Mus musculus Setdb1 gene Proteins 0.000 description 1
- 241000219492 Quercus Species 0.000 description 1
- 101710194411 Triosephosphate isomerase 1 Proteins 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 238000013075 data extraction Methods 0.000 description 1
- 230000009849 deactivation Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003623 enhancer Substances 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 238000012353 t test Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 230000003442 weekly effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31701—Arrangements for setting the Unit Under Test [UUT] in a test mode
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31373997A JP4141520B2 (ja) | 1997-11-14 | 1997-11-14 | 同期型半導体記憶装置 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW392167B true TW392167B (en) | 2000-06-01 |
Family
ID=18044953
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW087107783A TW392167B (en) | 1997-11-14 | 1998-05-20 | Synchronous semiconductor storage device |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US5905690A (enExample) |
| JP (1) | JP4141520B2 (enExample) |
| KR (1) | KR100282974B1 (enExample) |
| CN (1) | CN1107958C (enExample) |
| TW (1) | TW392167B (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8031552B2 (en) | 2006-06-30 | 2011-10-04 | Hynix Semiconductor Inc. | Multi-port memory device with serial input/output interface |
Families Citing this family (43)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100267781B1 (ko) * | 1998-03-04 | 2000-10-16 | 김영환 | 테스트 모드를 셋업하기 위한 반도체 소자 |
| JP3169071B2 (ja) * | 1998-04-27 | 2001-05-21 | 日本電気株式会社 | 同期型半導体記憶装置 |
| US6253340B1 (en) * | 1998-06-08 | 2001-06-26 | Micron Technology, Inc. | Integrated circuit implementing internally generated commands |
| TW463174B (en) | 1999-02-16 | 2001-11-11 | Fujitsu Ltd | Semiconductor device having test mode entry circuit |
| JP2001126498A (ja) * | 1999-10-29 | 2001-05-11 | Mitsubishi Electric Corp | 半導体記憶装置 |
| KR20020006556A (ko) * | 2000-07-03 | 2002-01-23 | 윤종용 | 반도체 메모리 장치의 모드 선택 회로 |
| US6735640B1 (en) * | 2000-08-16 | 2004-05-11 | Kabushiki Kaisha Toshiba | Computer system and method for operating a computer unit and a peripheral unit |
| KR100652362B1 (ko) | 2000-09-20 | 2006-11-30 | 삼성전자주식회사 | 정상동작에서는 고정된 카스 레이턴시를 갖고테스트시에는 다양한 카스 레이턴시로 테스트 가능한반도체 메모리 장치 |
| DE10110627A1 (de) * | 2001-03-06 | 2002-09-19 | Infineon Technologies Ag | Verfahren und Schaltungsanordnung zum Steuern von Testfunktionen in einem Speicherbaustein |
| JP4794059B2 (ja) * | 2001-03-09 | 2011-10-12 | 富士通セミコンダクター株式会社 | 半導体装置 |
| JP4707255B2 (ja) * | 2001-04-26 | 2011-06-22 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置 |
| KR100401506B1 (ko) | 2001-05-10 | 2003-10-17 | 주식회사 하이닉스반도체 | 비동기 프리차지 기능을 갖는 싱크로노스 메모리 디바이스 |
| JP2002343099A (ja) * | 2001-05-14 | 2002-11-29 | Toshiba Corp | 半導体記憶装置 |
| US6693837B2 (en) * | 2002-04-23 | 2004-02-17 | Micron Technology, Inc. | System and method for quick self-refresh exit with transitional refresh |
| JP2004087040A (ja) * | 2002-08-28 | 2004-03-18 | Renesas Technology Corp | 半導体装置とそのテスト方法 |
| KR100434513B1 (ko) * | 2002-09-11 | 2004-06-05 | 삼성전자주식회사 | 클럭 인에이블 신호를 이용한 데이터 경로의 리셋 회로,리셋 방법 및 이를 구비하는 반도체 메모리 장치 |
| TWM241942U (en) * | 2003-01-24 | 2004-08-21 | Delta Electronics Inc | A casing structure for an electronic apparatus |
| JP2004272638A (ja) * | 2003-03-10 | 2004-09-30 | Renesas Technology Corp | マイクロコンピュータ |
| US7155644B2 (en) * | 2003-05-08 | 2006-12-26 | Micron Technology, Inc. | Automatic test entry termination in a memory device |
| KR100557948B1 (ko) | 2003-06-20 | 2006-03-10 | 주식회사 하이닉스반도체 | 메모리 장치의 테스트 방법 |
| JP4213605B2 (ja) * | 2004-02-26 | 2009-01-21 | 東芝エルエスアイシステムサポート株式会社 | 動作モード設定回路 |
| US7332928B2 (en) * | 2004-03-05 | 2008-02-19 | Finisar Corporation | Use of a third state applied to a digital input terminal of a circuit to initiate non-standard operational modes of the circuit |
| KR100625293B1 (ko) * | 2004-06-30 | 2006-09-20 | 주식회사 하이닉스반도체 | 높은 신뢰성을 갖는 반도체메모리소자 및 그를 위한구동방법 |
| DE102004051345B9 (de) * | 2004-10-21 | 2014-01-02 | Qimonda Ag | Halbleiter-Bauelement, Verfahren zum Ein- und/oder Ausgeben von Testdaten, sowie Speichermodul |
| JP4620504B2 (ja) | 2005-03-10 | 2011-01-26 | 富士通セミコンダクター株式会社 | 半導体メモリおよびシステム装置 |
| KR100724626B1 (ko) * | 2005-08-29 | 2007-06-04 | 주식회사 하이닉스반도체 | 테스트 모드 제어 회로 |
| JP4669518B2 (ja) * | 2005-09-21 | 2011-04-13 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| US7586350B2 (en) | 2005-09-28 | 2009-09-08 | Hynix Semiconductor Inc. | Circuit and method for initializing an internal logic unit in a semiconductor memory device |
| JP2007200504A (ja) | 2006-01-30 | 2007-08-09 | Fujitsu Ltd | 半導体メモリ、メモリコントローラ及び半導体メモリの制御方法 |
| KR100695435B1 (ko) | 2006-04-13 | 2007-03-16 | 주식회사 하이닉스반도체 | 반도체 메모리 소자 |
| KR100924579B1 (ko) * | 2007-06-21 | 2009-11-02 | 삼성전자주식회사 | 리던던시 메모리 셀 억세스 회로, 이를 포함하는 반도체메모리 장치, 및 반도체 메모리 장치의 테스트 방법 |
| JP2009087526A (ja) * | 2007-09-28 | 2009-04-23 | Hynix Semiconductor Inc | 半導体メモリ装置およびその駆動方法 |
| KR100942940B1 (ko) * | 2007-09-28 | 2010-02-22 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 및 그 구동방법 |
| US7626884B2 (en) * | 2007-10-30 | 2009-12-01 | Intel Corporation | Optimizing mode register set commands |
| JP5096131B2 (ja) * | 2007-12-27 | 2012-12-12 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置 |
| KR100951666B1 (ko) * | 2008-08-08 | 2010-04-07 | 주식회사 하이닉스반도체 | 테스트 모드를 제어하는 반도체 집적 회로 |
| KR101187642B1 (ko) * | 2011-05-02 | 2012-10-08 | 에스케이하이닉스 주식회사 | 집적 회로의 모니터링 장치 |
| KR101903520B1 (ko) * | 2012-01-06 | 2018-10-04 | 에스케이하이닉스 주식회사 | 반도체 장치 |
| US8830780B2 (en) * | 2013-01-15 | 2014-09-09 | Qualcomm Incorporated | System and method of performing power on reset for memory array circuits |
| US9891277B2 (en) * | 2014-09-30 | 2018-02-13 | Nxp Usa, Inc. | Secure low voltage testing |
| KR20160123843A (ko) * | 2015-04-17 | 2016-10-26 | 에스케이하이닉스 주식회사 | 반도체 장치 |
| KR102375054B1 (ko) * | 2015-12-11 | 2022-03-17 | 에스케이하이닉스 주식회사 | 테스트 모드 설정회로 및 이를 포함하는 반도체 장치 |
| JP2022044114A (ja) * | 2020-09-07 | 2022-03-17 | キオクシア株式会社 | 半導体集積回路およびその試験方法 |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3421760B2 (ja) * | 1994-10-11 | 2003-06-30 | 三菱電機株式会社 | Ｓｄｒａｍのパワーオンリセット信号発生回路 |
| US5572470A (en) * | 1995-05-10 | 1996-11-05 | Sgs-Thomson Microelectronics, Inc. | Apparatus and method for mapping a redundant memory column to a defective memory column |
-
1997
- 1997-11-14 JP JP31373997A patent/JP4141520B2/ja not_active Expired - Fee Related
-
1998
- 1998-04-13 US US09/058,987 patent/US5905690A/en not_active Expired - Lifetime
- 1998-05-20 TW TW087107783A patent/TW392167B/zh not_active IP Right Cessation
- 1998-07-10 CN CN98115697A patent/CN1107958C/zh not_active Expired - Fee Related
- 1998-07-11 KR KR1019980028029A patent/KR100282974B1/ko not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8031552B2 (en) | 2006-06-30 | 2011-10-04 | Hynix Semiconductor Inc. | Multi-port memory device with serial input/output interface |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1217545A (zh) | 1999-05-26 |
| KR19990044766A (ko) | 1999-06-25 |
| US5905690A (en) | 1999-05-18 |
| KR100282974B1 (ko) | 2001-03-02 |
| JPH11149771A (ja) | 1999-06-02 |
| JP4141520B2 (ja) | 2008-08-27 |
| CN1107958C (zh) | 2003-05-07 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GD4A | Issue of patent certificate for granted invention patent | ||
| MM4A | Annulment or lapse of patent due to non-payment of fees |