JP7274461B2 - 保護バリア層を使用して半導体構造を製造する装置および方法 - Google Patents

保護バリア層を使用して半導体構造を製造する装置および方法 Download PDF

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JP7274461B2
JP7274461B2 JP2020514961A JP2020514961A JP7274461B2 JP 7274461 B2 JP7274461 B2 JP 7274461B2 JP 2020514961 A JP2020514961 A JP 2020514961A JP 2020514961 A JP2020514961 A JP 2020514961A JP 7274461 B2 JP7274461 B2 JP 7274461B2
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layer
annealing
thickness
silicon
liner layer
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JP2020533803A (ja
JP2020533803A5 (enExample
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プラミット マンナ
アビジット バス マルリック
カーティス レスチキーズ
スティーヴン ヴェルハヴェルベケ
シーシー ジャン
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Applied Materials Inc
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Applied Materials Inc
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    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02296Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
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    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
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    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76828Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
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    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76837Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics

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  • Engineering & Computer Science (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Plasma & Fusion (AREA)
  • Robotics (AREA)
  • Formation Of Insulating Films (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Element Separation (AREA)
JP2020514961A 2017-09-12 2018-09-11 保護バリア層を使用して半導体構造を製造する装置および方法 Active JP7274461B2 (ja)

Applications Claiming Priority (3)

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US201762557501P 2017-09-12 2017-09-12
US62/557,501 2017-09-12
PCT/US2018/050464 WO2019055415A1 (en) 2017-09-12 2018-09-11 APPARATUS AND METHODS FOR MANUFACTURING SEMICONDUCTOR STRUCTURES USING A PROTECTIVE BARRIER LAYER

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JP2020533803A JP2020533803A (ja) 2020-11-19
JP2020533803A5 JP2020533803A5 (enExample) 2021-10-21
JP7274461B2 true JP7274461B2 (ja) 2023-05-16

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US (1) US11177128B2 (enExample)
JP (1) JP7274461B2 (enExample)
KR (1) KR102659317B1 (enExample)
CN (1) CN111095524B (enExample)
SG (1) SG11202001450UA (enExample)
TW (1) TWI697050B (enExample)
WO (1) WO2019055415A1 (enExample)

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US12142479B2 (en) * 2020-01-17 2024-11-12 Asm Ip Holding B.V. Formation of SiOCN thin films
US12341005B2 (en) 2020-01-17 2025-06-24 Asm Ip Holding B.V. Formation of SiCN thin films
CN111261634A (zh) * 2020-02-10 2020-06-09 无锡拍字节科技有限公司 一种存储器件的制造设备及其方法
US11791155B2 (en) * 2020-08-27 2023-10-17 Applied Materials, Inc. Diffusion barriers for germanium
TWI749955B (zh) * 2020-09-28 2021-12-11 天虹科技股份有限公司 減少非輻射復合的微發光二極體的製作方法及製作機台
CN117546277A (zh) * 2021-08-23 2024-02-09 株式会社国际电气 半导体装置的制造方法、基板处理方法、基板处理装置以及程序
CN119170536A (zh) * 2024-11-21 2024-12-20 上海邦芯半导体科技有限公司 半导体处理机台

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