JP7274461B2 - 保護バリア層を使用して半導体構造を製造する装置および方法 - Google Patents
保護バリア層を使用して半導体構造を製造する装置および方法 Download PDFInfo
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- JP7274461B2 JP7274461B2 JP2020514961A JP2020514961A JP7274461B2 JP 7274461 B2 JP7274461 B2 JP 7274461B2 JP 2020514961 A JP2020514961 A JP 2020514961A JP 2020514961 A JP2020514961 A JP 2020514961A JP 7274461 B2 JP7274461 B2 JP 7274461B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
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- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68707—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a robot blade, or gripped by a gripper for conveyance
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Plasma & Fusion (AREA)
- Robotics (AREA)
- Formation Of Insulating Films (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Element Separation (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201762557501P | 2017-09-12 | 2017-09-12 | |
| US62/557,501 | 2017-09-12 | ||
| PCT/US2018/050464 WO2019055415A1 (en) | 2017-09-12 | 2018-09-11 | APPARATUS AND METHODS FOR MANUFACTURING SEMICONDUCTOR STRUCTURES USING A PROTECTIVE BARRIER LAYER |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2020533803A JP2020533803A (ja) | 2020-11-19 |
| JP2020533803A5 JP2020533803A5 (enExample) | 2021-10-21 |
| JP7274461B2 true JP7274461B2 (ja) | 2023-05-16 |
Family
ID=65724027
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2020514961A Active JP7274461B2 (ja) | 2017-09-12 | 2018-09-11 | 保護バリア層を使用して半導体構造を製造する装置および方法 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US11177128B2 (enExample) |
| JP (1) | JP7274461B2 (enExample) |
| KR (1) | KR102659317B1 (enExample) |
| CN (1) | CN111095524B (enExample) |
| SG (1) | SG11202001450UA (enExample) |
| TW (1) | TWI697050B (enExample) |
| WO (1) | WO2019055415A1 (enExample) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US12142479B2 (en) * | 2020-01-17 | 2024-11-12 | Asm Ip Holding B.V. | Formation of SiOCN thin films |
| US12341005B2 (en) | 2020-01-17 | 2025-06-24 | Asm Ip Holding B.V. | Formation of SiCN thin films |
| CN111261634A (zh) * | 2020-02-10 | 2020-06-09 | 无锡拍字节科技有限公司 | 一种存储器件的制造设备及其方法 |
| US11791155B2 (en) * | 2020-08-27 | 2023-10-17 | Applied Materials, Inc. | Diffusion barriers for germanium |
| TWI749955B (zh) * | 2020-09-28 | 2021-12-11 | 天虹科技股份有限公司 | 減少非輻射復合的微發光二極體的製作方法及製作機台 |
| CN117546277A (zh) * | 2021-08-23 | 2024-02-09 | 株式会社国际电气 | 半导体装置的制造方法、基板处理方法、基板处理装置以及程序 |
| CN119170536A (zh) * | 2024-11-21 | 2024-12-20 | 上海邦芯半导体科技有限公司 | 半导体处理机台 |
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| JP2005347636A (ja) | 2004-06-04 | 2005-12-15 | Az Electronic Materials Kk | トレンチ・アイソレーション構造の形成方法 |
| JP2012231007A (ja) | 2011-04-26 | 2012-11-22 | Elpida Memory Inc | 半導体装置の製造方法 |
| JP2013517616A (ja) | 2010-01-06 | 2013-05-16 | アプライド マテリアルズ インコーポレイテッド | 酸化物ライナを使用する流動可能な誘電体 |
| JP2013533639A (ja) | 2010-07-30 | 2013-08-22 | アプライド マテリアルズ インコーポレイテッド | 流動性cvdによる間隙充填用の酸化物を多く含むライナ層 |
| US20160336405A1 (en) | 2015-05-11 | 2016-11-17 | Applied Materials, Inc. | Horizontal gate all around and finfet device isolation |
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| US11177128B2 (en) | 2021-11-16 |
| KR20200042009A (ko) | 2020-04-22 |
| KR102659317B1 (ko) | 2024-04-18 |
| JP2020533803A (ja) | 2020-11-19 |
| SG11202001450UA (en) | 2020-03-30 |
| TW201923901A (zh) | 2019-06-16 |
| CN111095524A (zh) | 2020-05-01 |
| TWI697050B (zh) | 2020-06-21 |
| WO2019055415A1 (en) | 2019-03-21 |
| US20200388486A1 (en) | 2020-12-10 |
| CN111095524B (zh) | 2023-10-03 |
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