JP6542990B2 - 柱状半導体装置の製造方法 - Google Patents
柱状半導体装置の製造方法 Download PDFInfo
- Publication number
- JP6542990B2 JP6542990B2 JP2018520341A JP2018520341A JP6542990B2 JP 6542990 B2 JP6542990 B2 JP 6542990B2 JP 2018520341 A JP2018520341 A JP 2018520341A JP 2018520341 A JP2018520341 A JP 2018520341A JP 6542990 B2 JP6542990 B2 JP 6542990B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- layers
- material layer
- pillar
- conductive material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 120
- 238000004519 manufacturing process Methods 0.000 title claims description 58
- 239000010410 layer Substances 0.000 claims description 1032
- 239000004020 conductor Substances 0.000 claims description 131
- 239000000463 material Substances 0.000 claims description 78
- 239000012535 impurity Substances 0.000 claims description 72
- 238000000034 method Methods 0.000 claims description 60
- 229910052751 metal Inorganic materials 0.000 claims description 40
- 239000002184 metal Substances 0.000 claims description 40
- 238000005530 etching Methods 0.000 claims description 31
- 239000000758 substrate Substances 0.000 claims description 28
- 238000001459 lithography Methods 0.000 claims description 20
- 238000010438 heat treatment Methods 0.000 claims description 13
- 230000008569 process Effects 0.000 claims description 8
- 229910045601 alloy Inorganic materials 0.000 claims description 4
- 239000000956 alloy Substances 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- 239000011229 interlayer Substances 0.000 claims description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 151
- 229910021334 nickel silicide Inorganic materials 0.000 description 87
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 87
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 49
- 229910052581 Si3N4 Inorganic materials 0.000 description 45
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 45
- 239000000370 acceptor Substances 0.000 description 21
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 20
- 229910021332 silicide Inorganic materials 0.000 description 18
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 18
- 238000001020 plasma etching Methods 0.000 description 15
- 230000002093 peripheral effect Effects 0.000 description 13
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 12
- 230000000149 penetrating effect Effects 0.000 description 11
- 230000015572 biosynthetic process Effects 0.000 description 10
- 238000010586 diagram Methods 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 7
- 238000000231 atomic layer deposition Methods 0.000 description 6
- 239000002344 surface layer Substances 0.000 description 5
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 4
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- PEUPIGGLJVUNEU-UHFFFAOYSA-N nickel silicon Chemical compound [Si].[Ni] PEUPIGGLJVUNEU-UHFFFAOYSA-N 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000001125 extrusion Methods 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
- H01L21/2253—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
- H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
- H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
- H01L21/28132—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects conducting part of electrode is difined by a sidewall spacer or a similar technique, e.g. oxidation under mask, plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28568—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising transition metals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/764—Air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8221—Three dimensional integrated circuits stacked in different levels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823456—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
- H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Geometry (AREA)
- Composite Materials (AREA)
- Materials Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Non-Volatile Memory (AREA)
Description
基板と、
前記基板上に対して垂直方向に延在する半導体柱と、
前記半導体柱の外周を囲むゲート絶縁層と、
前記ゲート絶縁層を囲むゲート導体層と、
前記垂直方向において前記ゲート導体層の上端以上で前記半導体柱の頂部以下の高さに上面位置を有する層間絶縁層と、
を有する半導体構造体を提供する工程と、
露出している前記半導体柱の上部の側面を囲んで第1の材料層を形成する工程と、
前記第1の材料層を囲んで第2の材料層を形成する工程と、
前記第2の材料層をエッチングマスクにして、前記第1の材料層をエッチングして、前記第2の材料層内に第1のコンタクトホールを形成する工程と、
前記第1のコンタクトホールに導電性を有する第1の導電材料層を形成する工程と、を備える、
ことを特徴とする。
前記半導体柱の前記上部に前記第1の導電材料層の側面に繋がる前記アクセプタまたはドナー不純物を含む第1の不純物領域を形成する工程と、をさらに備える、
ことがさらに好ましい。
前記ゲート導体層、前記別のゲート導体層、前記第1の不純物領域、前記第2の不純物領域、前記第3の不純物領域、及び前記第4の不純物領域から選ばれる異なる部位にそれぞれ接続され、前記基板に水平に延在し、平面視において互いに少なくとも部分的に重なり、且つ下から上にこの順番で存在する第1の配線導体層、第2の配線導体層、及び第3の配線導体層を含む積層構造体を提供する工程と、
前記第2の材料層の上表面から前記第1の配線導体層の上表面又は内部までつづき、前記第3の配線導体層及び前記第2の配線導体層を貫通する第2のコンタクトホールを形成する工程と、
前記第2のコンタクトホールに露出した前記第2の配線導体層の側面に第1の管状絶縁層を形成する工程と、
前記第2のコンタクトホールを充満して導電性を有する第2の導電材料層を形成する工程と、
前記第2の導電材料層の上部の側面を露出させる工程と、をさらに備え、
前記第1の材料層を形成する工程は、前記第2の導電材料層の前記上部の前記側面を囲んで第3の材料層を形成する工程を含み、
前記第2の材料層を形成する工程は、前記第3の材料層を囲んで第4の材料層を形成する工程を含み、そして、
前記第4の材料層をエッチングマスクにして、前記第3の材料層をエッチングして、前記第4の材料層内に第3のコンタクトホールを形成する工程と、
前記第3のコンタクトホールに導電性を有する第3の導電材料層を形成する工程と、をさらに備える、
ことがさらに好ましい。
熱処理により、前記第1の導電材料層の前記金属原子を、前記半導体柱の前記上部内に拡散させて、前記半導体柱の前記上部内に合金層を形成する工程をさらに備える、
ことがさらに好ましい。
前記第1の不純物領域を形成する工程では、熱処理により前記アクセプタまたはドナー不純物を、前記半導体柱の前記上部内に拡散させて、前記第1の不純物領域を形成する、
ことがさらに好ましい。
第4の導電材料層を前記第4のコンタクトホールに充満する工程と、
前記第1の導電材料層と前記第4の導電材料層との頂部表面を面一にする工程と、をさらに備える、
ことがさらに好ましい。
ことがさらに好ましい。
ことがさらに好ましい。
リソグラフィ法とエッチングにより、前記配線材料層から、前記第1の導電材料層に繋がった第4の配線導体層と、前記第3の導電材料層に繋がった第5の配線導体層との、一方または両者を、前記第2の材料層上に形成する工程を含み、
前記エッチングにおける、前記第4の配線導体層及び前記第5の配線導体層のエッチング速度が、前記第1の導電材料層、前記第2の導電材料層、及び前記第3の導電材料層のエッチング速度より早い、
ことがさらに好ましい。
ことがさらに好ましい。
以下、図1A、図1B、図2A〜図2Wを参照しながら、本発明の第1実施形態に係る、SGTを有する柱状半導体装置の製造方法について説明する。
Si柱SP1には、図1AにおけるPチャネル型SGT_Pc1が上部に形成され、Pチャネル型SGT_Pc2が下部に形成されている。Pチャネル型SGT_Pc1、Pc2はSi柱SP1の中間にあるSiO2層Ox1で分離されている。Pチャネル型SGT_Pc1は、チャネルであるSi柱SP1の一部と、このSi柱SP1の一部を囲むゲートGp1と、ゲートGp1の上下のSi柱SP1内にあるドレインP+層Pd1とソースP+層Ps1とより形成されている。Pチャネル型SGT_Pc2は、チャネルであるSi柱SP1の一部と、このSi柱SP1の一部を囲むゲートGp2と、ゲートGp2の上下のSi柱SP1内にあるドレインP+層Pd2とソースP+層Ps2とより形成されている。
Si柱SP2には、図1AにおけるNチャネル型SGT_Nc1が上部に形成され、Nチャネル型SGT_Nc2が下部に形成されている。Nチャネル型SGT_Nc1、Nc2はSi柱SP2の中間にあるSiO2層Ox2で分離されている。Nチャネル型SGT_Nc1は、チャネルであるSi柱SP2の一部と、このSi柱SP2の一部を囲むゲートGn1と、ゲートGn1の上下のSi柱SP2内にあるドレインN+層Nd1とソースN+層Ns1とより形成されている。Nチャネル型SGT_Nc2は、チャネルであるSi柱SP2の一部と、このSi柱SP2の一部を囲むゲートGn2と、ゲートGn2の上下のSi柱SP2内にあるドレインN+層Nd2とソースN+層Ns2とより形成されている。
Si柱SP3には、図1AにおけるNチャネル型SGT_SN1が上部に形成され、Nチャネル型SGT_SN2が下部に形成されている。Nチャネル型SGT_SN1、SN2はSi柱SP3の中間にあるSiO2層Ox3で分離されている。Nチャネル型SGT_SN1は、チャネルであるSi柱SP3の一部と、このSi柱SP3の一部を囲むゲートGs1と、ゲートGs1の上下のSi柱SP3内にあるドレインN+層Sd1とソースN+層Ss1とより形成されている。Nチャネル型SGT_SN2は、チャネルであるSi柱SP3の一部と、このSi柱SP3の一部を囲むゲートGs2と、ゲートGs2の上下のSi柱SP3内にあるドレインN+層Sd2とソースN+層Ss2とより形成されている。
次に、リソグラフィ法とRIE法を用いて、下層に残存するi層2をエッチングして、Si柱6aの外周部にi層2a1を、Si柱6bの外周部にi層2a2を、Si柱6cの外周部にi層2a3を形成する。
また、Si柱6bの上部に、N+層33b、38bをソース、ドレインとし、TiN層18dをゲートとし、N+層33b、38b間のSi柱6bをチャネルにしたSGT(図1BのNチャネル型SGT_Nc1に対応する)が形成され、Si柱6bの下部に、N+層8bb、31bをソース、ドレインとし、TiN層18aをゲートとし、N+層8bb、31b間のSi柱6aをチャネルにしたSGT(図1BのNチャネル型SGT_Nc2に対応する)が、形成される。
また、Si柱6cの上部に、N+層33c、38cをソース、ドレインとし、TiN層18eをゲートとし、N+層33c、38c間のSi柱6cをチャネルにしたSGT(図1BのNチャネル型SGT_SN1に対応する)が形成され、Si柱6cの下部に、N+層8cc、31cをソース、ドレインとし、TiN層18bをゲートとし、N+層8cc、31c間のSi柱6cをチャネルにしたSGT(図1BのNチャネル型SGT_Nc2に対応する)が、形成される。
これらSGT(図1BのSGT_Pc1、Pc2、Nc1、Nc2、SN1、SN2に対応する)が接続配線されて、図1Bに示した模式構造図と同じく、Si柱6a、6b、6cの上部に形成されたPチャネル型SGT(図1BのPチャネル型SGT_Pc1に対応する)及びNチャネル型SGT(図1BのNチャネル型SGT_Nc1、SN1に対応する)による回路領域(図1Bの回路領域C1に対応する)と、Si柱6a、6b、6cの下部に形成されたPチャネル型SGT(図1BのPチャネル型SGT_Pc2に対応する)及びNチャネル型SGT(図1BのNチャネル型SGT_Nc2、SN2に対応する)による回路領域(図1Bの回路領域C2に対応する)と、により構成されたSRAMセル回路が形成される。
1.図2Wに示されるように、P+層38a、N+層38b、38cは、側面と上表面との全体を低抵抗金属層であるW層52c、52d、52eと、低抵抗シリサイド層であるNiSi層66a、66b、66eと、で囲まれている。W層52c、52d、52eの底部位置は、P+層38a、N+層38b、38cの下端に近い位置に形成されている。これにより、P+層38a、N+層38b、38cによるダイオード接合抵抗を低くでき、且つP+層38a、N+層38b、38cによるダイオード接合に均一な電界を形成することができる。これは、SGT回路の低電圧駆動化と高速化に寄与できる。
2.W層43a、43bとSi柱6a、6b、6cの頂部のP+層38a、N+層38b、38cとを平面視において円帯状に囲むSiO2層46a、46b、46c、46d、46eをエッチングして得られる構造を用いて、W層43a、43bとSi柱6a、6b、6cの頂部のP+層38a、N+層38b、38cとを平面視において円帯状に囲むW層52a、52b、52c、52d、52eが形成される。SiO2層46a、46b、46c、46d、46eは、W層43a、43bとSi柱6a、6b、6cとの位置関係について、リソグラフィ法におけるマスク合せ工程を必要としない自己整合(self-arraignment)で形成される。これにより、W層52a、52b、52c、52d、52eは、W層43a、43bとSi柱6a、6b、6cとに対して、自己整合で形成される。これはSGT回路を高密度に形成できることを示している。
3.図2Rに示したように、最初に、垂直方向において、同じ深さのコンタクトホール50a、50b、50c、50d、50eを形成し、その後に、図2Sに示すように、コンタクトホール50b、50c、50d、50eを覆ったレジスト層(図示せず)とAlO層51をマスクにして、RIE法により、コンタクトホール50aaとコンタクトホール50bbをそれぞれ形成する。こうして、コンタクトホール50c、50d、50eの深さと、コンタクトホール50aaの深さと、コンタクトホール50bbの深さとを異なるものにできる。これは、深さの異なるW層52c、52d、52eと、W層52aと、W層52bとを容易に形成できることを示している。これにより、SGT回路の製作が容易になる。
4.W層43aに面したNiSi層28bbの側面にSiO2層41aが形成されている。これにより、平面視において、NiSi層28aa、28bb、36aが、お互いに重なっているのにも関わらず、これらを貫通するW層43aとNiSi層28bbとを絶縁しつつ、NiSi層28aaとNiSi層36aとを接続することが可能となる。これは、SRAMセル面積の縮小を可能にする。
同様に、W層43bに面したNiSi層28aaの側面にSiO2層41bが形成されている。これにより、平面視において、TiN層18a、NiSi層28aa、28bbが、お互いに重なっているのにも関わらず、これらを貫通するW層43bによって、W層43bとNiSi層28aaを絶縁しつつ、TiN層18aとNiSi層28bbとを接続することが可能となる。これは、SRAMセル面積の縮小を可能にする。
5.平面視において互いに重なった、下部配線導体層であるNiSi層28aa、中間配線導体層であるNiSi層28bb、上部配線導体層であるNiSi層36aを有する構造において、NiSi層28aa上に、NiSi層28bb、36aを貫通して、且つ頂部がNiSi層36aより上部に位置するW層43aを形成し、そして、このW層43aの外周を囲み、特別なリソグラフィ法を用いないで、自己整合で形成されたW層52aが、NiSi層36aとその上表面に接続されることにより、NiSi層36aと28aaとの接続が実現されている。
同様に、平面視において互いに重なった、下部配線導体層であるTiN層18a、中間配線導体層であるNiSi層28aa、上部配線導体層であるNiSi層28bbを有する構造において、TiN層18a上に、NiSi層28aa、28bbを貫通して、且つ頂部がNiSi層28bbより上部に位置するW層43bを形成し、そして、このW層43bの外周を囲み、特別なリソグラフィ法を用いないで、自己整合で形成されたW層52bが、NiSi層28bbと、その上表面に接続されることにより、NiSi層28bbとTiN層18aとの接続が実現されている。
このように、W層43aとW層52aとが自己整合で形成され、W層43bとW層52bとが自己整合で形成されている。これにより、SRAMセルの高密度配線が実現する。
6.SGT回路の低電圧駆動化と高速化に寄与する、P+層38a、N+層38b、38cの側面全体を円帯状に囲んだW層52c、52d、52eと、SGT回路の高密度化に寄与するW層43a、43bの頂部側面全体を円帯状に囲んだW層52a、52bと、をそれぞれが自己整合プロセスで、かつ同じ工程で行うことができる。これにより、高密度SGT回路を容易に形成することができる。
7.図2P、図2Qに示したように、W層43a、43bの頂部と、Si柱6a、6b、6cの頂部のP+層38a、N+層38b、38cと、を覆ってSiO2層(図示せず)を堆積し、その後に、RIE法により、このSiO2層をエッチングして、W層43a、43bの頂部と、Si柱6a、6b、6cの頂部のP+層38a、N+層38b、38cと、を囲んでSiO2層46a、46b、46c、46d、46eを形成した。平面視における、SiO2層46a、46b、46c、46d、46eの幅長は、リソグラフィ法を用いて形成した場合より、リソグラフィ法におけるマスク合わせ寸法余裕を確保する必要がないので、短く形成することが可能である。また、平面視において、W層43a、43bと、P+層38a、N+層38b、38cと、SiO2層46a、46b、46c、46d、46eと、の位置関係が自己整合により形成されている。これにより、W層43a、43bと、P+層38a、N+層38b、38cと、W層52a、52b、52c、52d、52eとの接続を、高密度に形成することができる。
以下、図3A、図3Bを参照しながら、本発明の第2実施形態に係る、SGTを有する柱状半導体装置の製造方法について説明する。(a)は平面図、(b)は(a)のX−X’線に沿う断面構造図、(c)は(a)のY1−Y1’線に沿う断面構造図、(d)は(a)のY2−Y2’線に沿う断面構造図、(e)は(a)のY3−Y3’線に沿った断面構造図である。第2実施形態の製造方法は、以下に説明する相違点を除き、第1実施形態の図2A〜図2Wに示す工程と同様である。
本実施形態では、第1実施形態におけるP+層38a、N+層38b、38cの多くの部分がシリサイド層であるNiSi層64a、64b、64cに置き換えられた構造となっている。更に、NiSi層64a、64b、64cからのドナー、またはアクセプタ不純物の押し出し効果により高濃度の不純物密度を持つP+層65a、N+層65b、65cが形成される。これにより、第1実施形態と比べて、ダイオード接合抵抗がさらに低抵抗化される。これは、SGT回路の低電圧駆動化、高速駆動化に繋がる。
以下、図4A、図4Bを参照しながら、本発明の第3実施形態に係る、SGTを有する柱状半導体装置の製造方法について説明する。(a)は平面図、(b)は(a)のX−X’線に沿う断面構造図、(c)は(a)のY1−Y1’線に沿う断面構造図、(d)は(a)のY2−Y2’線に沿う断面構造図、(e)は(a)のY3−Y3’線に沿った断面構造図である。第3実施形態の製造方法は、以下に説明する相違点を除き、第1実施形態の図2A〜図2Wに示す工程と同様である。
1.本実施形態では、Si層の形成に例えばドナー又はアクセプタ不純物を高濃度に含んだSiエピタキシャル法を用いてSi層67c、67d、67eを形成することができる。これにより、Si柱6a、6b、6c頂部に低抵抗のP+層38a、N+層38b、38cを形成することができる。これにより、高速なSGT回路を製作することが可能となる。
2.アクセプタまたはドナーを含んだSi層67c、67d、67eに替えて、アクセプタまたはドナーを含んだシリサイド層を用いた場合は、Si柱6a、6b、6cの頂部に、第3実施形態と同様なシリサイド層が形成される。これは、SGT回路の低電圧駆動化、高速駆動化に繋がる。
以下、図5を参照しながら、本発明の第4実施形態に係る、SGTを有する柱状半導体装置の製造方法について説明する。(a)は平面図、(b)は(a)のX−X’線に沿う断面構造図、(c)は(a)のY1−Y1’線に沿う断面構造図、(d)は(a)のY2−Y2’線に沿う断面構造図、(e)は(a)のY3−Y3’線に沿った断面構造図である。
第1実施形態では、コンタクトホール55a、55b、55c、55d、57、60a、60bの底部位置が、それぞれ異なっていた。これに対して、本実施形態では、コンタクトホール55a、55b、60a、71a、71b、71c、71dの底部位置が、W層43a、43b、52a、52b、52c、52d、52e、70a、70bの頂部表面位置になっている。これにより、コンタクトホール55a、55b、60a、71a、71b、71c、71dを介した配線金属層VDD、VSS、BL、BLR、WLの形成が容易になる。例えば、CPUチップのようにSRAMセル領域と同じチップ上に論理回路を形成する場合、配線金属層の層数が数10層に及ぶので、論理回路部の形成を含めて、配線金属層に繋がるコンタクトホールの底部位置を高さ方向で同じにするのは、配線金属層の高密度形成に繋がる。
以下、図6を参照しながら、本発明の第5実施形態に係る、SGTを有する柱状半導体装置の製造方法について説明する。(a)は平面図、(b)は(a)のX−X’線に沿う断面構造図、(c)は(a)のY1−Y1’線に沿う断面構造図、(d)は(a)のY2−Y2’線に沿う断面構造図、(e)は(a)のY3−Y3’線に沿った断面構造図である。
1.本実施形態では、W層43a、52aに繋がるW層72aと、N+層38c及びW層52eに繋がるW層72bとを形成した。これは、設計上の必要性により、W層52a、52b、52c、52d、52eのいずれか、または全てに繋がったW配線層をAlO層51上に形成できることを示している。これにより、SRAM回路だけでなく、他の回路設計に本実施形態を適用することにより、回路の高性能化を図ることができる。
2.また、第1実施形態における図2A〜図2Tまでの工程を行った後に、W層43a、43b、52a、52b、及びAlO層51の上に、タングステン以外の配線材料層を形成しても、同様に、W層52a、52b、52c、52d、52eのいずれか、または全てに繋がった金属配線層をAlO層51上に形成できる。これにより、SRAM回路だけでなく、他の回路設計に本実施形態を適用することにより、回路の高性能化を図ることができる。この場合、リソグラフィ工程の後の配線材料層のエッチングが、W層より早くエッチングされるようになされることが望ましい。これにより、W層52a、52b、52c、52d、52eの中で、レジストで覆われてないW層がエッチングされることなく、配線材料層がパターンニングされる利点が得られる。
Nc1、Nc2、Nc3、Nc4、SN1、SN2 Nチャネル型SGT
BLt ビット線端子
BLRt 反転ビット線端子
WLt ワード線端子
Vss グランド端子
Vdd 電源端子
C1、C2 回路領域
Gp1、Gp2、Gn1、Gn2、Gs1、Gs2 ゲート
1 SiO2層基板
2、2a1、2a2、2a3、2b1、2b2、2b3、4、4a、4b、4c i層
Ns1、Ns2、Nd1、Nd2、Sd1、Sd2、NS1、ND、Ss1、SD1、SD2、Ss2、8b、8c、8bb、8cc、31b、31c、33b、33c、38b、38c、65b、65c、68b、68c N+層
Ps1、Ps2、Pd1、Pd2、8a、8aa、31a、33a、38a、65a、68a P+層
Ox1、Ox2、Ox3、3、3a、3b、3c、5、5a、5b、5c、7a、7b、7c、10、14、14a、14b、14c、14d、23a、23b、23aa、23bb、37、39b、41a、41b、46a、46b、46c、46d、46e、54、56、58、63 SiO2層
SP1、SP2、SP3、6a、6b、6c Si柱
11、11a、11b、11c、11d HfO2層
12、12a、12b、18a、18b、18c、18d、18e TiN層
15、35、39a SiN層
51 AlO層
16、27 レジスト層
20a、20b、20c、20d、20e、20f TiO層
21a、21b Ni層
22a、22b P型ポリSi層
26a、26b N+型ポリSi層
25a、25b、25c 空間
28a、28b、28aa、28bb、30a、30b、30c、32a、32b、32c、36a、36b、62a、62b、62c、62d、62e、64a、64b、64c、66a、66b、66c、66d、66e、66f NiSi層
67a、67b、67c、67d、67e Si層
40a、40b、50a、50b、50c、50d、50e、50aa、50bb、55a、55b、55c、55d、55e、57、60a、60b、71a、71b、71c、71d コンタクトホール
43a、43b、52a、52b、52c、52d、52e、70a、70b、70c、70d、72a、72b W層
VDD 電源配線金属層
VSS グランド配線金属層
WL ワード線配線金属層
BL ビット線配線金属層
BLR 反転ビット線配線金属層
Claims (10)
- 基板と、
前記基板上に対して垂直方向に延在する半導体柱と、
前記半導体柱の外周を囲むゲート絶縁層と、
前記ゲート絶縁層を囲むゲート導体層と、
前記垂直方向において前記ゲート導体層の上端以上で前記半導体柱の頂部以下の高さに上面位置を有する層間絶縁層と、
を有する半導体構造体を提供する工程と、
露出している前記半導体柱の上部の側面を囲んで第1の材料層を形成する工程と、
前記第1の材料層を囲んで第2の材料層を形成する工程と、
前記第2の材料層をエッチングマスクにして、前記第1の材料層をエッチングして、前記第2の材料層内に第1のコンタクトホールを形成する工程と、
前記第1のコンタクトホールに導電性を有する第1の導電材料層を形成する工程と、を備える、
ことを特徴とする柱状半導体装置の製造方法。 - 前記半導体柱内で前記半導体柱の前記上部より下方にアクセプタまたはドナー不純物を含む第2の不純物領域を形成する工程と、
前記半導体柱の前記上部に前記第1の導電材料層の側面に繋がる前記アクセプタまたはドナー不純物を含む第1の不純物領域を形成する工程と、をさらに備える、
ことを特徴とする請求項1に記載の柱状半導体装置の製造方法。 - 前記基板に対して垂直方向に延在する前記半導体柱とは別の半導体柱と、前記別の半導体柱の外周を囲む前記ゲート絶縁層とは別のゲート絶縁層と、前記別のゲート絶縁層を囲む前記ゲート導体層とは別のゲート導体層と、前記別の半導体柱内に互いに離れて形成された第3の不純物領域及び第4の不純物領域とを有する、前記半導体構造体とは異なる1個または複数個の別の半導体構造体と、
前記ゲート導体層、前記別のゲート導体層、前記第1の不純物領域、前記第2の不純物領域、前記第3の不純物領域、及び前記第4の不純物領域から選ばれる異なる部位にそれぞれ接続され、前記基板に水平に延在し、平面視において互いに少なくとも部分的に重なり、且つ下から上にこの順番で存在する第1の配線導体層、第2の配線導体層、及び第3の配線導体層を含む積層構造体を提供する工程と、
前記第2の材料層の上表面から前記第1の配線導体層の上表面又は内部までつづき、前記第3の配線導体層及び前記第2の配線導体層を貫通する第2のコンタクトホールを形成する工程と、
前記第2のコンタクトホールに露出した前記第2の配線導体層の側面に第1の管状絶縁層を形成する工程と、
前記第2のコンタクトホールを充満して導電性を有する第2の導電材料層を形成する工程と、
前記第2の導電材料層の上部の側面を露出させる工程と、をさらに備え、
前記第1の材料層を形成する工程は、前記第2の導電材料層の前記上部の前記側面を囲んで第3の材料層を形成する工程を含み、
前記第2の材料層を形成する工程は、前記第3の材料層を囲んで第4の材料層を形成する工程を含み、そして、
前記第4の材料層をエッチングマスクにして、前記第3の材料層をエッチングして、前記第4の材料層内に第3のコンタクトホールを形成する工程と、
前記第3のコンタクトホールに導電性を有する第3の導電材料層を形成する工程と、をさらに備える、
ことを特徴とする請求項2に記載の柱状半導体装置の製造方法。 - 前記第1の導電材料層が少なくとも金属原子と半導体原子とを含み、
熱処理により、前記第1の導電材料層の前記金属原子を、前記半導体柱の前記上部内に拡散させて、前記半導体柱の前記上部内に合金層を形成する工程をさらに備える、
ことを特徴とする請求項1に記載の柱状半導体装置の製造方法。 - 前記第1の導電材料層が前記アクセプタまたはドナー不純物を含み、
前記第1の不純物領域を形成する工程では、熱処理により前記アクセプタまたはドナー不純物を、前記半導体柱の前記上部内に拡散させて、前記第1の不純物領域を形成する、
ことを特徴とする請求項2に記載の柱状半導体装置の製造方法。 - 平面視において、前記第1のコンタクトホールの場所以外にあり、前記ゲート導体層、前記第1の不純物領域、又は前記第2の不純物領域に接続され水平方向に延在する配線導体層に繋がり、且つ前記第2の材料層の表面より下方に延びる第4のコンタクトホールを形成する工程と、
第4の導電材料層を前記第4のコンタクトホールに充満する工程と、
前記第1の導電材料層と前記第4の導電材料層との頂部表面を面一にする工程と、をさらに備える、
ことを特徴とする請求項2に記載の柱状半導体装置の製造方法。 - 前記第1の導電材料層と、前記第2の導電材料層と、前記第3の導電材料層との頂部表面を面一にする工程を備える、
ことを特徴とする請求項3に記載の柱状半導体装置の製造方法。 - 前記第1の導電材料層を形成する工程及び前記第3の導電材料層を形成する工程は、導体材料を、前記第1のコンタクトホール及び前記第3のコンタクトホールに充満させ、且つ前記第2の材料層上に堆積し、その後、リソグラフィ法とエッチングにより、前記導体材料から、前記第1の導電材料層に繋がった第1の配線導体層と、前記第3の導電材料層に繋がった第2の配線導体層との、一方または両者を、前記第2の材料層上に形成することで行われる、
ことを特徴とする請求項3に記載の柱状半導体装置の製造方法。 - 前記第1の導電材料層と、前記第2の導電材料層と、前記第3の導電材料層との頂部表面を面一にする工程の後、前記第2の材料層上に配線材料層を堆積する工程と、
リソグラフィ法とエッチングにより、前記配線材料層から、前記第1の導電材料層に繋がった第4の配線導体層と、前記第3の導電材料層に繋がった第5の配線導体層との、一方または両者を、前記第2の材料層上に形成する工程を含み、
前記エッチングにおける、前記第4の配線導体層及び前記第5の配線導体層のエッチング速度が、前記第1の導電材料層、前記第2の導電材料層、及び前記第3の導電材料層のエッチング速度より早い、
ことを特徴とする請求項7に記載の柱状半導体装置の製造方法。 - 前記第1の材料層が、平面視において、等幅で前記半導体柱の上部を囲んで形成される、
ことを特徴とする請求項1に記載の柱状半導体装置の製造方法。
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2015/060763 WO2016162927A1 (ja) | 2015-04-06 | 2015-04-06 | 柱状半導体メモリ装置と、その製造方法 |
PCT/JP2015/069689 WO2017006468A1 (ja) | 2015-07-08 | 2015-07-08 | 柱状半導体メモリ装置と、その製造方法 |
JPPCT/JP2016/066151 | 2016-06-01 | ||
PCT/JP2016/066151 WO2017061139A1 (ja) | 2015-04-06 | 2016-06-01 | 柱状半導体装置の製造方法 |
PCT/JP2016/089129 WO2017208486A1 (ja) | 2015-04-06 | 2016-12-28 | 柱状半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2017208486A1 JPWO2017208486A1 (ja) | 2018-08-30 |
JP6542990B2 true JP6542990B2 (ja) | 2019-07-10 |
Family
ID=57072210
Family Applications (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2017511450A Active JP6378826B2 (ja) | 2015-04-06 | 2015-10-09 | Sgtを有する柱状半導体装置と、その製造方法 |
JP2017544382A Active JP6503470B2 (ja) | 2015-04-06 | 2016-06-01 | 柱状半導体装置の製造方法 |
JP2018520341A Active JP6542990B2 (ja) | 2015-04-06 | 2016-12-28 | 柱状半導体装置の製造方法 |
JP2018559129A Active JP6793409B2 (ja) | 2015-04-06 | 2017-12-21 | 柱状半導体装置の製造方法 |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2017511450A Active JP6378826B2 (ja) | 2015-04-06 | 2015-10-09 | Sgtを有する柱状半導体装置と、その製造方法 |
JP2017544382A Active JP6503470B2 (ja) | 2015-04-06 | 2016-06-01 | 柱状半導体装置の製造方法 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2018559129A Active JP6793409B2 (ja) | 2015-04-06 | 2017-12-21 | 柱状半導体装置の製造方法 |
Country Status (3)
Country | Link |
---|---|
US (4) | US10217865B2 (ja) |
JP (4) | JP6378826B2 (ja) |
WO (4) | WO2016163045A1 (ja) |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6378826B2 (ja) * | 2015-04-06 | 2018-08-22 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | Sgtを有する柱状半導体装置と、その製造方法 |
CN110366775B (zh) * | 2016-12-28 | 2023-06-02 | 新加坡优尼山帝斯电子私人有限公司 | 柱状半导体装置的制造方法 |
CN110192280A (zh) * | 2017-01-12 | 2019-08-30 | 美光科技公司 | 存储器单元、双晶体管单电容器存储器单元阵列、形成双晶体管单电容器存储器单元阵列的方法及用于制造集成电路的方法 |
KR102350485B1 (ko) * | 2017-08-18 | 2022-01-14 | 삼성전자주식회사 | 반도체 소자 |
JPWO2019142670A1 (ja) | 2018-01-19 | 2021-01-07 | 株式会社ソシオネクスト | 半導体集積回路装置 |
US10756217B2 (en) * | 2018-02-15 | 2020-08-25 | Micron Technology, Inc. | Access devices formed with conductive contacts |
KR102431218B1 (ko) * | 2018-10-01 | 2022-08-09 | 유니산티스 일렉트로닉스 싱가포르 프라이빗 리미티드 | 기둥상 반도체 장치의 제조 방법 |
US11349025B2 (en) * | 2018-10-31 | 2022-05-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-channel device to improve transistor speed |
US11217680B2 (en) * | 2019-05-23 | 2022-01-04 | International Business Machines Corporation | Vertical field-effect transistor with T-shaped gate |
KR20220002421A (ko) * | 2019-06-05 | 2022-01-06 | 유니산티스 일렉트로닉스 싱가포르 프라이빗 리미티드 | 기둥상 반도체 장치의 제조 방법 |
CN114127916A (zh) * | 2019-07-11 | 2022-03-01 | 新加坡优尼山帝斯电子私人有限公司 | 柱状半导体装置及其制造方法 |
US11373913B2 (en) * | 2019-09-03 | 2022-06-28 | Micron Technology, Inc. | Method of forming an array of vertical transistors |
US11177369B2 (en) * | 2019-09-25 | 2021-11-16 | International Business Machines Corporation | Stacked vertical field effect transistor with self-aligned junctions |
JP7350371B2 (ja) * | 2019-10-30 | 2023-09-26 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 柱状半導体装置と、その製造方法 |
US11222892B2 (en) * | 2020-06-15 | 2022-01-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Backside power rail and methods of forming the same |
US11640987B2 (en) * | 2021-02-04 | 2023-05-02 | Applied Materials, Inc. | Implant to form vertical FETs with self-aligned drain spacer and junction |
WO2023281728A1 (ja) * | 2021-07-09 | 2023-01-12 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体素子を用いたメモリ装置 |
CN116959984A (zh) * | 2022-04-18 | 2023-10-27 | 长鑫存储技术有限公司 | 半导体结构及其制备方法 |
EP4287241A4 (en) | 2022-04-18 | 2023-12-27 | Changxin Memory Technologies, Inc. | SEMICONDUCTOR STRUCTURE AND PRODUCTION PROCESS THEREOF |
Family Cites Families (52)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2703970B2 (ja) | 1989-01-17 | 1998-01-26 | 株式会社東芝 | Mos型半導体装置 |
JPH0324753A (ja) * | 1989-06-22 | 1991-02-01 | Nec Corp | 半導体装置用パッケージ |
US7052941B2 (en) | 2003-06-24 | 2006-05-30 | Sang-Yun Lee | Method for making a three-dimensional integrated circuit structure |
KR100510997B1 (ko) * | 2000-06-29 | 2005-08-31 | 주식회사 하이닉스반도체 | 복합 반도체소자의 접합전극 형성방법 |
US6670642B2 (en) | 2002-01-22 | 2003-12-30 | Renesas Technology Corporation. | Semiconductor memory device using vertical-channel transistors |
DE10350751B4 (de) * | 2003-10-30 | 2008-04-24 | Infineon Technologies Ag | Verfahren zum Herstellen eines vertikalen Feldeffekttransistors und Feldeffekt-Speichertransistor, insbesondere FLASH-Speichertransistor |
JP4293193B2 (ja) * | 2005-03-09 | 2009-07-08 | セイコーエプソン株式会社 | 半導体装置および半導体装置の製造方法 |
JP2009141110A (ja) * | 2007-12-06 | 2009-06-25 | Elpida Memory Inc | 半導体装置および半導体装置の製造方法 |
US8378425B2 (en) | 2008-01-29 | 2013-02-19 | Unisantis Electronics Singapore Pte Ltd. | Semiconductor storage device |
JP6014726B2 (ja) | 2008-02-15 | 2016-10-25 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | 半導体装置及びその製造方法 |
JP5779702B2 (ja) * | 2008-02-15 | 2015-09-16 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | 半導体装置及びその製造方法 |
WO2009110048A1 (ja) | 2008-02-15 | 2009-09-11 | 日本ユニサンティスエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
JP5632055B2 (ja) | 2008-02-15 | 2014-11-26 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | 半導体装置及びその製造方法 |
JP5356260B2 (ja) | 2008-02-15 | 2013-12-04 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体装置及びその製造方法 |
US8211758B2 (en) | 2008-02-15 | 2012-07-03 | Unisantis Electronics Singapore Pte Ltd. | Semiconductor device and method of producing the same |
JP2010040538A (ja) * | 2008-07-31 | 2010-02-18 | Toshiba Corp | 半導体装置の製造方法 |
US8395191B2 (en) * | 2009-10-12 | 2013-03-12 | Monolithic 3D Inc. | Semiconductor device and structure |
JP4530098B1 (ja) * | 2009-05-29 | 2010-08-25 | 日本ユニサンティスエレクトロニクス株式会社 | 半導体装置 |
JP2011023543A (ja) * | 2009-07-15 | 2011-02-03 | Renesas Electronics Corp | 半導体装置及び半導体装置の製造方法 |
JP5583933B2 (ja) * | 2009-07-28 | 2014-09-03 | 猛英 白土 | 半導体装置及びその製造方法 |
US9373694B2 (en) * | 2009-09-28 | 2016-06-21 | Semiconductor Manufacturing International (Shanghai) Corporation | System and method for integrated circuits with cylindrical gate structures |
CN102034863B (zh) * | 2009-09-28 | 2012-10-31 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件、含包围圆柱形沟道的栅的晶体管及制造方法 |
JP2012209340A (ja) * | 2011-03-29 | 2012-10-25 | Nec Corp | 多層基板及び多層基板の製造方法 |
US8575584B2 (en) * | 2011-09-03 | 2013-11-05 | Avalanche Technology Inc. | Resistive memory device having vertical transistors and method for making the same |
JP5701831B2 (ja) | 2012-09-06 | 2015-04-15 | 株式会社東芝 | パスゲートを備えた半導体記憶装置 |
US9368619B2 (en) * | 2013-02-08 | 2016-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for inducing strain in vertical semiconductor columns |
US9466668B2 (en) * | 2013-02-08 | 2016-10-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Inducing localized strain in vertical nanowire transistors |
WO2014141485A1 (ja) * | 2013-03-15 | 2014-09-18 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Sgtを有する半導体装置の製造方法 |
CN104303334B (zh) | 2013-05-15 | 2018-03-20 | 三洋电机株式会社 | 电池组和电池组的制造方法 |
JP5612237B1 (ja) * | 2013-05-16 | 2014-10-22 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | Sgtを有する半導体装置の製造方法 |
JP5731073B1 (ja) * | 2013-06-17 | 2015-06-10 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | 半導体装置の製造方法、及び、半導体装置 |
KR20150028419A (ko) * | 2013-09-06 | 2015-03-16 | 에스케이하이닉스 주식회사 | 반도체 장치 및 이의 제조 방법 |
KR20150034980A (ko) * | 2013-09-27 | 2015-04-06 | 에스케이하이닉스 주식회사 | 반도체 장치 및 이의 제조 방법 |
KR20150037168A (ko) * | 2013-09-30 | 2015-04-08 | 에스케이하이닉스 주식회사 | 수직 채널 트랜지스터를 갖는 반도체 소자 및 그의 제조방법 |
JP5639317B1 (ja) * | 2013-11-06 | 2014-12-10 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | Sgtを有する半導体装置と、その製造方法 |
JP5685351B1 (ja) * | 2013-12-25 | 2015-03-18 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | 柱状半導体装置の製造方法 |
US20150318288A1 (en) * | 2014-05-01 | 2015-11-05 | Globalfoundries Inc. | Vertical transistor static random access memory cell |
WO2015193940A1 (ja) * | 2014-06-16 | 2015-12-23 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体装置の製造方法、及び、半導体装置 |
JP5692884B1 (ja) * | 2014-08-19 | 2015-04-01 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | Sgtを有する半導体装置の製造方法 |
WO2016084205A1 (ja) * | 2014-11-27 | 2016-06-02 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 柱状半導体装置と、その製造方法 |
JP5938529B1 (ja) * | 2015-01-08 | 2016-06-22 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | 柱状半導体装置と、その製造方法 |
US9385195B1 (en) * | 2015-03-31 | 2016-07-05 | Stmicroelectronics, Inc. | Vertical gate-all-around TFET |
JP6378826B2 (ja) * | 2015-04-06 | 2018-08-22 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | Sgtを有する柱状半導体装置と、その製造方法 |
US9613955B1 (en) * | 2015-12-10 | 2017-04-04 | International Business Machines Corporation | Hybrid circuit including a tunnel field-effect transistor |
US9711618B1 (en) * | 2016-03-31 | 2017-07-18 | International Business Machines Corporation | Fabrication of vertical field effect transistor structure with controlled gate length |
US9954109B2 (en) * | 2016-05-05 | 2018-04-24 | International Business Machines Corporation | Vertical transistor including controlled gate length and a self-aligned junction |
US9865705B2 (en) * | 2016-06-02 | 2018-01-09 | International Business Machines Corporation | Vertical field effect transistors with bottom source/drain epitaxy |
US10580901B2 (en) * | 2016-09-02 | 2020-03-03 | International Business Machines Corporation | Stacked series connected VFETs for high voltage applications |
US10170616B2 (en) * | 2016-09-19 | 2019-01-01 | Globalfoundries Inc. | Methods of forming a vertical transistor device |
US10134642B2 (en) * | 2016-09-28 | 2018-11-20 | International Business Machines Corporation | Semiconductor device and method of forming the semiconductor device |
US9972494B1 (en) * | 2016-11-15 | 2018-05-15 | Globalfoundries Inc. | Method and structure to control channel length in vertical FET device |
US10164056B2 (en) * | 2017-05-17 | 2018-12-25 | International Business Machines Corporation | Vertical field effect transistors with uniform threshold voltage |
-
2015
- 2015-10-09 JP JP2017511450A patent/JP6378826B2/ja active Active
- 2015-10-09 WO PCT/JP2015/078776 patent/WO2016163045A1/ja active Application Filing
-
2016
- 2016-06-01 WO PCT/JP2016/066151 patent/WO2017061139A1/ja active Application Filing
- 2016-06-01 JP JP2017544382A patent/JP6503470B2/ja active Active
- 2016-12-28 JP JP2018520341A patent/JP6542990B2/ja active Active
- 2016-12-28 WO PCT/JP2016/089129 patent/WO2017208486A1/ja active Application Filing
-
2017
- 2017-07-20 US US15/655,168 patent/US10217865B2/en active Active
- 2017-12-21 WO PCT/JP2017/046000 patent/WO2018123823A1/ja active Application Filing
- 2017-12-21 JP JP2018559129A patent/JP6793409B2/ja active Active
-
2018
- 2018-11-29 US US16/203,982 patent/US10651180B2/en active Active
-
2019
- 2019-01-03 US US16/238,816 patent/US10734391B2/en active Active
- 2019-04-02 US US16/372,717 patent/US10651181B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US10217865B2 (en) | 2019-02-26 |
WO2018123823A1 (ja) | 2018-07-05 |
WO2016163045A1 (ja) | 2016-10-13 |
JPWO2017208486A1 (ja) | 2018-08-30 |
JP6503470B2 (ja) | 2019-04-17 |
WO2017208486A1 (ja) | 2017-12-07 |
US20190237367A1 (en) | 2019-08-01 |
US20190252392A1 (en) | 2019-08-15 |
US10651180B2 (en) | 2020-05-12 |
WO2017061139A1 (ja) | 2017-04-13 |
JPWO2017061139A1 (ja) | 2017-11-16 |
JP6378826B2 (ja) | 2018-08-22 |
JPWO2016163045A1 (ja) | 2017-09-28 |
US20170323969A1 (en) | 2017-11-09 |
US10651181B2 (en) | 2020-05-12 |
US10734391B2 (en) | 2020-08-04 |
JPWO2018123823A1 (ja) | 2019-07-18 |
US20190109140A1 (en) | 2019-04-11 |
JP6793409B2 (ja) | 2020-12-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6542990B2 (ja) | 柱状半導体装置の製造方法 | |
JP6104477B2 (ja) | 柱状半導体メモリ装置と、その製造方法 | |
JP5639317B1 (ja) | Sgtを有する半導体装置と、その製造方法 | |
JP6175196B2 (ja) | 柱状半導体メモリ装置と、その製造方法 | |
JP6651657B2 (ja) | 柱状半導体装置と、その製造方法 | |
JP6367495B2 (ja) | 柱状半導体装置とその製造方法 | |
JP5639318B1 (ja) | Sgtを有する半導体装置の製造方法 | |
US10229916B2 (en) | Method for producing pillar-shaped semiconductor device | |
WO2021005842A1 (ja) | 柱状半導体装置と、その製造方法 | |
US10410932B2 (en) | Method for producing pillar-shaped semiconductor device | |
JP2006261421A (ja) | 半導体装置 | |
WO2021176693A1 (ja) | 柱状半導体装置とその製造方法 | |
JPWO2021176693A5 (ja) | ||
WO2023017618A1 (ja) | 柱状半導体の製造方法 | |
TWI815229B (zh) | 柱狀半導體記憶裝置及其製造方法 | |
CN110366775B (zh) | 柱状半导体装置的制造方法 | |
WO2022113187A1 (ja) | 柱状半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination | ||
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20181113 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20190604 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20190613 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6542990 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |