JPWO2018123823A1 - 柱状半導体装置の製造方法 - Google Patents
柱状半導体装置の製造方法 Download PDFInfo
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- JPWO2018123823A1 JPWO2018123823A1 JP2018559129A JP2018559129A JPWO2018123823A1 JP WO2018123823 A1 JPWO2018123823 A1 JP WO2018123823A1 JP 2018559129 A JP2018559129 A JP 2018559129A JP 2018559129 A JP2018559129 A JP 2018559129A JP WO2018123823 A1 JPWO2018123823 A1 JP WO2018123823A1
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Abstract
Description
基板と、前記基板上に対して垂直方向に延在する第1の半導体柱を形成する工程と、
前記第1の半導体柱の外周を囲む第1のゲート絶縁層を形成する工程と、
前記ゲート絶縁層を囲む第1のゲート導体層を形成する工程と、
垂直方向において、前記第1のゲート絶縁層の下端に、その上端位置がある、前記第1の半導体柱の内部、又はその側面に接した第1の不純物領域を形成する工程と、
前記垂直方向において前記第1のゲート導体層の上端以上で、且つ前記半導体柱の頂部以下の高さに上面位置を有する第1の絶縁層を形成する工程と、
前記第1の絶縁層の上表面より上で露出している前記半導体柱の上部の側面を囲んで第1の材料層を形成する工程と、
前記第1の材料層をマスクに前記第1の半導体柱の頂部をエッチングして、凹部を形成する工程と、
前記凹部に、ドナーまたはアクセプタ不純物を含む第2の不純物領域をエピタキシャル結晶成長させて形成する工程と、
前記第1の材料層を除去する工程と、
前記第1の絶縁層より上部の前記第2の不純物領域の側面を、平面視において等幅で囲んだ第2の材料層を形成する工程と、
前記第2の材料層の外周部に第3の材料層を形成する工程と、
前記第3の材料層と、前記第2の不純物領域と、をエッチングマスクにして、前記第2の材料層をエッチングして前記第1の絶縁層を底部にした第1のコンタクトホールを形成する工程と、
前記第1のコンタクトホールに単層又は、複数層よりなる導電性を有する第1の導体材料層を埋め込む工程と、を備える、
ことを特徴とする。
前記第1のコンタクトホールを埋めて、前記第2の不純物領域との側面と、上表面とを覆って、単層又は、複数層よりなる導電性を有する第2の導体材料層を形成する工程と、を備える、
ことがさらに好ましい。
前記第3の導体材料層の上表面位置が、前記第2の材料層の上表面位置になるように研磨する工程と、
前記第3の導体材料層に接続して、第1の配線導体層を形成する工程と、を備える、
ことがさらに好ましい。
ことがさらに好ましい。
ことがさらに好ましい。
前記第5の導体材料層上に、第2の配線導体層を形成する工程と、を備える、
ことがさらに好ましい。
前記第1の半導体柱の下方に、前記第2の絶縁層と、前記ゲート導体層と、前記ゲート絶縁層と、を貫通した開口部を形成する工程と、
前記開口部に面した、前記ゲート導体層の端面を覆った第3の絶縁層を形成する工程と、
前記開口部の前記第1の半導体柱の側面に接して、水平方向に伸延するドナー、またはアクセプタ不純物を含んだ前記第1の不純物領域を選択エピタキシャル結晶成長により形成する工程を、を備える、
ことがさらに好ましい。
ことがさらに好ましい。
ことがさらに好ましい。
前記第2の半導体柱上に前記第2の不純物領域と同じ工程を用いて、ドナーまたはアクセプタ不純物を含み、エピタキシャル結晶成長させて第3の不純物領域を形成する工程と、
前記第1の半導体柱の下方にあり、且つ前記第1の半導体柱内または、側面に繋がった第4の不純物領域、を形成する工程と、
前記第2の半導体柱の下方にあり、且つ前記第2の半導体柱内または、側面に繋がった第5の不純物領域、を形成する工程と、
前記第1のゲート導体層、前記第2のゲート導体層、前記第1の不純物領域、前記第3の不純物領域、前記第4の不純物領域、及び前記第5の不純物領域から選ばれる異なる部位にそれぞれ接続され、前記基板に水平に延在し、平面視において互いに少なくとも部分的に重なり、且つ上から下にこの順番で存在する第2の配線導体層、第3の配線導体層、及び第4の配線導体層を含む積層構造体を提供する工程と、
前記第3の材料層の上表面から前記第4の配線導体層の上表面又は内部までつづき、前記第2の配線導体層及び前記第3の配線導体層を貫通する第2のコンタクトホールを形成する工程と、
前記第2のコンタクトホールに露出した前記第3の配線導体層の側面に第1の管状絶縁層を形成する工程と、
前記第2のコンタクトホールを充満して導電性を有する第6の導体材料層を形成する工程と、
前記第6の導体材料層の上部の側面を露出させる工程と、
前記第2の材料層を形成する工程は、前記第6の導体材料層の側面を囲んで第4の材料層を形成する工程を含み、
前記第3の材料層を形成する工程は、前記第4の材料層を囲んで第5の材料層を形成する工程を含み、そして、
前記第5の材料層をエッチングマスクにして、前記第4の材料層をエッチングして、前記第2の導体材料層上面に繋がる第3のコンタクトホールを形成する工程と、
前記第3のコンタクトホールに導電性を有する第7の導体材料層を形成す工程と、をさらに備える、
ことがさらに好ましい。
第8の導体材料層を前記第4のコンタクトホールに充満する工程と、
をさらに備える、
ことがさらに好ましい。
ことがさらに好ましい。
ことがさらに好ましい。
基板と、前記基板上に対して垂直方向に延在する第1の半導体柱を形成する工程と、
前記第1の半導体柱の外周を囲む第1のゲート絶縁層を形成する工程と、
前記第1のゲート絶縁層を囲む第1のゲート導体層を形成する工程と、
前記基板に対する垂直方向において、前記第1のゲート絶縁層の下端に、その上端位置がある、前記第1の半導体柱の内部、又はその側面に接した第1の不純物領域を形成する工程と、
前記垂直方向において前記第1のゲート導体層の上端以上で、且つ前記第1の半導体柱の頂部以下の高さに上面位置を有する第1の絶縁層を形成する工程と、
前記第1の絶縁層の上表面より上で露出している前記第1の半導体柱の上部の側面を平面視において等幅に囲んで第1の材料層を形成する工程と、
前記第1の材料層を囲んで第2の材料層を形成する工程と、
前記第1の材料層と、前記第2の材料層と、をマスクに前記半導体柱の頂部をエッチングして、凹部を形成する工程と、
前記凹部に、ドナーまたはアクセプタ不純物を含む第1の不純物領域をエピタキシャル結晶成長させて形成する工程と、
前記第1の材料層をエッチングして、前記第2の材料層と、前記第2の不純物領域の間にあり、且つ前記第1の絶縁層を底部にした第1のコンタクトホールを形成する工程と、
前記第1のコンタクトホールに単層又は、複数層よりなる導電性を有する第1の導体材料層を埋め込む工程と、を備える、
ことを特徴とする。
前記第1のコンタクトホールを埋めて、前記第2の不純物領域との側面と、上表面とを覆って、単層又は、複数層よりなる導電性を有する第2の導体材料層を形成する工程と、を備える、
ことがさらに好ましい。
前記第3の導体材料層の上表面位置が、前記第2の材料層の上表面位置になるように研磨する工程と、
前記第3の導体材料層に接続して、第1の配線導体層を形成する工程と、を備える、
ことがさらに好ましい。
ことがさらに好ましい。
ことがさらに好ましい。
前記第5の導体材料層上に、第2の配線導体層を形成する工程と、を備える、
ことがさらに好ましい。
前記第1の半導体柱の下方に、前記第2の絶縁層と、前記ゲート導体層と、前記ゲート絶縁層と、を貫通した開口部を形成する工程と、
前記開口部に面した、前記ゲート導体層の端面を覆った第3の絶縁層を形成する工程と、
前記開口部の前記第1の半導体柱の側面に接して、水平方向に伸延するドナー、またはアクセプタ不純物を含んだ第1の不純物領域を選択エピタキシャル結晶成長により形成する工程を、を備える、
ことがさらに好ましい。
ことがさらに好ましい。
ことがさらに好ましい。
前記第2の半導体柱上に前記第2の不純物領域と同じ工程を用いて、ドナーまたはアクセプタ不純物を含み、エピタキシャル結晶成長させて第3の不純物領域を形成する工程と、
前記第1の半導体柱の下方にあり、且つ前記第1の半導体柱内または、側面に繋がった第4の不純物領域、を形成する工程と、
前記第2の半導体柱の下方にあり、且つ前記第2の半導体柱内または、側面に繋がった第5の不純物領域、を形成する工程と、
前記第1のゲート導体層、前記第2のゲート導体層、前記第1の不純物領域、前記第3の不純物領域、前記第4の不純物領域、及び前記第5の不純物領域から選ばれる異なる部位にそれぞれ接続され、前記基板に水平に延在し、平面視において互いに少なくとも部分的に重なり、且つ上から下にこの順番で存在する第2の配線導体層、第3の配線導体層、及び第4の配線導体層を含む積層構造体を提供する工程と、
前記第2の材料層の上表面から前記第4の配線導体層の上表面又は内部までつづき、前記第2の配線導体層及び前記第3の配線導体層を貫通する第2のコンタクトホールを形成する工程と、
前記第2のコンタクトホールに露出した前記第3の配線導体層の側面に第1の管状絶縁層を形成する工程と、
前記第2のコンタクトホールを充満して導電性を有する第6の導体材料層を形成する工程と、
前記第6の導体材料層の上部の側面を露出させる工程と、
前記第1の材料層を形成する工程は、前記第6の導体材料層の側面を囲んで第3の材料層を形成する工程を含み、
前記第2の材料層を形成する工程は、前記第3の材料層を囲んで第4の材料層を形成する工程を含み、そして、
前記第4の材料層をエッチングマスクにして、前記第3の材料層をエッチングして、前記第2の導体材料層と前記第6の導体材料層の上面に繋がる第3のコンタクトホールを形成する工程と、
前記第3のコンタクトホールに導電性を有する第7の導体材料層を形成す工程と、をさらに備える、
ことがさらに好ましい。
第8の導体材料層を前記第4のコンタクトホールに充満する工程と、
をさらに備える、
ことがさらに好ましい。
ことがさらに好ましい。
以下、図1A、図1B、図2A〜図2Zを参照しながら、本発明の第1実施形態に係る、SGTを有する柱状半導体装置の製造方法について説明する。
Si柱SP1には、図1AにおけるPチャネル型SGT_Pc1が上部に形成され、Pチャネル型SGT_Pc2が下部に形成されている。Pチャネル型SGT_Pc1、Pc2はSi柱SP1の中間にあるSiO2層Ox1で分離されている。Pチャネル型SGT_Pc1は、チャネルであるSi柱SP1の一部と、このSi柱SP1の一部を囲むゲートGp1と、ゲートGp1の上下のSi柱SP1内にあるドレインP+層Pd1とソースP+層Ps1とより形成されている。Pチャネル型SGT_Pc2は、チャネルであるSi柱SP1の一部と、このSi柱SP1の一部を囲むゲートGp2と、ゲートGp2の上下のSi柱SP1内にあるドレインP+層Pd2とソースP+層Ps2とより形成されている。
Si柱SP2には、図1AにおけるNチャネル型SGT_Nc1が上部に形成され、Nチャネル型SGT_Nc2が下部に形成されている。Nチャネル型SGT_Nc1、Nc2はSi柱SP2の中間にあるSiO2層Ox2で分離されている。Nチャネル型SGT_Nc1は、チャネルであるSi柱SP2の一部と、このSi柱SP2の一部を囲むゲートGn1と、ゲートGn1の上下のSi柱SP2内にあるドレインN+層Nd1とソースN+層Ns1とより形成されている。Nチャネル型SGT_Nc2は、チャネルであるSi柱SP2の一部と、このSi柱SP2の一部を囲むゲートGn2と、ゲートGn2の上下のSi柱SP2内にあるドレインN+層Nd2とソースN+層Ns2とより形成されている。
Si柱SP3には、図1AにおけるNチャネル型SGT_SN1が上部に形成され、Nチャネル型SGT_SN2が下部に形成されている。Nチャネル型SGT_SN1、SN2はSi柱SP3の中間にあるSiO2層Ox3で分離されている。Nチャネル型SGT_SN1は、チャネルであるSi柱SP3の一部と、このSi柱SP3の一部を囲むゲートGs1と、ゲートGs1の上下のSi柱SP3内にあるドレインN+層Sd1とソースN+層Ss1とより形成されている。Nチャネル型SGT_SN2は、チャネルであるSi柱SP3の一部と、このSi柱SP3の一部を囲むゲートGs2と、ゲートGs2の上下のSi柱SP3内にあるドレインN+層Sd2とソースN+層Ss2とより形成されている。
次に、リソグラフィ法とRIE法を用いて、下層に残存するi層2をエッチングして、Si柱6aの外周部にi層2a1を、Si柱6bの外周部にi層2a2を、Si柱6cの外周部にi層2a3を形成する。
また、Si柱6bの上部に、N+層33b、38bをソース、ドレインとし、TiN層18dをゲートとし、N+層33b、38b間のSi柱6bをチャネルにしたSGT(図1BのNチャネル型SGT_Nc1に対応する)が形成され、Si柱6bの下部に、N+層8bb、31bをソース、ドレインとし、TiN層18aをゲートとし、N+層8bb、31b間のSi柱6aをチャネルにしたSGT(図1BのNチャネル型SGT_Nc2に対応する)が、形成される。
また、Si柱6cの上部に、N+層33c、38cをソース、ドレインとし、TiN層18eをゲートとし、N+層33c、38c間のSi柱6cをチャネルにしたSGT(図1BのNチャネル型SGT_SN1に対応する)が形成され、Si柱6cの下部に、N+層8cc、31cをソース、ドレインとし、TiN層18bをゲートとし、N+層8cc、31c間のSi柱6cをチャネルにしたSGT(図1BのNチャネル型SGT_Nc2に対応する)が、形成される。
これらSGT(図1BのSGT_Pc1、Pc2、Nc1、Nc2、SN1、SN2に対応する)が接続配線されて、図1Bに示した模式構造図と同じく、Si柱6a、6b、6cの上部に形成されたPチャネル型SGT(図1BのPチャネル型SGT_Pc1に対応する)及びNチャネル型SGT(図1BのNチャネル型SGT_Nc1、SN1に対応する)による回路領域(図1Bの回路領域C1に対応する)と、Si柱6a、6b、6cの下部に形成されたPチャネル型SGT(図1BのPチャネル型SGT_Pc2に対応する)及びNチャネル型SGT(図1BのNチャネル型SGT_Nc2、SN2に対応する)による回路領域(図1Bの回路領域C2に対応する)と、により構成されたSRAMセル回路が形成される。
1.図2N〜図2Qに示したように、高濃度にアクセプタ、そしてドナー不純物を含んだP+層38a、N+層38b、38cが、Si柱6a、6b、6cの頂部をエッチングして形成した凹部38AA,38BB,38CC底部にあるSi柱6a、6b、6c上にエピタキシャル結晶成長して形成された。この方法は、例えば、P+層38a、N+層38b、38cをイオン注入法により形成した場合と比べて、アクセプタ、そしてドナー不純物をより高濃度に含ませることが出来、かつP+層38a、N+層38b、38cとSi柱6a、6b、6cの境界での不純物濃度分布を急峻にできる特徴を得ることができる。この2つの特徴共に、P+層38a、N+層38b、38cのダイオード接合抵抗を小さくすることができる。これは、SGT回路の低電圧駆動化と高速化に寄与できる。
2.更に、図2Zに示されるように、P+層38a、N+層38b、38cは、側面を低抵抗金属層であるW層52c、52d、52eで囲まれている。W層52c、52d、52e(バリヤ金属層を含む)の底部位置は、P+層38a、N+層38b、38cの下端に近い位置に形成されている。これにより、P+層38a、N+層38b、38cによるダイオード接合抵抗を低くできる。これは、SGT回路の更なる低電圧駆動化と高速化に寄与できる。
3.P+層38a、N+層38b、38cが、Si柱6a、6b、6cに対して自己整合で形成されている。そして、W層52a、52b、52c、52d、52eが、W層43a、43b、P+層38a、N+層38b、38cに対して自己整合で形成されている。これにより、Si柱6a、6b、6cと、P+層38a、N+層38b、38cと、W層52c、52d、52cの3者が自己整合の関係で形成され、W層43a、43bとW層52a、52bが自己整合の関係で形成される。これにより、低電圧駆動化と高速化に加えて、SGT回路の更なる高密度が図れる。
以下、図3A〜図3Cを参照しながら、本発明の第2実施形態に係る、SGTを有する柱状半導体装置の製造方法について説明する。(a)は平面図、(b)は(a)のX−X’線に沿う断面構造図、(c)は(a)のY1−Y1’線に沿う断面構造図、(d)は(a)のY2−Y2’線に沿う断面構造図である。第2実施形態の製造方法は、以下に説明する相違点を除き、第1実施形態の図2A〜図2Zに示す工程と同様である。
第1実施形態では、P+層38a、N+層38b、38cの頂部にNiSi層67a、67b、67cを形成した。 これらNiSi層67a、67b、67cは、P+層38a、N+層38b、38cの上面にNi層を被覆した後に、熱処理を行い、P+層38a、N+層38b、38cの頂部のシリサド化を行うことにより形成させる。このシリサイド化によるNiSi層67a、67b、67cの形成では、NiSi層67a、67b、67cとP+層38a、N+層38b、38cとの間でNi原子とSi原子の組成比の異なる領域で抵抗に高いシリサイド領域が形成される。これは、NiSi層の中で、抵抗の低いのはNi原子1個に対してSi原子2個の割合で形成されているNiSi2層であるが、NiSi層67a、67b、67cとP+層38a、N+層38b、38cの境界付近で、この割合がずれてくる領域が長くなることによる。このことは、通常のSGTを用いた回路形成においては、問題ではないが、更なるSGT回路の高速化、低電圧化を行う場合において問題になる。これに対して、本実施形態では、直接に抵抗の低いW層72a、72b、72c(バッファ金属層を含む)を、P+層38A、N+層38B、38Cの側面と上面の全体を覆って形成される。これによって、さらにP+層38A、N+層38B、38CのダイオードPN接合抵抗を小さく出来て、SGT回路の低電圧駆動化と高速化が図れる。
以下、図4A、図4Bを参照しながら、本発明の第3実施形態に係る、SGTを有する柱状半導体装置の製造方法について説明する。(a)は平面図、(b)は(a)のX−X’線に沿う断面構造図、(c)は(a)のY1−Y1’線に沿う断面構造図、(d)は(a)のY2−Y2’線に沿う断面構造図である。
第1実施形態では、P+層38a、N+層38b、38c、W層43a、43bの側面を囲んで、W層52a、52b、52c、52d、52eが形成されている。この場合、W層52c、52d、52eと、P+層38a、N+層38b、38cとの接触抵抗を下げるための、例えば、Ti層、TiN層などのバッファ金属層を、W層52c、52d、52eとP+層38a、N+層38b、38cとの間に確実に設けようとすると、平面視において、図2Uに示したコンタクトホール50c、50d、50eの幅を大きくしなければいけない。これに対して、本実施形態では、コンタクトホール50c、50d、50e内には、バッファ金属層のみを形成している。このため、コンタクトホール50c、50d、50e内にはW層を形成する必要がない。これにより、平面視において、コンタクトホール50c、50d、50eの幅を狭くすることができる。これにより、SGT回路の高密度化が図れる。
以下、図5を参照しながら、本発明の第4実施形態に係る、SGTを有する柱状半導体装置の製造方法について説明する。(a)は平面図、(b)は(a)のX−X’線に沿う断面構造図、(c)は(a)のY1−Y1’線に沿う断面構造図、(d)は(a)のY2−Y2’線に沿う断面構造図である。
1. 第3実施形態では、全体を覆ってW層(図示せず)を被覆した後、リソグラフィ法とRIEエッチングにより、図4Bに示すように、バッファ金属層74a、74b、74c、75a、75b上とW層43a、43b上にW層76a、76b、76c、77a、77bを形成した。これに対して、本実施形態では、リソグラフィ法とRIEエッチング工程を用いないで、W層76a、76b、76c、77a、77bと同じように、W層78a、78b、78c、79a、79bを形成することができる。且つ、W層78a、78b、78c、79a、79bは、バッファ金属層74a、74b、74c、75a、75bと、及びW層43a、43bと、に対して自己整合で形成される。これにより、SGT回路の高密度化が図れると共に、製造工程の簡易化が図れる。
以下、図6を参照しながら、本発明の第5実施形態に係る、SGTを有する柱状半導体装置の製造方法について説明する。(a)は平面図、(b)は(a)のX−X’線に沿う断面構造図、(c)は(a)のY1−Y1’線に沿う断面構造図、(d)は(a)のY2−Y2’線に沿う断面構造図である。
第3実施形態では、P+層38a、N+層38b、38c、の頂部をエッチングして形成された、P+層38A、N+層38B、38Cの側面に接したSiO2層46c、46d、46eをエッチングして除去した。そして、バッファ導体層74a、74b、74cを、P+層38A、N+層38B、38Cの側面と頂部上とを囲んで形成した。これに対して、本実施形態では、P+層38a、N+層38b、38cの頂部のエッチングを行わないで、バッファ導体層81c、81d、81eを、P+層38a、N+層38b、38cの側面と頂部上との全体を囲んで形成できる。これにより、SGT回路の高密度化が図れると共に、製造工程の簡易化が図れる。
以下、図7A、図7Bを参照しながら、本発明の第6実施形態に係る、SGTを有する柱状半導体装置の製造方法について説明する。(a)は平面図、(b)は(a)のX−X’線に沿う断面構造図、(c)は(a)のY−Y’線に沿う断面構造図である。
1.Si柱85の下部側面に繋がった、P+層96も、上部のP+層105と同様に、高濃度のアクセプタ不純物を含んだSiのエピタキシャル結晶成長法により形成される。これにより、SGTのソース、およびドレインとなる不純物領域の両者が、イオン注入法により形成した場合と比べて、アクセプタ、そしてドナー不純物をより高濃度に含ませることが出来、かつP+層96とSi柱85の境界での不純物濃度分布を急峻にできる。これにより、P+層96、105のダイオード接合抵抗を小さくすることができる。これは、SGT回路の更なる低電圧駆動化と高速化に寄与できる。
2.Siを母体にしたP+層96、105に替えて、例えばシリコン・ゲルマニウム(SiGe)を母体にして、P+層96、105を形成することができる。 P+層96、105にSiGeを用いることによりチャネルであるSi柱85内に生じる応力によりホール移動度が向上できる。これにより、更なる回路の高速化が図れる。
3.P+層96、105は、それぞれ独立にエピタキシャル結晶成長法により半導体層を形成できる。従って、P+層96と、P+層105とを異なる半導体原子を母体として形成することは容易に出来る。これにより、更にSGTの特性向上を図ることが可能である。
以下、図8を参照しながら、本発明の第7実施形態に係る、SGTを有する柱状半導体装置の製造方法について説明する。(a)は平面図、(b)は(a)のX−X’線に沿う断面構造図、(c)は(a)のY−Y’線に沿う断面構造図である。
1. 平面視において、P+層96aが、チャネル部分のSi柱85外周より、内側になるため、図7Bと比べてチャネル内に均一な電界分布が形成される。これはSGTの低電圧駆動において望ましい。
例えば、SiGeを母体にしてP+層96a、105を形成した場合、チャネルSi柱85内にホール移動度を高める応力を形成しやすくなる。これにより、SGTの高性能化が図れる。
以下、図9A〜図9Dを参照しながら、本発明の第8実施形態に係る、SGTを有する柱状半導体装置の製造方法について説明する。(a)は平面図、(b)は(a)のX−X’線に沿う断面構造図、(c)は(a)のY−Y’線に沿う断面構造図である。 そして、図9A(d)は、図9A(d)のY2−Y2’線に沿った断面構造図である。
1. 第1実施形態では、エピタキシャル結晶成長によるP+層38a、N+層38b、38cを形成した後に、自己整合コンタクトホール50a〜50eを形成するため、P+層38a、N+層38b、38cの側面と、W層43a、43bの頂部の側面と、を等幅で囲んだSiO2層46a〜46eを形成し、そしてSiO2層46a〜46eを囲んでAlO層51を形成した。これに対して、本実施形態では、エピタキシャル結晶成長によるP+層116a、N+層116b、116cを形成する前に、ドナー、又はアクセプタ不純物をドープしていないSi柱6a、6b、6cとW層43a、43bの頂部の側面を等幅で囲んだSiO2層111a〜111eを形成し、SiO2層111a〜111eを囲んだAlO層110と、を形成する。その後に、SiO2層111a〜111eをエッチングすることにより、自己整合コンタクトホール(図示せず)が形成される。このように、Si柱6a、6b、6cとW層43a、43bの頂部の側面を等幅で囲んだSiO2層111a〜111eは、凹部115a、115b、115cを形成するためのエッチングマスクの役割と、自己整合コンタクトホール形成の役割を行う。これにより、本実施形態の工程は、第1実施形態の工程より簡略にできる。
2. 本実施形態では、P+層116a、N+層116b、116cと、自己整合コンタクトホール(図示せず)とが、第1実施形態におけるP+層38a、N+層38b、38cと、自己整合コンタクトホール50a〜50eは、同じ形状に形成される。P+層38a、N+層38b、38cと、自己整合コンタクトホール50a〜50e形成の後の製造方法に係る第2実施形態〜第5実施形態と、P+層38a、N+層38b、38cと、自己整合コンタクトホール50a〜50e形成の前の製造方法に係る第6実施形態と、第7実施形態には、本実施形態は直接適用することが出来る。これにより、第2実施形態〜第7実施形態の回路形成工程の簡略化が図れる。
3.本実施形態では、図9Aにおいて、Si柱6a、6b、6cの頂部上に、図2Lで示したSiO2層5a、5b、5cを残存させた状態で、Si柱6a、6b、6cの頂部と、SiO2層5a、5b、5cと、の側面を囲んで、SiO2層111c,111d,111eとAlO層110を形成することができる。その後に、SiO2層5a、5b、5cとSiO2層111c,111d,111eとをエッチングして除去すると、第2実施形態と同じように、P+層116a、N+層116b、116cの頂部上面位置をAlO層110の上表面位置より低くすることができる。これによって、第2実施形態と同様に、さらにP+層116a、N+層116b、116cのダイオードPN接合抵抗を小さく出来て、SGT回路の低電圧駆動化と高速化が図れる。
Nc1、Nc2、Nc3、Nc4、SN1、SN2 Nチャネル型SGT
BLt ビット線端子
BLRt 反転ビット線端子
WLt ワード線端子
Vss グランド端子
Vdd 電源端子
C1、C2 回路領域
Gp1、Gp2、Gn1、Gn2、Gs1、Gs2 ゲート
1 SiO2層基板
2、2a1、2a2、2a3、2b1、2b2、2b3、4、4a、4b、4c i層
Ns1、Ns2、Nd1、Nd2、Sd1、Sd2、NS1、ND、Ss1、SD1、SD2、Ss2、8b、8c、8bb、8cc、31b、31c、33b、33c、38b、38c、38B、38C N+層
8a、8aa、31a、33a、38a、38A、96、96a、105 P+層
Ox1、Ox2、Ox3、3、3a、3b、3c、5、5a、5b、5c、7a、7b、7c、10、14、14a、14b、14c、14d、23a、23b、23aa、23bb、35b、35d、35e、35f、37、39b、41a、41b、46a、46b、46c、46d、46e、54、56、58、90、93、93a、101、103 SiO2層
SP1、SP2、SP3、6a、6b、6c、85 Si柱
11、11a、11b、11c、11d、91、91a HfO2層
12、12a、12b、18a、18b、18c、18d、18e、92、92a TiN層
15、35a、35c、39a、89、102 SiN層
51、71、103 AlO層
16、27、37a、37b、 レジスト層
20a、20b、20c、20d、20e、20f TiO層
21a、21b Ni層
22a、22b P型ポリSi層
26a、26b N+型ポリSi層
25a、25b、25c 空間
19a、19b、19c、94 開口部
38AA、38BB、38CC 凹部
28a、28b、28aa、28bb、30a、30b、30c、32a、32b、32c、36a、36b、62a、67a、67b、67c、67d、67e NiSi層
40a、40b、50a、50b、50c、50d、50e、50aa、50bb、55a、55b、55c、55d、57、60a、60b、108a、108b コンタクトホール
43a、43b、52a、52b、52c、52d、52e、70a、72a、72b、72c、73a、73b、76a、76b、76c、77a、77b、78a、78b、78c、79a、79b、82a、82b、82c、82d、82e、98、100、106 W層
74a、74b、74c、75a、75b、81a、81b、81c、81d、81e バッファ導体層
86 P層
87 N層
95 絶縁層
VDD 電源配線金属層
VSS グランド配線金属層
WL ワード線配線金属層
BL ビット線配線金属層
BLR 反転ビット線配線金属層
M1,M2、MG 配線金属層
Claims (24)
- 基板と、
前記基板上に対して垂直方向に延在する第1の半導体柱を形成する工程と、
前記第1の半導体柱の外周を囲む第1のゲート絶縁層を形成する工程と、
前記第1のゲート絶縁層を囲む第1のゲート導体層を形成する工程と、
垂直方向において、前記第1のゲート絶縁層の下端に、その上端位置がある、前記第1の半導体柱の内部、又はその側面に接した第1の不純物領域を形成する工程と、
前記垂直方向において前記第1のゲート導体層の上端以上で、且つ前記第1の半導体柱の頂部以下の高さに上面位置を有する第1の絶縁層を形成する工程と、
前記第1の絶縁層の上表面より上で露出している前記第1の半導体柱の上部の側面を囲んで第1の材料層を形成する工程と、
前記第1の材料層をマスクに前記第1の半導体柱の頂部をエッチングして、凹部を形成する工程と、
前記凹部に、ドナーまたはアクセプタ不純物を含む第2の不純物領域をエピタキシャル結晶成長させて形成する工程と、
前記第1の材料層を除去する工程と、
前記第1の絶縁層より上部の前記第2の不純物領域の側面を、平面視において等幅で囲んだ第2の材料層を形成する工程と、
前記第2の材料層の外周部に第3の材料層を形成する工程と、
前記第3の材料層と、前記第2の不純物領域と、をエッチングマスクにして、前記第2の材料層をエッチングして前記第1の絶縁層を底部にした第1のコンタクトホールを形成する工程と、
前記第1のコンタクトホールに単層又は、複数層よりなる導電性を有する第1の導体材料層を埋め込む工程と、を備える、
ことを特徴とする柱状半導体装置の製造方法。 - 前記第2の不純物領域の上表面位置を前記第2の材料層の上表面位置より低く形成する工程と、
前記第1のコンタクトホールを埋めて、前記第2の不純物領域との側面と、上表面とを覆って、単層又は、複数層よりなる導電性を有する第2の導体材料層を形成する工程と、を備える、
ことを特徴とする請求項1に記載の柱状半導体装置の製造方法。 - 前記第1のコンタクトホールを埋めて、前記第2の不純物領域との側面と、上表面と、前記第3の材料層の上表面を覆って、単層又は、複数層よりなる導電性を有する第3の導体材料層を形成する工程と、
前記第3の導体材料層の上表面位置が、前記第2の材料層の上表面位置になるように研磨する工程と、
前記第3の導体材料層に接続して、第1の配線導体層を形成する工程と、を備える、
ことを特徴とする請求項1に記載の柱状半導体装置の製造方法。 - 前記第2の導体材料層上に、選択成長により、第4の導体材料層を形成する工程、を備える、
ことを特徴とする請求項2に記載の柱状半導体装置の製造方法。 - 前記第2の導体材料層を選択成長により形成する工程、を備える、
ことを特徴とする請求項2に記載の柱状半導体装置の製造方法。 - 前記第1のコンタクトホールを埋めて、前記第2の不純物領域との側面と、上表面と、上表面位置が前記第3の材料層の上表面より高い、単層又は、複数層よりなる導電性を有する第5の導体材料層を形成する工程と、
前記第5の導体材料層上に、第2の配線導体層を形成する工程と、を備える、
ことを特徴とする請求項1に記載の柱状半導体装置の製造方法。 - 前記第1のゲート導体層を囲んだ第2の絶縁層を形成する工程と、
前記第1の半導体柱の下方に、前記第2の絶縁層と、前記ゲート導体層と、前記ゲート絶縁層と、を貫通した開口部を形成する工程と、
前記開口部を形成する前、または後に、前記開口部に面して、少なくとも前記ゲート導体層の端面を覆った第3の絶縁層を形成する工程と、
前記開口部の前記第1の半導体柱の側面に接して、水平方向に伸延するドナー、またはアクセプタ不純物を含んだ前記第1の不純物領域を選択エピタキシャル結晶成長により形成する工程を、を備える、
ことを特徴とする請求項1に記載の柱状半導体装置の製造方法。 - 平面視において、前記第1の不純物領域の外周が、前記第2の絶縁層の外周より外側になるように、前記第1の不純物領域を形成する工程を、さらに備える、
ことを特徴とする請求項7に記載の柱状半導体装置の製造方法。 - 前記第1の不純物領域と、前記第2の不純物領域と、の一方または両方が、前記第1の半導体柱を構成している半導体母体と異なる半導体母体から形成されている、
ことを特徴とする請求項7に記載の柱状半導体装置の製造方法。 - 前記基板上に前記第1の半導体柱に隣接して立つ第2の半導体柱と、前記第2の半導体柱の外周を囲む第2のゲート絶縁層と、前記第2のゲート絶縁層を囲む第2のゲート導体層と、
前記第2の半導体柱上に前記第2の不純物領域と同じ工程を用いて、ドナーまたはアクセプタ不純物を含み、エピタキシャル結晶成長させて第3の不純物領域を形成する工程と、
前記第1の半導体柱の下方にあり、且つ前記第1の半導体柱内または、側面に繋がった第4の不純物領域、を形成する工程と、
前記第2の半導体柱の下方にあり、且つ前記第2の半導体柱内または、側面に繋がった第5の不純物領域、を形成する工程と、
前記第1のゲート導体層、前記第2のゲート導体層、前記第1の不純物領域、前記第3の不純物領域、前記第4の不純物領域、及び前記第5の不純物領域から選ばれる異なる部位にそれぞれ接続され、前記基板に水平に延在し、平面視において互いに少なくとも部分的に重なり、且つ上から下にこの順番で存在する第2の配線導体層、第3の配線導体層、及び第4の配線導体層を含む積層構造体を提供する工程と、
前記第3の材料層の上表面から前記第4の配線導体層の上表面又は内部までつづき、前記第2の配線導体層及び前記第3の配線導体層を貫通する第2のコンタクトホールを形成する工程と、
前記第2のコンタクトホールに露出した前記第3の配線導体層の側面に第1の管状絶縁層を形成する工程と、
前記第2のコンタクトホールを充満して導電性を有する第6の導体材料層を形成する工程と、
前記第6の導体材料層の上部の側面を露出させる工程と、
前記第2の材料層を形成する工程は、前記第6の導体材料層の側面を囲んで第4の材料層を形成する工程を含み、
前記第3の材料層を形成する工程は、前記第4の材料層を囲んで第5の材料層を形成する工程を含み、そして、
前記第5の材料層をエッチングマスクにして、前記第4の材料層をエッチングして、前記第2の導体材料層上面に繋がる第3のコンタクトホールを形成する工程と、
前記第3のコンタクトホールに導電性を有する第7の導体材料層を形成す工程と、をさらに備える、
ことを特徴とする請求項1に記載の柱状半導体装置の製造方法。 - 平面視において、前記第1のコンタクトホール、前記第2のコンタクトホール、前記第3のコンタクトホールの場所以外にあり、前記第1のゲート導体層、前記第2ゲート導体層、前記第4の不純物領域、前記第5の不純物領域のいずれかに接続され水平方向に延在する第5の配線導体層に繋がり、且つ前記第3の材料層の表面より下方に延びる第4のコンタクトホールを形成する工程と、
第8の導体材料層を前記第4のコンタクトホールに充満する工程と、
をさらに備える、
ことを特徴とする請求項10に記載の柱状半導体装置の製造方法。 - 平面視において、前記第2のコンタクトホールに面した前記第3の配線導体層の側面が、前記第2の配線導体層の側面より、外側になるように形成される、
ことを特徴とする請求項10に記載の柱状半導体装置の製造方法。 - 基板上に対して垂直方向に延在する第1の半導体柱を形成する工程と、
前記第1の半導体柱の外周を囲む第1のゲート絶縁層を形成する工程と、
前記第1のゲート絶縁層を囲む第1のゲート導体層を形成する工程と、
前記基板に対する垂直方向において、前記第1のゲート絶縁層の下端に、その上端位置がある、前記第1の半導体柱の内部、又はその側面に接した第1の不純物領域を形成する工程と、
前記垂直方向において前記第1のゲート導体層の上端以上で、且つ前記第1の半導体柱の頂部以下の高さに上面位置を有する第1の絶縁層を形成する工程と、
前記第1の絶縁層の上表面より上で露出している前記第1の半導体柱の上部の側面を平面視において等幅に囲んで第1の材料層を形成する工程と、
前記第1の材料層を囲んで第2の材料層を形成する工程と、
前記第1の材料層と、前記第2の材料層と、をマスクに前記半導体柱の頂部をエッチングして、凹部を形成する工程と、
前記凹部に、ドナーまたはアクセプタ不純物を含む第2の不純物領域をエピタキシャル結晶成長させて形成する工程と、
前記第1の材料層をエッチングして、前記第2の材料層と、前記第2の不純物領域の間にあり、且つ前記第1の絶縁層を底部にした第1のコンタクトホールを形成する工程と、
前記第1のコンタクトホールに単層又は、複数層よりなる導電性を有する第1の導体材料層を埋め込む工程と、を備える、
ことを特徴とする柱状半導体装置の製造方法。 - 前記第2の不純物領域の上表面位置を前記第1の材料層の上表面位置より低く形成する工程と、
前記第1のコンタクトホールを埋めて、前記第2の不純物領域との側面と、上表面とを覆って、単層又は、複数層よりなる導電性を有する第2の導体材料層を形成する工程と、を備える、
ことを特徴とする請求項13に記載の柱状半導体装置の製造方法。 - 前記第1のコンタクトホールを埋めて、前記第2の不純物領域との側面と、上表面と、前記第2の材料層の上表面を覆って、単層又は、複数層よりなる導電性を有する第3の導体材料層を形成する工程と、
前記第3の導体材料層の上表面位置が、前記第2の材料層の上表面位置になるように研磨する工程と、
前記第3の導体材料層に接続して、第1の配線導体層を形成する工程と、を備える、
ことを特徴とする請求項13に記載の柱状半導体装置の製造方法。 - 前記第2の導体材料層上に、選択成長により、第4の導体材料層を形成する工程、を備える、
ことを特徴とする請求項14に記載の柱状半導体装置の製造方法。 - 前記第2の導体材料層を選択成長により形成する工程、を備える、
ことを特徴とする請求項14に記載の柱状半導体装置の製造方法。 - 前記第1のコンタクトホールを埋めて、前記第2の不純物領域との側面と、上表面と、上表面位置が前記第2の材料層の上表面より高い、単層又は、複数層よりなる導電性を有する第5の導体材料層を形成する工程と、
前記第5の導体材料層上に、第2の配線導体層を形成する工程と、を備える、
ことを特徴とする請求項13に記載の柱状半導体装置の製造方法。 - 前記第1のゲート導体層を囲んだ第2の絶縁層を形成する工程と、
前記第1の半導体柱の下方に、前記第2の絶縁層と、前記ゲート導体層と、前記ゲート絶縁層と、を貫通した開口部を形成する工程と、
前記開口部を形成する前、または後に、少なくとも前記ゲート導体層の端面を覆った第3の絶縁層を形成する工程と、
前記開口部の前記第1の半導体柱の側面に接して、水平方向に伸延するドナー、またはアクセプタ不純物を含んだ第1の不純物領域を選択エピタキシャル結晶成長により形成する工程を、を備える、
ことを特徴とする請求項13に記載の柱状半導体装置の製造方法。 - 平面視において、前記第1の不純物領域の外周が、前記第2の絶縁層の外周より外側になるように、前記第1の不純物領域を形成する工程を、さらに備える、
ことを特徴とする請求項19に記載の柱状半導体装置の製造方法。 - 前記第1の不純物領域と、前記第2の不純物領域と、の一方または両方が、前記第1の半導体柱を構成している半導体母体と異なる半導体母体から形成されている、
ことを特徴とする請求項19に記載の柱状半導体装置の製造方法。 - 前記基板上に前記第1の半導体柱に隣接して立つ第2の半導体柱と、前記第2の半導体柱の外周を囲む第2のゲート絶縁層と、前記第2のゲート絶縁層を囲む第2のゲート導体層と、
前記第2の半導体柱上に前記第2の不純物領域と同じ工程を用いて、ドナーまたはアクセプタ不純物を含み、エピタキシャル結晶成長させて第3の不純物領域を形成する工程と、
前記第1の半導体柱の下方にあり、且つ前記第1の半導体柱内または、側面に繋がった第4の不純物領域、を形成する工程と、
前記第2の半導体柱の下方にあり、且つ前記第2の半導体柱内または、側面に繋がった第5の不純物領域、を形成する工程と、
前記第1のゲート導体層、前記第2のゲート導体層、前記第2の不純物領域、前記第3の不純物領域、前記第4の不純物領域、及び前記第5の不純物領域から選ばれる異なる部位にそれぞれ接続され、前記基板に水平に延在し、平面視において互いに少なくとも部分的に重なり、且つ上から下にこの順番で存在する第2の配線導体層、第3の配線導体層、及び第4の配線導体層を含む積層構造体を提供する工程と、
前記第2の材料層の上表面から前記第4の配線導体層の上表面又は内部までつづき、前記第2の配線導体層及び前記第3の配線導体層を貫通する第2のコンタクトホールを形成する工程と、
前記第2のコンタクトホールに露出した前記第3の配線導体層の側面に第1の管状絶縁層を形成する工程と、
前記第2のコンタクトホールを充満して導電性を有する第6の導体材料層を形成する工程と、
前記第6の導体材料層の上部の側面を露出させる工程と、
前記第1の材料層を形成する工程は、前記第6の導体材料層の側面を囲んで第3の材料層を形成する工程を含み、
前記第2の材料層を形成する工程は、前記第3の材料層を囲んで第4の材料層を形成する工程を含み、そして、
前記第4の材料層をエッチングマスクにして、前記第3の材料層をエッチングして、前記第2の配線導体層と前記第6の導体材料層の上面に繋がる第3のコンタクトホールを形成する工程と、
前記第3のコンタクトホールに導電性を有する第7の導体材料層を形成す工程と、をさらに備える、
ことを特徴とする請求項13に記載の柱状半導体装置の製造方法。 - 平面視において、前記第1のコンタクトホール、前記第2のコンタクトホール、前記第3のコンタクトホールの場所以外にあり、前記第1のゲート導体層、前記第2ゲート導体層、前記第4の不純物領域、前記第5の不純物領域のいずれかに接続され水平方向に延在する第5の配線導体層に繋がり、且つ前記第2の材料層の表面より下方に延びる第4のコンタクトホールを形成する工程と、
第8の導体材料層を前記第4のコンタクトホールに充満する工程と、
をさらに備える、
ことを特徴とする請求項22に記載の柱状半導体装置の製造方法。 - 平面視において、前記第2のコンタクトホールに面した前記第3の配線導体層の側面が、前記第2の配線導体層の側面より、外側になるように形成される、
ことを特徴とする請求項22に記載の柱状半導体装置の製造方法。
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