JP6356550B2 - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

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JP6356550B2
JP6356550B2 JP2014183972A JP2014183972A JP6356550B2 JP 6356550 B2 JP6356550 B2 JP 6356550B2 JP 2014183972 A JP2014183972 A JP 2014183972A JP 2014183972 A JP2014183972 A JP 2014183972A JP 6356550 B2 JP6356550 B2 JP 6356550B2
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insulating substrate
case
semiconductor device
resin
outer edge
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JP2016058563A (ja
JP2016058563A5 (https=
Inventor
義貴 大坪
義貴 大坪
吉田 博
博 吉田
藤野 純司
純司 藤野
菊池 正雄
正雄 菊池
村井 淳一
淳一 村井
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to JP2014183972A priority Critical patent/JP6356550B2/ja
Priority to US14/717,309 priority patent/US9443778B2/en
Priority to DE102015213495.4A priority patent/DE102015213495B4/de
Priority to CN201510575213.1A priority patent/CN105405815B/zh
Publication of JP2016058563A publication Critical patent/JP2016058563A/ja
Publication of JP2016058563A5 publication Critical patent/JP2016058563A5/ja
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10W74/00Encapsulations, e.g. protective coatings
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    • H10W40/00Arrangements for thermal protection or thermal control
    • H10W40/20Arrangements for cooling
    • H10W40/25Arrangements for cooling characterised by their materials
    • H10W40/255Arrangements for cooling characterised by their materials having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates
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    • H10W40/00Arrangements for thermal protection or thermal control
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    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01Manufacture or treatment
    • H10W70/05Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/095Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
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    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63Vias, e.g. via plugs
    • H10W70/635Through-vias
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    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68Shapes or dispositions thereof
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    • H10W74/131Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/134Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being in grooves in the semiconductor body
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    • H10W72/07531Techniques
    • H10W72/07532Compression bonding, e.g. thermocompression bonding
    • H10W72/07533Ultrasonic bonding, e.g. thermosonic bonding
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    • H10W72/5475Dispositions of multiple bond wires multiple bond wires connected to common bond pads at both ends of the wires
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    • H10W72/551Materials of bond wires
    • H10W72/552Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5524Materials of bond wires comprising metals or metalloids, e.g. silver comprising aluminium [Al]
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    • H10W72/551Materials of bond wires
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    • H10W72/5525Materials of bond wires comprising metals or metalloids, e.g. silver comprising copper [Cu]
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    • H10W90/731Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
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    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/753Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between laterally-adjacent chips

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Ceramic Engineering (AREA)
JP2014183972A 2014-09-10 2014-09-10 半導体装置およびその製造方法 Active JP6356550B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2014183972A JP6356550B2 (ja) 2014-09-10 2014-09-10 半導体装置およびその製造方法
US14/717,309 US9443778B2 (en) 2014-09-10 2015-05-20 Semiconductor device and manufacturing method thereof
DE102015213495.4A DE102015213495B4 (de) 2014-09-10 2015-07-17 Halbleitervorrichtung und Herstellungsverfahren dafür
CN201510575213.1A CN105405815B (zh) 2014-09-10 2015-09-10 半导体装置及其制造方法

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JP2014183972A JP6356550B2 (ja) 2014-09-10 2014-09-10 半導体装置およびその製造方法

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JP2018108039A Division JP2018133598A (ja) 2018-06-05 2018-06-05 半導体装置およびその製造方法

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JP2016058563A JP2016058563A (ja) 2016-04-21
JP2016058563A5 JP2016058563A5 (https=) 2017-01-19
JP6356550B2 true JP6356550B2 (ja) 2018-07-11

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JP (1) JP6356550B2 (https=)
CN (1) CN105405815B (https=)
DE (1) DE102015213495B4 (https=)

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