JP5394276B2 - 駆動回路 - Google Patents
駆動回路 Download PDFInfo
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- JP5394276B2 JP5394276B2 JP2010023729A JP2010023729A JP5394276B2 JP 5394276 B2 JP5394276 B2 JP 5394276B2 JP 2010023729 A JP2010023729 A JP 2010023729A JP 2010023729 A JP2010023729 A JP 2010023729A JP 5394276 B2 JP5394276 B2 JP 5394276B2
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- thin film
- film transistor
- signal
- gate
- layer
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- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 1
- QQQSFSZALRVCSZ-UHFFFAOYSA-N triethoxysilane Chemical compound CCO[SiH](OCC)OCC QQQSFSZALRVCSZ-UHFFFAOYSA-N 0.000 description 1
- JOHWNGGYGAVMGU-UHFFFAOYSA-N trifluorochlorine Chemical compound FCl(F)F JOHWNGGYGAVMGU-UHFFFAOYSA-N 0.000 description 1
- IGELFKKMDLGCJO-UHFFFAOYSA-N xenon difluoride Chemical compound F[Xe]F IGELFKKMDLGCJO-UHFFFAOYSA-N 0.000 description 1
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Description
本実施の形態では、駆動回路の一形態及び当該薄膜トランジスタの構成について説明する。
図17に、薄膜トランジスタの一形態の断面図を示す。図17に示す薄膜トランジスタは、基板1101上に、ゲート電極1103と、微結晶半導体層1115aと、混合層1115bと、非晶質半導体を含む層1129cと、ゲート電極1103及び微結晶半導体層1115aの間に設けられるゲート絶縁層1105と、非晶質半導体を含む層1129cに接するソース領域及びドレイン領域として機能する不純物半導体層1127と、不純物半導体層1127に接する配線1125とを有する。
図19に、薄膜トランジスタの一形態の断面図を示す。図19に示す薄膜トランジスタは、基板1101上にゲート電極1103を有し、ゲート電極1103を覆うゲート絶縁層1105を有し、ゲート絶縁層1105に接してチャネル領域として機能する微結晶半導体層1131を有し、微結晶半導体層1131上に一対の非晶質半導体を含む層1132を有し、非晶質半導体を含む層1132に接して、ソース領域及びドレイン領域として機能する不純物半導体層1127を有する。また、不純物半導体層1127に接して配線1125を有する。配線1125はソース電極及びドレイン電極として機能する。また、微結晶半導体層1131の表面には、第1の絶縁層1135aが形成される。また、一対の非晶質半導体を含む層1132及び不純物半導体層1127の表面には、第2の絶縁層1135cが形成される。また、配線1125の表面には、第3の絶縁層1135eが形成される。
本実施の形態では、上記実施の形態とは異なる構成の駆動回路の一形態について説明する。
本実施の形態では、表示素子、表示素子を有する装置である表示装置、発光素子、発光素子を有する装置である発光装置の一例について説明する。なお、表示素子、表示素子を有する装置である表示装置、発光素子、発光素子を有する装置である発光装置は、様々な形態を用いたり、様々な素子を有することが出来る。例えば、表示素子、表示装置、発光素子または発光装置としては、EL(エレクトロルミネッセンス)素子(有機物及び無機物を含むEL素子、有機EL素子、無機EL素子)、LED(白色LED、赤色LED、緑色LED、青色LEDなど)、電流に応じて発光するトランジスタ、電子放出素子、液晶素子、電子インク、電気泳動素子、グレーティングライトバルブ(GLV)、プラズマディスプレイパネル(PDP)、デジタルマイクロミラーデバイス(DMD)、圧電セラミックディスプレイ、カーボンナノチューブ、など、電気磁気的作用により、コントラスト、輝度、反射率、透過率などが変化する表示媒体を有することができる。なお、EL素子を用いた表示装置としてはELディスプレイ、電子放出素子を用いた表示装置としてはフィールドエミッションディスプレイ(FED)やSED方式平面型ディスプレイ(SED:Surface−conduction Electron−emitter Disply)など、液晶素子を用いた表示装置としては液晶ディスプレイ(透過型液晶ディスプレイ、半透過型液晶ディスプレイ、反射型液晶ディスプレイ、直視型液晶ディスプレイ、投射型液晶ディスプレイ)、電子インクや電気泳動素子を用いた表示装置としては電子ペーパーがある。
本実施の形態では、ソースドライバの一例について説明する。
本実施の形態においては、液晶表示装置に適用できる画素の構成及び画素の動作について説明する。
本実施の形態では、実施の形態1に示す薄膜トランジスタの作製方法について図20乃至図25を参照して説明する。
はじめに、図17で示した、薄膜トランジスタの作製工程を、図20で説明する。図20で(A)に示すように、基板1101上にゲート電極1103を形成する。次に、ゲート電極1103を覆うゲート絶縁層1105を形成した後に、第1の半導体層1106を形成する。
上記(方法1)とは異なる薄膜トランジスタの作製方法について、図20、図23及び図24を用いて示す。
次に、図19に示す薄膜トランジスタの作製方法について、図20、図21、及び図25を用いて示す。
(方法1)乃至(方法3)に適用可能な第2の半導体層1107の作製方法について、以下に示す。ここでは、第2の半導体層1107の原料ガスとして、窒素を含む気体を用いる代わりに、プラズマCVD装置の処理室内に窒素を含む層を形成した後、第2の半導体層1107を形成することで、第2の半導体層1107に窒素を供給することを特徴とする。
(方法1)乃至(方法3)に適用可能な第2の半導体層1107の作製方法について、以下に示す。ここでは、第2の半導体層1107の原料ガスとして、窒素を含む気体を用いる代わりに、第2の半導体層1107を形成する前にCVD装置の処理室内に窒素を含む気体を導入した後、第2の半導体層1107を形成することで、第2の半導体層1107に窒素を供給することを特徴とする。
本実施の形態では、表示装置の一形態として、液晶表示装置の断面構造について、図26を参照して説明する。具体的には、TFT基板と、対向基板と、対向基板とTFT基板との間に挟持された液晶層とを有する液晶表示装置の構成について説明する。また、図26(A)は、液晶表示装置の上面図である。図26(B)は、図26(A)の線C−Dにおける断面図である。なお、図26(B)は、基板1601上に、チャネル領域に微結晶半導体層を用いた逆スタガ型の薄膜トランジスタを形成した構造を有し、表示方式がMVA(Multi−domain Vertical Alignment)方式の液晶表示装置の断面図である。
本実施の形態においては、電子機器の例について説明する。
101 パルス出力回路
102 配線
103 配線
104 配線
106 半導体層
111 薄膜トランジスタ
112 薄膜トランジスタ
113 薄膜トランジスタ
114 薄膜トランジスタ
115 薄膜トランジスタ
116 薄膜トランジスタ
117 薄膜トランジスタ
118 薄膜トランジスタ
119 薄膜トランジスタ
120 薄膜トランジスタ
121 薄膜トランジスタ
131 電源線
132 電源線
151 信号線
152 信号線
153 信号線
154 信号線
155 信号線
156 信号線
157 信号線
166 信号線
171 電源線
172 電源線
201 期間
540 画素
600 回路
601 回路
602 回路
603 薄膜トランジスタ
604 配線
605 配線
614 信号
615 信号
700 シフトレジスタ
701 パルス出力回路
702 配線
703 配線
704 配線
705 配線
706 配線
1101 基板
1103 ゲート電極
1105 ゲート絶縁層
1106 半導体層
1107 半導体層
1109 不純物半導体層
1111 導電層
1113 レジストマスク
1115 半導体層
1117 不純物半導体層
1119 導電層
1123 レジストマスク
1125 配線
1127 不純物半導体層
1131 微結晶半導体層
1132 層
1133 配線
1140 プラズマ処理
1180 グレートーンマスク
1181 基板
1182 遮光部
1183 回折格子部
1185 ハーフトーンマスク
1186 基板
1187 半透光部
1188 遮光部
1601 基板
1603 画素部
1607 信号線駆動回路
1609 シール材
1611 基板
1613 FPC
1615 ICチップ
1617 端子部
1621 薄膜トランジスタ
1623 薄膜トランジスタ
1625 絶縁層
1627 絶縁層
1629 配線
1631 画素電極
1635 絶縁層
1641 導電層
1643 絶縁層
1645 突起部
1647 スペーサ
1649 液晶層
1651 微結晶半導体層
1653 不純物半導体層
1655 配線
1657 異方性導電体層
1659 接続端子
1661 異方性導電体層
1700 筐体
1701 筐体
1702 表示部
1703 表示部
1704 蝶番
1705 電源入力端子
1706 操作キー
1707 スピーカ
1711 筐体
1712 表示部
1721 筐体
1722 表示部
1723 スタンド
1731 筐体
1732 表示部
1733 操作ボタン
1734 外部接続ポート
1735 スピーカ
1736 マイク
1737 操作ボタン
2801 電源線
2802 薄膜トランジスタ
2901 容量素子
5321 薄膜トランジスタ
5360 映像信号
5361 回路
5362 ソースドライバ
5363 ゲートドライバ
5364 画素部
5365 回路
5366 照明装置
5367 画素
5371 配線
5372 配線
5373 配線
5380 基板
5381 入力端子
5420 画素
5421 薄膜トランジスタ
5422 液晶素子
5423 容量素子
5431 配線
5432 配線
5433 配線
5434 電極
5441 信号
5442 電圧
1107a 微結晶半導体層
1107b 混合層
1107c 層
1108a 微結晶半導体領域
1108b 非晶質半導体領域
1115a 微結晶半導体層
1115b 混合層
1115c 層
1129a 層
1129c 層
1131a 微結晶半導体層
1131b 微結晶半導体層
1135a 絶縁層
1135c 絶縁層
1135e 絶縁層
1605a 走査線駆動回路
1605b 走査線駆動回路
5361a 回路
5361b 回路
5362a ソースドライバ
5362b ソースドライバ
5420A サブ画素
5420B サブ画素
5421A 薄膜トランジスタ
5421B 薄膜トランジスタ
5422A 液晶素子
5422B 液晶素子
5423A 容量素子
5423B 容量素子
5431A 配線
5431B 配線
5432A 配線
5432B 配線
Claims (7)
- 第1乃至第8トランジスタを有し、
前記第1トランジスタのソースまたはドレインの一方は、前記第2トランジスタのソースまたはドレインの一方と電気的に接続され、
前記第3トランジスタのソースまたはドレインの一方は、前記第1トランジスタのゲートと電気的に接続され、
前記第4トランジスタのゲートは、前記第2トランジスタのゲートと電気的に接続され、
前記第5トランジスタのソースまたはドレインの一方は、前記第3トランジスタのソースまたはドレインの他方と電気的に接続され、
前記第6トランジスタのソースまたはドレインの一方は、前記第2トランジスタのゲートと電気的に接続され、
前記第7トランジスタのソースまたはドレインの一方は、前記第2トランジスタのゲートと電気的に接続され、
前記第8トランジスタのソースまたはドレインの一方は、前記第2トランジスタのゲートと電気的に接続され、
前記第5ランジスタのソースまたはドレインの他方は、前記第6トランジスタのソースまたはドレインの他方と電気的に接続され、
前記第5トランジスタのソースまたはドレインの他方は、前記第7トランジスタのソースまたはドレインの他方と電気的に接続され、
前記第3トランジスタのゲートは、第1の配線に電気的に接続され、
前記第3トランジスタのゲートは、前記第7トランジスタのソースまたはドレインの前記他方とは電気的に接続されない駆動回路。 - 第1乃至第11トランジスタを有し、
前記第1トランジスタのソースまたはドレインの一方は、前記第2トランジスタのソースまたはドレインの一方と電気的に接続され、
前記第3トランジスタのソースまたはドレインの一方は、前記第1トランジスタのゲートと電気的に接続され、
前記第4トランジスタのゲートは、前記第2トランジスタのゲートと電気的に接続され、
前記第5トランジスタのソースまたはドレインの一方は、前記第3トランジスタのソースまたはドレインの他方と電気的に接続され、
前記第6トランジスタのソースまたはドレインの一方は、前記第2トランジスタのゲートと電気的に接続され、
前記第7トランジスタのソースまたはドレインの一方は、前記第2トランジスタのゲートと電気的に接続され、
前記第8トランジスタのソースまたはドレインの一方は、前記第2トランジスタのゲートと電気的に接続され、
前記第5ランジスタのソースまたはドレインの他方は、前記第6トランジスタのソースまたはドレインの他方と電気的に接続され、
前記第3トランジスタのゲートは、第1の配線に電気的に接続され、
前記第3トランジスタのゲートは、前記第7トランジスタのソースまたはドレインの他方とは電気的に接続されず、
前記第9トランジスタのゲートは、前記第1のトランジスタのゲートに電気的に接続され、
前記第10トランジスタのゲートは、前記第2トランジスタのゲートに電気的に接続され、
前記第9トランジスタのソースまたはドレインの一方は、前記第10トランジスタのソースまたはドレインの一方に電気的に接続され、
前記第11トランジスタのソースまたはドレインの一方は、前記第9トランジスタのソースまたはドレインの前記一方に電気的に接続され、
前記第1トランジスタのソースまたはドレインの前記他方は、前記第9トランジスタのソースまたはドレインの他方に電気的に接続される駆動回路。 - 請求項1または請求項2において、
前記第5トランジスタのソースまたはドレインの前記他方は、第2の配線に電気的に接続され、
前記第6トランジスタのソースまたはドレインの前記他方は、前記第2の配線に電気的に接続され、
前記第7トランジスタのソースまたはドレインの前記他方は、前記第2の配線に電気的に接続される駆動回路。 - 請求項1乃至請求項3のいずれか一において、
前記第2トランジスタのソースまたはドレインの他方は、第3の配線に電気的に接続され、
前記第4トランジスタのソースまたはドレインの他方は、前記第3の配線に電気的に接続され、
前記第8トランジスタのソースまたはドレインの他方は、前記第3の配線に電気的に接続される駆動回路。 - 請求項4において、
前記第3の配線は第3の電源供給線である駆動回路。 - 請求項3乃至請求項5のいずれか一において、
前記第2の配線は第2の電源供給線である駆動回路。 - 請求項1乃至請求項6のいずれか一において、
前記第1の配線は第1の電源供給線である駆動回路。
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