JP5345521B2 - 二層パッシベーションを有するトランジスタ及び方法 - Google Patents

二層パッシベーションを有するトランジスタ及び方法 Download PDF

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JP5345521B2
JP5345521B2 JP2009505525A JP2009505525A JP5345521B2 JP 5345521 B2 JP5345521 B2 JP 5345521B2 JP 2009505525 A JP2009505525 A JP 2009505525A JP 2009505525 A JP2009505525 A JP 2009505525A JP 5345521 B2 JP5345521 B2 JP 5345521B2
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alignment
region
forming
layer
semiconductor
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JP2009533874A5 (enExample
JP2009533874A (ja
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エム． グリーン、ブルース
エス． ヘンリー、ホールデン
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NXP USA Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H10D30/87—FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET]
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G03F9/7076—Mark details, e.g. phase grating mark, temporary mark
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G03F9/708—Mark formation
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G03F9/7084—Position of mark on substrate, i.e. position in (x, y, z) of mark, e.g. buried or resist covered mark, mark on rearside, at the substrate edge, in the circuit area, latent image mark, marks in plural levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/252—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H01L2223/5446—Located in scribe lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
JP2009505525A 2006-04-13 2007-03-12 二層パッシベーションを有するトランジスタ及び方法 Active JP5345521B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/404,714 2006-04-13
US11/404,714 US8193591B2 (en) 2006-04-13 2006-04-13 Transistor and method with dual layer passivation
PCT/US2007/063775 WO2007121010A2 (en) 2006-04-13 2007-03-12 Transistor and method with dual layer passivation

Publications (3)

Publication Number Publication Date
JP2009533874A JP2009533874A (ja) 2009-09-17
JP2009533874A5 JP2009533874A5 (enExample) 2010-03-11
JP5345521B2 true JP5345521B2 (ja) 2013-11-20

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JP2009505525A Active JP5345521B2 (ja) 2006-04-13 2007-03-12 二層パッシベーションを有するトランジスタ及び方法

Country Status (6)

Country Link
US (2) US8193591B2 (enExample)
EP (1) EP2011155A4 (enExample)
JP (1) JP5345521B2 (enExample)
KR (1) KR20090007318A (enExample)
CN (1) CN101427379B (enExample)
WO (1) WO2007121010A2 (enExample)

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US7935620B2 (en) * 2007-12-05 2011-05-03 Freescale Semiconductor, Inc. Method for forming semiconductor devices with low leakage Schottky contacts
US8431962B2 (en) * 2007-12-07 2013-04-30 Northrop Grumman Systems Corporation Composite passivation process for nitride FET
US7632726B2 (en) * 2007-12-07 2009-12-15 Northrop Grumman Space & Mission Systems Corp. Method for fabricating a nitride FET including passivation layers
CN101789391B (zh) * 2009-01-23 2012-08-22 中芯国际集成电路制造(上海)有限公司 半导体装置及其制造方法
US8304271B2 (en) * 2009-05-20 2012-11-06 Jenn Hwa Huang Integrated circuit having a bulk acoustic wave device and a transistor
JP4794655B2 (ja) * 2009-06-09 2011-10-19 シャープ株式会社 電界効果トランジスタ
JP5890709B2 (ja) * 2011-06-30 2016-03-22 株式会社東芝 テンプレート用基板及びその製造方法
US8653558B2 (en) 2011-10-14 2014-02-18 Freescale Semiconductor, Inc. Semiconductor device and method of making
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US10522670B2 (en) 2012-06-26 2019-12-31 Nxp Usa, Inc. Semiconductor device with selectively etched surface passivation
US8946776B2 (en) 2012-06-26 2015-02-03 Freescale Semiconductor, Inc. Semiconductor device with selectively etched surface passivation
US9111868B2 (en) 2012-06-26 2015-08-18 Freescale Semiconductor, Inc. Semiconductor device with selectively etched surface passivation
US10825924B2 (en) 2012-06-26 2020-11-03 Nxp Usa, Inc. Semiconductor device with selectively etched surface passivation
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JP6241100B2 (ja) * 2013-07-17 2017-12-06 豊田合成株式会社 Ｍｏｓｆｅｔ
US9685345B2 (en) * 2013-11-19 2017-06-20 Nxp Usa, Inc. Semiconductor devices with integrated Schottky diodes and methods of fabrication
KR102736227B1 (ko) 2016-07-29 2024-12-03 삼성전자주식회사 회로 기판 및 반도체 패키지
US10741496B2 (en) 2018-12-04 2020-08-11 Nxp Usa, Inc. Semiconductor devices with a protection layer and methods of fabrication
CN112750903B (zh) * 2019-10-29 2022-09-27 苏州能讯高能半导体有限公司 半导体器件及其制造方法
CN112687543B (zh) * 2020-12-09 2021-09-03 上海芯导电子科技股份有限公司 一种氮化镓器件的制备方法及终端结构

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Also Published As

Publication number Publication date
US20130015462A1 (en) 2013-01-17
US9029986B2 (en) 2015-05-12
KR20090007318A (ko) 2009-01-16
CN101427379A (zh) 2009-05-06
CN101427379B (zh) 2010-12-29
JP2009533874A (ja) 2009-09-17
EP2011155A4 (en) 2009-09-16
WO2007121010A3 (en) 2009-01-15
US8193591B2 (en) 2012-06-05
US20070241419A1 (en) 2007-10-18
EP2011155A2 (en) 2009-01-07
WO2007121010A2 (en) 2007-10-25

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