KR20090007318A - 듀얼 층 패시베이션을 갖는 트랜지스터 및 방법 - Google Patents

듀얼 층 패시베이션을 갖는 트랜지스터 및 방법 Download PDF

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Publication number
KR20090007318A
KR20090007318A KR1020087024820A KR20087024820A KR20090007318A KR 20090007318 A KR20090007318 A KR 20090007318A KR 1020087024820 A KR1020087024820 A KR 1020087024820A KR 20087024820 A KR20087024820 A KR 20087024820A KR 20090007318 A KR20090007318 A KR 20090007318A
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South Korea
Prior art keywords
layer
forming
alignment
semiconductor
region
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KR1020087024820A
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English (en)
Korean (ko)
Inventor
브루스 엠. 그린
홀데인 에스. 헨리
Original Assignee
프리스케일 세미컨덕터, 인크.
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Publication of KR20090007318A publication Critical patent/KR20090007318A/ko
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H10D30/87—FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET]
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G03F9/7076—Mark details, e.g. phase grating mark, temporary mark
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G03F9/708—Mark formation
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G03F9/7084—Position of mark on substrate, i.e. position in (x, y, z) of mark, e.g. buried or resist covered mark, mark on rearside, at the substrate edge, in the circuit area, latent image mark, marks in plural levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/252—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H01L2223/5446—Located in scribe lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
KR1020087024820A 2006-04-13 2007-03-12 듀얼 층 패시베이션을 갖는 트랜지스터 및 방법 Withdrawn KR20090007318A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/404,714 2006-04-13
US11/404,714 US8193591B2 (en) 2006-04-13 2006-04-13 Transistor and method with dual layer passivation

Publications (1)

Publication Number Publication Date
KR20090007318A true KR20090007318A (ko) 2009-01-16

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020087024820A Withdrawn KR20090007318A (ko) 2006-04-13 2007-03-12 듀얼 층 패시베이션을 갖는 트랜지스터 및 방법

Country Status (6)

Country Link
US (2) US8193591B2 (enExample)
EP (1) EP2011155A4 (enExample)
JP (1) JP5345521B2 (enExample)
KR (1) KR20090007318A (enExample)
CN (1) CN101427379B (enExample)
WO (1) WO2007121010A2 (enExample)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8193591B2 (en) * 2006-04-13 2012-06-05 Freescale Semiconductor, Inc. Transistor and method with dual layer passivation
US7935620B2 (en) * 2007-12-05 2011-05-03 Freescale Semiconductor, Inc. Method for forming semiconductor devices with low leakage Schottky contacts
US8431962B2 (en) * 2007-12-07 2013-04-30 Northrop Grumman Systems Corporation Composite passivation process for nitride FET
US7632726B2 (en) * 2007-12-07 2009-12-15 Northrop Grumman Space & Mission Systems Corp. Method for fabricating a nitride FET including passivation layers
CN101789391B (zh) * 2009-01-23 2012-08-22 中芯国际集成电路制造(上海)有限公司 半导体装置及其制造方法
US8304271B2 (en) * 2009-05-20 2012-11-06 Jenn Hwa Huang Integrated circuit having a bulk acoustic wave device and a transistor
JP4794655B2 (ja) * 2009-06-09 2011-10-19 シャープ株式会社 電界効果トランジスタ
JP5890709B2 (ja) * 2011-06-30 2016-03-22 株式会社東芝 テンプレート用基板及びその製造方法
US8653558B2 (en) 2011-10-14 2014-02-18 Freescale Semiconductor, Inc. Semiconductor device and method of making
US9601638B2 (en) * 2011-10-19 2017-03-21 Nxp Usa, Inc. GaN-on-Si switch devices
US8754421B2 (en) * 2012-02-24 2014-06-17 Raytheon Company Method for processing semiconductors using a combination of electron beam and optical lithography
US10522670B2 (en) 2012-06-26 2019-12-31 Nxp Usa, Inc. Semiconductor device with selectively etched surface passivation
US8946776B2 (en) 2012-06-26 2015-02-03 Freescale Semiconductor, Inc. Semiconductor device with selectively etched surface passivation
US9111868B2 (en) 2012-06-26 2015-08-18 Freescale Semiconductor, Inc. Semiconductor device with selectively etched surface passivation
US10825924B2 (en) 2012-06-26 2020-11-03 Nxp Usa, Inc. Semiconductor device with selectively etched surface passivation
JP2014138111A (ja) * 2013-01-17 2014-07-28 Fujitsu Ltd 半導体装置及びその製造方法、電源装置、高周波増幅器
US8946779B2 (en) 2013-02-26 2015-02-03 Freescale Semiconductor, Inc. MISHFET and Schottky device integration
JP6197427B2 (ja) * 2013-07-17 2017-09-20 豊田合成株式会社 ショットキーバリアダイオード
JP6241100B2 (ja) * 2013-07-17 2017-12-06 豊田合成株式会社 Ｍｏｓｆｅｔ
US9685345B2 (en) * 2013-11-19 2017-06-20 Nxp Usa, Inc. Semiconductor devices with integrated Schottky diodes and methods of fabrication
KR102736227B1 (ko) 2016-07-29 2024-12-03 삼성전자주식회사 회로 기판 및 반도체 패키지
US10741496B2 (en) 2018-12-04 2020-08-11 Nxp Usa, Inc. Semiconductor devices with a protection layer and methods of fabrication
CN112750903B (zh) * 2019-10-29 2022-09-27 苏州能讯高能半导体有限公司 半导体器件及其制造方法
CN112687543B (zh) * 2020-12-09 2021-09-03 上海芯导电子科技股份有限公司 一种氮化镓器件的制备方法及终端结构

Family Cites Families (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2103419A (en) * 1981-08-04 1983-02-16 Siliconix Inc Field effect transistor with metal source
JPS628575A (ja) * 1985-07-04 1987-01-16 Nec Corp 半導体装置
JPS63248136A (ja) * 1987-04-02 1988-10-14 Nec Corp 半導体装置
US4843037A (en) 1987-08-21 1989-06-27 Bell Communications Research, Inc. Passivation of indium gallium arsenide surfaces
US4925808A (en) * 1989-03-24 1990-05-15 Sprague Electric Company Method for making IC die with dielectric isolation
JPH07111966B2 (ja) 1989-12-22 1995-11-29 株式会社東芝 半導体装置の製造方法
JPH04133439A (ja) * 1990-09-26 1992-05-07 Sharp Corp 電界効果トランジスタの製造方法
US5341114A (en) * 1990-11-02 1994-08-23 Ail Systems, Inc. Integrated limiter and amplifying devices
JPH0745635A (ja) * 1993-07-26 1995-02-14 Murata Mfg Co Ltd 電界効果トランジスタの製造方法
JPH0774184A (ja) * 1993-09-06 1995-03-17 Toshiba Corp ショットキーゲート型電界効果トランジスタの製造方法
KR0144821B1 (ko) 1994-05-16 1998-07-01 양승택 저전원전압으로 작동가능한 갈륨비소 반도체 전력소자의 제조 방법
US20040004262A1 (en) * 1994-05-31 2004-01-08 Welch James D. Semiconductor devices in compensated semiconductor
US5401691A (en) * 1994-07-01 1995-03-28 Cypress Semiconductor Corporation Method of fabrication an inverse open frame alignment mark
JP3393237B2 (ja) * 1994-10-04 2003-04-07 ソニー株式会社 半導体装置の製造方法
JPH0945635A (ja) * 1995-07-27 1997-02-14 Mitsubishi Electric Corp 半導体装置の製造方法，及び半導体装置
US5799028A (en) 1996-07-18 1998-08-25 Sdl, Inc. Passivation and protection of a semiconductor surface
JP3203192B2 (ja) * 1996-10-16 2001-08-27 三洋電機株式会社 半導体装置およびその製造方法
US6054752A (en) * 1997-06-30 2000-04-25 Denso Corporation Semiconductor device
JP2000091348A (ja) * 1998-09-09 2000-03-31 Sanyo Electric Co Ltd 電界効果型半導体装置及びその製造方法
JP4114248B2 (ja) * 1998-10-09 2008-07-09 株式会社デンソー 電界効果トランジスタの製造方法
TW436961B (en) * 1998-12-14 2001-05-28 United Microelectronics Corp Method for forming the dielectric layer of an alignment marker area
TW474024B (en) 1999-08-16 2002-01-21 Cornell Res Foundation Inc Passivation of GaN based FETs
US6436763B1 (en) * 2000-02-07 2002-08-20 Taiwan Semiconductor Manufacturing Company Process for making embedded DRAM circuits having capacitor under bit-line (CUB)
US6319837B1 (en) * 2000-06-29 2001-11-20 Agere Systems Guardian Corp. Technique for reducing dishing in Cu-based interconnects
US6696220B2 (en) 2000-10-12 2004-02-24 Board Of Regents, The University Of Texas System Template for room temperature, low pressure micro-and nano-imprint lithography
JP3378561B2 (ja) * 2000-08-04 2003-02-17 日本電信電話株式会社 半導体装置の製造方法
JP3462166B2 (ja) * 2000-09-08 2003-11-05 富士通カンタムデバイス株式会社 化合物半導体装置
US6870225B2 (en) * 2001-11-02 2005-03-22 International Business Machines Corporation Transistor structure with thick recessed source/drain structures and fabrication process of same
US6835954B2 (en) 2001-12-29 2004-12-28 Lg.Philips Lcd Co., Ltd. Active matrix organic electroluminescent display device
JP3951743B2 (ja) * 2002-02-28 2007-08-01 松下電器産業株式会社 半導体装置およびその製造方法
JP2003282597A (ja) * 2002-03-22 2003-10-03 Sumitomo Electric Ind Ltd 電界効果トランジスタの製造方法
TWI255432B (en) * 2002-06-03 2006-05-21 Lg Philips Lcd Co Ltd Active matrix organic electroluminescent display device and fabricating method thereof
US7183120B2 (en) * 2002-10-31 2007-02-27 Honeywell International Inc. Etch-stop material for improved manufacture of magnetic devices
AU2003301057A1 (en) 2002-12-20 2004-07-22 Cree, Inc. Methods of forming semiconductor mesa structures including self-aligned contact layers and related devices
US6803291B1 (en) * 2003-03-20 2004-10-12 Taiwan Semiconductor Manufacturing Co., Ltd Method to preserve alignment mark optical integrity
US7135720B2 (en) 2003-08-05 2006-11-14 Nitronex Corporation Gallium nitride material transistors and methods associated with the same
US7053425B2 (en) 2003-11-12 2006-05-30 General Electric Company Gas sensor device
US7649215B2 (en) 2003-12-05 2010-01-19 International Rectifier Corporation III-nitride device passivation and method
US7332795B2 (en) * 2004-05-22 2008-02-19 Cree, Inc. Dielectric passivation for semiconductor devices
TW200602774A (en) * 2004-07-06 2006-01-16 Chunghwa Picture Tubes Ltd Thin-film transistor manufacture method
US7485514B2 (en) * 2006-01-05 2009-02-03 Winslow Thomas A Method for fabricating a MESFET
US8193591B2 (en) * 2006-04-13 2012-06-05 Freescale Semiconductor, Inc. Transistor and method with dual layer passivation

Also Published As

Publication number Publication date
US20130015462A1 (en) 2013-01-17
US9029986B2 (en) 2015-05-12
JP5345521B2 (ja) 2013-11-20
CN101427379A (zh) 2009-05-06
CN101427379B (zh) 2010-12-29
JP2009533874A (ja) 2009-09-17
EP2011155A4 (en) 2009-09-16
WO2007121010A3 (en) 2009-01-15
US8193591B2 (en) 2012-06-05
US20070241419A1 (en) 2007-10-18
EP2011155A2 (en) 2009-01-07
WO2007121010A2 (en) 2007-10-25

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Patent event date: 20081010

Patent event code: PA01051R01D

Comment text: International Patent Application

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WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid