JP5345521B2 - 二層パッシベーションを有するトランジスタ及び方法 - Google Patents
二層パッシベーションを有するトランジスタ及び方法 Download PDFInfo
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- 238000002161 passivation Methods 0.000 title claims description 39
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
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- G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
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- G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
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- G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
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- G03F9/7073—Alignment marks and their environment
- G03F9/7084—Position of mark on substrate, i.e. position in (x, y, z) of mark, e.g. buried or resist covered mark, mark on rearside, at the substrate edge, in the circuit area, latent image mark, marks in plural levels
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
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- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
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- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Electrodes Of Semiconductors (AREA)
Description
Claims (3)
- 半導体デバイスを形成する方法であって、
主面を有する基板を設けることと、
位置合わせに用いられる波長において光学的に透明であり、かつ、外面を有するようになされている半導体層を、前記基板の前記主面上に形成することと、
前記外面上に第一のパッシベーション層を設けることと、
上面が依然として前記第一のパッシベーション層により覆われ、かつその側端部が露出されているデバイス・メサと、前記デバイス・メサから所定距離だけ離間して位置する1つ以上のアラインメント・メサとを、前記主面上方に同時に形成するように、前記第一のパッシベーション層の一部及び前記半導体層の一部を局所的にエッチングすることと、
前記1つ以上のアラインメント・メサの少なくとも一部の上に、位置合わせに用いられる前記波長において光学的に不透明な材料のアラインメント領域を設けることと、
少なくとも前記デバイス・メサの前記上面上の前記第一のパッシベーション層及び前記デバイス・メサの前記露出側端部を覆って、第二のパッシベーション層を形成することと、
前記第一及び第二のパッシベーション層を貫通して前記デバイス・メサ上の前記半導体層の前記上面まで、ソース−ドレイン・ビア及びゲート・ビアを設けることと、
前記ソース−ドレイン・ビア内の半導体へのオーミック接続及び前記ゲート・ビア内の半導体へのショットキー接続が得られるように、前記ビア内に導体を形成することと、
を含む方法。 - ソース−ドレイン・ビア及びゲート・ビアを設ける前記工程は、前記1つ以上のアラインメント・メサの少なくとも1つ内に、前記ソース−ドレイン・ビア又は前記ゲート・ビアを開けるのと同時に、アラインメントパターンを形成することを更に含む、請求項1に記載の方法。
- 半導体デバイスに関連してアラインメントマークを形成する方法であって、
主面を有する基板を設けることと、
前記基板の前記主面上に、位置合わせに用いられる波長において実質的に光学的に透明であり、かつ外面を有するようになされている半導体層を形成することと、
前記外面上に第一の誘電体層を設けることと、
前記主面上方にデバイス領域及びアラインメント領域を形成するように、前記第一の誘電体層の一部及び前記半導体層の一部を局所的にエッチングすることと、
前記アラインメント領域上に、位置合わせに用いられる前記波長において光学的に不透明であるようになされている光学的不透明領域を形成することと、
前記デバイス領域及び前記アラインメント領域上の前記光学的不透明領域を覆って第二の誘電体層を形成することと、
前記デバイス領域上の前記誘電体層内に1つ以上のビアを開口するのと同時に、前記アラインメント領域上の前記第二の誘電体層内にアラインメントパターンを形成することと、
を含む方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/404,714 | 2006-04-13 | ||
US11/404,714 US8193591B2 (en) | 2006-04-13 | 2006-04-13 | Transistor and method with dual layer passivation |
PCT/US2007/063775 WO2007121010A2 (en) | 2006-04-13 | 2007-03-12 | Transistor and method with dual layer passivation |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2009533874A JP2009533874A (ja) | 2009-09-17 |
JP2009533874A5 JP2009533874A5 (ja) | 2010-03-11 |
JP5345521B2 true JP5345521B2 (ja) | 2013-11-20 |
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Application Number | Title | Priority Date | Filing Date |
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JP2009505525A Active JP5345521B2 (ja) | 2006-04-13 | 2007-03-12 | 二層パッシベーションを有するトランジスタ及び方法 |
Country Status (6)
Country | Link |
---|---|
US (2) | US8193591B2 (ja) |
EP (1) | EP2011155A4 (ja) |
JP (1) | JP5345521B2 (ja) |
KR (1) | KR20090007318A (ja) |
CN (1) | CN101427379B (ja) |
WO (1) | WO2007121010A2 (ja) |
Families Citing this family (24)
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US8193591B2 (en) * | 2006-04-13 | 2012-06-05 | Freescale Semiconductor, Inc. | Transistor and method with dual layer passivation |
US7935620B2 (en) * | 2007-12-05 | 2011-05-03 | Freescale Semiconductor, Inc. | Method for forming semiconductor devices with low leakage Schottky contacts |
US7632726B2 (en) * | 2007-12-07 | 2009-12-15 | Northrop Grumman Space & Mission Systems Corp. | Method for fabricating a nitride FET including passivation layers |
US8431962B2 (en) * | 2007-12-07 | 2013-04-30 | Northrop Grumman Systems Corporation | Composite passivation process for nitride FET |
CN101789391B (zh) * | 2009-01-23 | 2012-08-22 | 中芯国际集成电路制造(上海)有限公司 | 半导体装置及其制造方法 |
US8304271B2 (en) * | 2009-05-20 | 2012-11-06 | Jenn Hwa Huang | Integrated circuit having a bulk acoustic wave device and a transistor |
JP4794655B2 (ja) * | 2009-06-09 | 2011-10-19 | シャープ株式会社 | 電界効果トランジスタ |
JP5890709B2 (ja) * | 2011-06-30 | 2016-03-22 | 株式会社東芝 | テンプレート用基板及びその製造方法 |
US8653558B2 (en) | 2011-10-14 | 2014-02-18 | Freescale Semiconductor, Inc. | Semiconductor device and method of making |
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US8754421B2 (en) | 2012-02-24 | 2014-06-17 | Raytheon Company | Method for processing semiconductors using a combination of electron beam and optical lithography |
US8946776B2 (en) | 2012-06-26 | 2015-02-03 | Freescale Semiconductor, Inc. | Semiconductor device with selectively etched surface passivation |
US10522670B2 (en) | 2012-06-26 | 2019-12-31 | Nxp Usa, Inc. | Semiconductor device with selectively etched surface passivation |
US10825924B2 (en) | 2012-06-26 | 2020-11-03 | Nxp Usa, Inc. | Semiconductor device with selectively etched surface passivation |
US9111868B2 (en) * | 2012-06-26 | 2015-08-18 | Freescale Semiconductor, Inc. | Semiconductor device with selectively etched surface passivation |
JP2014138111A (ja) * | 2013-01-17 | 2014-07-28 | Fujitsu Ltd | 半導体装置及びその製造方法、電源装置、高周波増幅器 |
US8946779B2 (en) | 2013-02-26 | 2015-02-03 | Freescale Semiconductor, Inc. | MISHFET and Schottky device integration |
JP6241100B2 (ja) * | 2013-07-17 | 2017-12-06 | 豊田合成株式会社 | Mosfet |
JP6197427B2 (ja) * | 2013-07-17 | 2017-09-20 | 豊田合成株式会社 | ショットキーバリアダイオード |
US9685345B2 (en) * | 2013-11-19 | 2017-06-20 | Nxp Usa, Inc. | Semiconductor devices with integrated Schottky diodes and methods of fabrication |
KR20180014362A (ko) | 2016-07-29 | 2018-02-08 | 삼성전자주식회사 | 회로 기판 및 반도체 패키지 |
US10741496B2 (en) | 2018-12-04 | 2020-08-11 | Nxp Usa, Inc. | Semiconductor devices with a protection layer and methods of fabrication |
CN112750903B (zh) * | 2019-10-29 | 2022-09-27 | 苏州能讯高能半导体有限公司 | 半导体器件及其制造方法 |
CN112687543B (zh) * | 2020-12-09 | 2021-09-03 | 上海芯导电子科技股份有限公司 | 一种氮化镓器件的制备方法及终端结构 |
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-
2006
- 2006-04-13 US US11/404,714 patent/US8193591B2/en active Active
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2007
- 2007-03-12 CN CN2007800132282A patent/CN101427379B/zh active Active
- 2007-03-12 EP EP07758334A patent/EP2011155A4/en not_active Withdrawn
- 2007-03-12 WO PCT/US2007/063775 patent/WO2007121010A2/en active Application Filing
- 2007-03-12 KR KR1020087024820A patent/KR20090007318A/ko not_active Application Discontinuation
- 2007-03-12 JP JP2009505525A patent/JP5345521B2/ja active Active
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US9029986B2 (en) | 2015-05-12 |
KR20090007318A (ko) | 2009-01-16 |
US8193591B2 (en) | 2012-06-05 |
EP2011155A4 (en) | 2009-09-16 |
US20070241419A1 (en) | 2007-10-18 |
WO2007121010A3 (en) | 2009-01-15 |
WO2007121010A2 (en) | 2007-10-25 |
CN101427379A (zh) | 2009-05-06 |
US20130015462A1 (en) | 2013-01-17 |
CN101427379B (zh) | 2010-12-29 |
JP2009533874A (ja) | 2009-09-17 |
EP2011155A2 (en) | 2009-01-07 |
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