CN113506825A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN113506825A
CN113506825A CN202110631068.XA CN202110631068A CN113506825A CN 113506825 A CN113506825 A CN 113506825A CN 202110631068 A CN202110631068 A CN 202110631068A CN 113506825 A CN113506825 A CN 113506825A
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photoresist
layer
opening
barrier metal
semiconductor device
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渡边健一
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Sumitomo Electric Device Innovations Inc
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Abstract

一种半导体装置，包括：在半导体基板上形成包含Al的欧姆电极的工序；形成将欧姆电极覆盖的SiN膜的工序；在SiN膜上形成具有与欧姆电极重叠的开口图案的第一光致抗蚀剂的工序；对第一光致抗蚀剂进行紫外线固化的工序；在从开口图案露出的SiN膜形成开口，使欧姆电极的表面露出的工序；在第一光致抗蚀剂上及从开口露出的欧姆电极上形成阻挡金属层的工序；在开口图案内形成第二光致抗蚀剂的工序；对第二光致抗蚀剂进行热处理，利用第二光致抗蚀剂将与开口重叠的阻挡金属层覆盖的工序；及使用第二光致抗蚀剂对阻挡金属层进行蚀刻的工序。

Description

半导体装置
本申请为2019年6月5日提交的、申请号为201910486151.5的、发明名称为“半导体装置的制造方法”的申请的分案申请。
技术领域
本发明涉及半导体装置的制造方法。
背景技术
从导电性等的观点出发，半导体装置的配线及欧姆电极有时使用Al(铝)。例如日本特开平4-162531号公报公开了如下内容，将由Al膜或以Al为主成分的合金膜构成的第一层设置于半导体基板中的扩散层的表面上。
在包含Al的配线及欧姆电极中，处于在半导体装置的制造中产生小丘的倾向。例如，在包含Al的欧姆电极上的阻挡金属膜与覆盖该配线的绝缘膜之间等产生间隙的情况下，在该间隙会产生上述小丘。这样的小丘的产生能成为配线或电极的短路的原因，因此不优选。
发明内容
本发明的一方案的半导体装置的制造方法包括：在半导体基板上形成包含Al的欧姆电极的工序；形成将欧姆电极覆盖的SiN膜的工序；在SiN膜上形成具有与欧姆电极重叠的开口图案的第一光致抗蚀剂的工序；对第一光致抗蚀剂进行紫外线固化的工序；在从开口图案露出的SiN膜形成开口并使欧姆电极的表面在该开口内露出的工序；在第一光致抗蚀剂上及从开口露出的欧姆电极上形成阻挡金属层的工序；在开口图案内形成第二光致抗蚀剂的工序；对第二光致抗蚀剂进行热处理并利用第二光致抗蚀剂将与开口重叠的阻挡金属层覆盖的工序；及使用第二光致抗蚀剂对阻挡金属层进行蚀刻的工序。
附图说明
图1是表示通过实施方式的制造方法制造的半导体装置的一例的剖视图。
图2的(a)～图2的(c)是说明实施方式的半导体装置的一部分的制造方法的图。
图3的(a)～图3的(c)是说明实施方式的半导体装置的一部分的制造方法的图。
图4的(a)、图4的(b)是说明实施方式的半导体装置的一部分的制造方法的图。
图5的(a)～图5的(c)是说明实施方式的半导体装置的一部分的制造方法的图。
具体实施方式
[本公开的实施方式的说明]
首先，列举本公开的实施方式的内容进行说明。
本公开的一实施方式涉及一种半导体装置的制造方法，包括：在半导体基板上形成包含Al的欧姆电极的工序；形成将欧姆电极覆盖的SiN膜的工序；在SiN膜上形成具有与欧姆电极重叠的开口图案的第一光致抗蚀剂的工序；对第一光致抗蚀剂进行紫外线固化的工序；在从开口图案露出的SiN膜形成开口并使欧姆电极的表面在该开口内露出的工序；在第一光致抗蚀剂上及从开口露出的欧姆电极上形成阻挡金属层的工序；在开口图案内形成第二光致抗蚀剂的工序；对第二光致抗蚀剂进行热处理并利用第二光致抗蚀剂将与开口重叠的阻挡金属层覆盖的工序；及使用第二光致抗蚀剂对阻挡金属层进行蚀刻的工序。
也可以是，上述制造方法在对第一光致抗蚀剂进行紫外线固化之前还包括对第一光致抗蚀剂进行热处理的工序。
也可以是，阻挡金属层具有彼此层叠的Ti层、TiWN层及TiW层。
也可以是，SiN膜的厚度为30nm～50nm。
也可以是，第二光致抗蚀剂为紫外线抗蚀剂，对于第二光致抗蚀剂的热处理在140℃以上实施。
[本公开的实施方式的详情]
以下，参照附图，说明本发明的实施方式的半导体装置的制造方法的具体例。需要说明的是，本发明没有限定为这些例示，由权利要求书公开，意图包括与权利要求书等同的意思及范围内的全部变更。在以下的说明中，在附图的说明中，对于同一要素，标注同一标号，省略重复的说明。
图1是表示通过本实施方式的制造方法制造的半导体装置的剖视图。如图1所示，半导体装置1例如是设置在基板2上的场效应晶体管。基板2是晶体生长用的基板。作为基板2，可列举例如SiC基板、GaN基板等半导体基板、或者蓝宝石(Al2O3)基板。在本实施方式中，基板2是半导体基板。
半导体装置1具备半导体层叠体11、绝缘膜12、21、源电极13、漏电极14、栅电极15及阻挡导电层16、17。
半导体层叠体11是在基板2上进行了外延生长的半导体层的层叠体。半导体层叠体11例如从基板2的表面依次包含缓冲层、沟槽层及阻挡层。本实施方式的半导体装置1是高电子迁移率晶体管(HEMT)，通过在沟槽层与阻挡层的界面的沟槽层侧产生二维电子气体(2DEG：Two Dimensional Electron Gas)，从而在沟槽层内形成沟槽区域。缓冲层为例如AlN层，沟槽层为例如GaN层，阻挡层为例如AlGaN层。半导体层叠体11也可以具有位于阻挡层上的间隙层。间隙层为例如GaN层。
绝缘膜21是对半导体层叠体11的表面进行保护的钝化膜，设置在半导体层叠体11上。绝缘膜12是对源电极13、漏电极14及栅电极15进行保护的保护膜。在绝缘膜12设有开口12a、12b。开口12a使源电极13的一部分露出，开口12b使漏电极14的一部分露出。而且，在绝缘膜21中的与栅电极15对应的部位设有开口21a。栅电极15经由该开口21a而与半导体层叠体11接触。绝缘膜21是利用减压CVD法形成的氮化硅(SiN)膜，绝缘膜12是利用等离子体CVD法形成的SiN膜。
源电极13及漏电极14分别与半导体层叠体11的阻挡层接触。源电极13及漏电极14是包含铝(Al)的欧姆电极。源电极13及漏电极14是例如将钽(Ta)层与Al层与Ta层的层叠构造以例如500℃～800℃的温度进行了合金化后的结构。而且，也可以取代Ta层而采用钛(Ti)层。此外，也可以在上述层叠构造上形成金(Au)层。源电极13及漏电极14的表面的一部分由绝缘膜12覆盖。
栅电极15设置在源电极13与漏电极14之间。栅电极15例如包含与半导体层叠体11的间隙层进行肖特基接触(Schottky-contact)的金属，例如具有镍(Ni)层与金(Au)层的层叠构造。在该情况下，Ni层与间隙层进行肖特基接触。
阻挡导电层16是保护源电极13的导电层，设置于开口12a内。阻挡导电层16具有例如彼此层叠的Ti层、TiWN层及TiW层。而且，阻挡导电层17是保护漏电极14的导电层，设置在开口12b内。阻挡导电层16、17的结构彼此相同。
接下来，参照图2～图5，说明本实施方式的半导体装置的制造方法的一部分。图2的(a)～图2的(c)、图3的(a)～图3的(c)、图4的(a)、图4的(b)及图5的(a)～图5的(c)是说明本实施方式的半导体装置1的一部分的制造方法的图。以下，详细说明半导体装置1中包含的作为欧姆电极的源电极13和设置在源电极13上的阻挡导电层16的制造方法。
首先，如图2的(a)所示，在基板2上形成绝缘膜21。首先，利用有机金属气相生长法(Metal Organic Chemical Vapor Deposition：金属有机气相沉积；MOCVD)，在基板2上生长出半导体层叠体11。接下来，在半导体层叠体11上形成绝缘膜21。绝缘膜21是例如通过减压CVD(Low Pressure Chemical Vapor Deposition：低压化学气相沉积；LPCVD)法形成的SiN膜。LPCVD法是通过降低成膜压力并提高成膜温度而形成致密的膜的方法。绝缘膜21的厚度为例如10nm以上且30nm以下。绝缘膜21的成膜温度为例如800℃以上且900℃以下，成膜压力为例如10Pa以上且100Pa以下。
接下来，如图2的(b)所示，在基板2上形成作为包含Al的欧姆电极的源电极13。首先，在绝缘膜21形成开口21b。接下来，将具有依次层叠的Ta层、Al层、Ta层的源极金属堆积在开口21b内。下侧的Ta层的厚度为例如5nm以上且10nm以下，Al层的厚度为例如200nm以上且400nm以下，上侧的Ta层的厚度为例如5nm以上且10nm以下。接下来，通过将源极金属以500℃～800℃进行加热，而对源极金属进行合金化来形成源电极13。虽然未图示，但是在源电极13的形成时也形成漏电极14(参照图1)。源极金属使用例如抗蚀图案(未图示)，通过蒸镀法及提离而形成。该抗蚀图案也可以使用于开口21b的形成。
接下来，如图2的(c)所示，形成将绝缘膜21及源电极13覆盖的绝缘膜12。在本实施方式中，绝缘膜12是通过等离子体CVD法形成的SiN膜。绝缘膜12的成膜温度为例如300℃以上且320℃以下。绝缘膜12的厚度为例如30nm以上且50nm以下。
接下来，如图3的(a)所示，在绝缘膜12上形成具有与源电极13重叠的开口图案31a的第一光致抗蚀剂31。首先，在绝缘膜12上涂布第一光致抗蚀剂31。接下来，对于第一光致抗蚀剂31实施光刻，由此在第一光致抗蚀剂31形成开口图案31a。开口图案31a在第一光致抗蚀剂31中设置于与源电极13重叠的位置。绝缘膜12的一部分在开口图案31a内露出。第一光致抗蚀剂31是例如紫外线抗蚀剂。第一光致抗蚀剂31的厚度为例如1μm以上且2μm以下。
接下来，对第一光致抗蚀剂31进行热处理。例如以120℃以上将第一光致抗蚀剂31加热(烘烤)。通过该烘烤而第一光致抗蚀剂31的流动性上升。由此，如图3的(b)所示，形成开口图案31a的第一光致抗蚀剂31的端部变钝。需要说明的是，由于第一光致抗蚀剂31的表面张力而第一光致抗蚀剂31的向源电极13上的流动受到妨碍。接下来，对第一光致抗蚀剂31进行紫外线固化。在该工序中，对于第一光致抗蚀剂31照射紫外线U。由此，第一光致抗蚀剂31固化，因此在第一光致抗蚀剂31难以发生膨胀等。而且，开口图案31a的形状变化也难以发生。紫外线U是例如波长365nm左右的由汞灯得到的紫外线。
接下来，使用氟系气体对于绝缘膜12的从第一光致抗蚀剂31露出的部分进行干蚀刻。由此，如图3的(c)所示，源电极13的表面的一部分在开口12a内露出。具体而言，源电极13的顶面13a的与开口12a重叠的部分露出。干蚀刻是例如反应性离子蚀刻(Reactive IonEtching；RIE)。作为氟系气体，例如，从由SF6、CF4、CHF3、C3F6、及C2F6构成的组中选择1个以上。RIE装置也可以是电感耦合型(Inductive Coupled Plasma；ICP)的结构。
接下来，如图4的(a)所示，在第一光致抗蚀剂31上及从绝缘膜12的开口12a露出的源电极13上形成阻挡金属层41。例如通过溅射法，形成具有彼此层叠的Ti层、TiWN层、TiW层的阻挡金属层41。阻挡金属层41的一部分在开口12a内与源电极13接触。需要说明的是，Ti层的厚度例如为5nm，TiWN层的厚度例如为300nm，TiW层的厚度例如为6nm。阻挡金属层41堆积于平面时的厚度成为上述各层的厚度之和的程度。然而，例如在阻挡金属层41中，在第一光致抗蚀剂31的侧壁或绝缘膜12的开口12a的侧壁堆积的部分的厚度比上述厚度薄。在本实施方式中，在阻挡金属层41中，位于第一光致抗蚀剂31的侧壁上的部位的厚度为100nm以下。
接下来，如图4的(b)所示，在第一光致抗蚀剂31的开口图案31a内形成第二光致抗蚀剂51。在阻挡金属层41的与开口12a重叠的部分41a上形成第二光致抗蚀剂51。如图4的(b)所示，在阻挡金属层41中也可以是存在于源电极13上的部分41a的一部分从第二光致抗蚀剂51露出。第二光致抗蚀剂51例如与第一光致抗蚀剂31同样是紫外线抗蚀剂。第二光致抗蚀剂51的厚度例如为1μm以上且2μm以下。
接下来，如图5的(a)所示，对第二光致抗蚀剂51进行热处理，利用第二光致抗蚀剂51将与绝缘膜12的开口12a重叠的阻挡金属层41覆盖。例如以140℃以上将第二光致抗蚀剂51加热(烘烤)。从利用第二光致抗蚀剂51覆盖阻挡金属层41中的与源电极13重叠的部分41a的观点出发，烘烤温度也可以比第一光致抗蚀剂31的烘烤温度高。由此，第二光致抗蚀剂51流动，阻挡金属层41的部分41a由第二光致抗蚀剂51覆盖。另一方面，第一光致抗蚀剂31的流动未发生或者实质上未发生。此外，第一光致抗蚀剂31的膨胀等也未发生，或者实质上未发生。这是因为，第一光致抗蚀剂31已经被烘烤，且利用紫外线U而被固化。
接下来，如图5的(b)所示，使用第二光致抗蚀剂51对阻挡金属层41进行蚀刻。使用氟系气体对于阻挡金属层41的从第二光致抗蚀剂51露出的部分进行干蚀刻。由此，形成将源电极13的顶面13a覆盖并将从绝缘膜12的开口12a露出的源电极13覆盖的阻挡导电层16。此时，在阻挡金属层41的源电极13上的部分41a中的从第二光致抗蚀剂51的端部至绝缘膜12的开口12a的缘部之间，源电极13的表面露出。露出的该表面具有阻挡金属层41的厚度程度的宽度。第一光致抗蚀剂31的侧壁部的阻挡金属层41的厚度为100nm以下，因此该源电极13露出的间隙的宽度被抑制为100nm以下。
接下来，如图5的(c)所示，将第一光致抗蚀剂31及第二光致抗蚀剂51除去。在阻挡金属层41的一部分残存于第一光致抗蚀剂31上的情况下，将该一部分通过提离而能够与第一光致抗蚀剂31一起除去。通过实施以上说明的工序，形成源电极13及阻挡导电层16。
经由以上的工序，形成本实施方式的半导体装置1。也可以在形成了半导体装置1之后，进行将该半导体装置1覆盖的层间绝缘膜的形成、将该层间绝缘膜贯通并使阻挡导电层露出的通孔的形成、向该通孔埋入的Au配线层的形成。
根据以上说明的本实施方式的半导体装置1的制造方法，通过实施上述工序，利用流动的第二光致抗蚀剂51能够将阻挡金属层41中的与开口12a重叠的部分41a覆盖。并且，通过将从第二光致抗蚀剂51露出的阻挡金属层41除去，不仅能够将作为包含Al的欧姆电极的源电极13的顶面13a覆盖，而且能够将绝缘膜12与阻挡导电层16之间的间隙抑制成极小的宽度。由此，即使在制造半导体装置1的过程中在之后实施热处理的情况下，或者，即使由于形成将半导体装置1覆盖的层间绝缘膜而对于源电极13产生了应力，也能够防止以源电极13中包含的Al为起因的小丘的产生。
通常，当对于由金属层覆盖的光致抗蚀剂实施烘烤时，光致抗蚀剂膨胀而刺穿金属层。然而，在本实施方式中，第一光致抗蚀剂31在对于第二光致抗蚀剂51的再次的烘烤前，暂时实施烘烤并利用紫外线U固化。因此，在再次烘烤中，第一光致抗蚀剂31的膨胀也不会发生或者实质上未发生。这相当于再次的烘烤温度比第一烘烤温度高的情况。
本实施方式的半导体装置1的制造方法在对第一光致抗蚀剂31进行紫外线固化之前具备对第一光致抗蚀剂31进行热处理的工序。在该情况下，第一光致抗蚀剂31的角被修圆，因此在图4的(a)所示的形成阻挡金属层41时，能够将第一光致抗蚀剂31及绝缘膜12的侧面可靠地覆盖。在未覆盖侧面的状态下进行图5的(a)所示的阻挡金属层41的蚀刻时，使源电极13的表面露出的间隙的宽度扩大。
在本实施方式中，阻挡金属层41具有彼此层叠的Ti层、TiWN层及TiW层。在该情况下，良好地表现出阻挡导电层16、17的阻挡性能。
本发明的半导体装置的制造方法并不局限于上述的实施方式，除此之外能够进行各种变形。例如，在上述实施方式中，说明了对HEMT适用了本发明的例子，但是本发明的制造方法能够适用于HEMT以外的各种场效应晶体管。

Claims (4)

1.一种半导体装置，包括：
半导体基板；
半导体层叠体，所述半导体层叠体在所述半导体基板上；
包含Al的欧姆电极，所述欧姆电极在所述半导体层叠体上；
SiN膜，所述SiN膜覆盖所述欧姆电极；
所述SiN膜中的开口；
阻挡金属层，所述阻挡金属层形成在所述开口内部；以及
间隙，所述间隙在所述开口的缘部和阻挡金属层的端部之间，
其中，所述间隙的宽度小于所述阻挡金属层的厚度。
2.根据权利要求1所述的半导体装置，
其中，所述阻挡金属层包括依次层叠的Ti层、TiWN层以及TiW层。
3.根据权利要求1所述的半导体装置，
其中，所述SiN膜的厚度是在30nm至50nm的范围内。
4.根据权利要求1所述的半导体装置，
其中，所述间隙的宽度是100nm以下。
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