JP2009533874A - 二層パッシベーションを有するトランジスタ及び方法 - Google Patents
二層パッシベーションを有するトランジスタ及び方法 Download PDFInfo
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Abstract
Description
Claims (20)
- 半導体デバイスを形成する方法であって、
主面を有する基板を設けることと、
外面を有するようになされている半導体層を、前記基板の前記主面上に形成することと、
前記外面上に第一のパッシベーション層を設けることと、
上面が依然として前記第一のパッシベーション層により覆われ、かつその側端部が露出されているデバイス・メサを、前記主面上方に形成するように、前記第一のパッシベーション層の一部及び前記半導体層の一部を局所的にエッチングすることと、
少なくとも前記デバイス・メサの前記上面上の前記第一のパッシベーション層及び前記デバイス・メサの前記露出側端部を覆って、第二のパッシベーション層を形成することと、
前記第一及び第二のパッシベーション層を貫通して前記デバイス・メサ上の前記半導体層の前記上面まで、ソース−ドレイン・ビア及びゲート・ビアを設けることと、
前記ソース−ドレイン・ビア内の半導体へのオーミック接続及び前記ゲート・ビア内の半導体へのショットキー接続が得られるように、前記ビア内に導体を形成することと、
を含む方法。 - 前記第一のパッシベーション層の一部及び前記半導体層の一部を局所的にエッチングする前記工程は、前記デバイス・メサから所定距離だけ離間して位置する1つ以上のアラインメント・メサも同時に形成することを更に含む、請求項1に記載の方法。
- 前記第二のパッシベーション層を形成する前記工程の前に、前記1つ以上のアラインメント・メサの少なくとも一部の上に光学的に不透明な材料のアラインメント領域を設けることを更に含む、請求項2に記載の方法。
- ソース−ドレイン・ビア及びゲート・ビアを設ける前記工程は、前記1つ以上のアラインメント・メサの少なくとも1つ内に、前記ソース−ドレイン・ビア又は前記ゲート・ビアを開けるのと同時に、アラインメントパターンを形成することを更に含む、請求項3に記載の方法。
- 半導体層を形成する前記工程は、III−V族化合物を具備する層を形成することを含む、請求項1に記載の方法。
- 半導体層を形成する前記工程は、GaNを具備する層を形成することを含む、請求項1に記載の方法。
- 第一のパッシベーション層を設ける前記工程は、シリコン及び窒素を具備する層を設けることを含む、請求項1に記載の方法。
- 第二のパッシベーション層を設ける前記工程は、シリコン及び窒素を具備する層を設けることを含む、請求項1に記載の方法。
- 前記ビア内に導体を形成する前記工程は、アルミニウムを具備するソース−ドレイン接続部を形成することを含む、請求項1に記載の方法。
- 前記ビア内に導体を形成する前記工程は、Ni又はPtを具備するゲート導体を形成することを含む、請求項1に記載の方法。
- 支持基板と、
位置合わせに用いられる波長において光学的に透明で、前記支持基板上に位置し、かつ前記基板から離間した外面及び前記外面から前記支持基板の方向に延長する側端部を有する半導体と、
前記外面を保護するための、前記外面上の、第一の材料でできた第一の絶縁パッシベーション性薄膜層と、
前記第一の薄膜層の上にあり、かつ前記外面から前記側端部の前記部分に亘って延長する絶縁経路を提供するように前記側端部の一部を覆って延長する、第二の材料でできた第二の絶縁パッシベーション性薄膜層と、
前記第一及び第二の薄膜層を貫通し、前記外面にまで延長するビア開口と、
前記ビア開口内に延長して前記半導体の前記外面への電気的接触を形成し、その上にソース−ドレイン接続部及びゲート接続部を形成する導体と、
前記接続部の一部又は全部から前記第二の薄膜層によって形成された前記絶縁経路上の前記側端部を覆って延長する相互接続部と、
を備える半導体デバイス。 - 前記半導体はGaNである、請求項11に記載のデバイス。
- 前記第一の絶縁パッシベーション性薄膜層は、Si3N4、SiO2、SiOxNy、AlN若しくはAl2O3又はそれらの組合せ若しくは混合物のいずれかを備えている、請求項11に記載のデバイス。
- 前記第二の絶縁パッシベーション性薄膜層は、Si3N4、SiO2、SiOxNy、AlN若しくはAl2O3又はそれらの組合せ若しくは混合物のいずれかを備えている、請求項11に記載のデバイス。
- 半導体デバイスに関連してアラインメントマークを形成する方法であって、
主面を有する基板を設けることと、
前記基板の前記主面上に、位置合わせに用いられる波長において実質的に光学的に透明であり、かつ外面を有するようになされている半導体層を形成することと、
前記外面上に第一の誘電体層を設けることと、
前記主面上方にデバイス領域及びアラインメント領域を形成するように、前記第一の誘電体層の一部及び前記半導体層の一部を局所的にエッチングすることと、
前記アラインメント領域上に、位置合わせに用いられる前記波長において光学的に不透明であるようになされている光学的不透明領域を形成することと、
前記デバイス領域及び前記アラインメント領域上の前記光学的不透明領域を覆って第二の誘電体層を形成することと、
前記デバイス領域上の前記誘電体層内に1つ以上のビアを開口するのと同時に、前記アラインメント領域上の前記第二の誘電体層内にアラインメントパターンを形成することと、
を含む方法。 - 半導体層を形成する前記工程は、GaNを具備する層を形成することを含む、請求項15に記載の方法。
- 光学的不透明領域を形成する前記工程は、シリコンを具備する領域を形成することを含む、請求項15に記載の方法。
- 第一の誘電体層を設ける前記工程は、Si3N4、SiO2、SiOxNy、AlN若しくはAl2O3又はそれらの組合せ若しくは混合物を具備する層を形成することを含む、請求項15に記載の方法。
- 第二の誘電体層を設ける前記工程は、Si3N4、SiO2、SiOxNy、AlN若しくはAl2O3又はそれらの組合せ若しくは混合物を具備する層を形成することを含む、請求項15に記載の方法。
- 前記アラインメント領域上の前記第二の誘電体層内にアラインメントパターンを形成する前記工程は、前記第二の誘電体層の一部及び前記光学的不透明領域の一部をエッチングで除去することを含む、請求項15に記載の方法。
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Application Number | Priority Date | Filing Date | Title |
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US11/404,714 | 2006-04-13 | ||
US11/404,714 US8193591B2 (en) | 2006-04-13 | 2006-04-13 | Transistor and method with dual layer passivation |
PCT/US2007/063775 WO2007121010A2 (en) | 2006-04-13 | 2007-03-12 | Transistor and method with dual layer passivation |
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JP2015023072A (ja) * | 2013-07-17 | 2015-02-02 | 豊田合成株式会社 | 半導体装置 |
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US9029986B2 (en) | 2015-05-12 |
KR20090007318A (ko) | 2009-01-16 |
US8193591B2 (en) | 2012-06-05 |
EP2011155A4 (en) | 2009-09-16 |
US20070241419A1 (en) | 2007-10-18 |
WO2007121010A3 (en) | 2009-01-15 |
WO2007121010A2 (en) | 2007-10-25 |
CN101427379A (zh) | 2009-05-06 |
US20130015462A1 (en) | 2013-01-17 |
JP5345521B2 (ja) | 2013-11-20 |
CN101427379B (zh) | 2010-12-29 |
EP2011155A2 (en) | 2009-01-07 |
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