JP5330184B2 - 電子部品装置 - Google Patents
電子部品装置 Download PDFInfo
- Publication number
- JP5330184B2 JP5330184B2 JP2009232372A JP2009232372A JP5330184B2 JP 5330184 B2 JP5330184 B2 JP 5330184B2 JP 2009232372 A JP2009232372 A JP 2009232372A JP 2009232372 A JP2009232372 A JP 2009232372A JP 5330184 B2 JP5330184 B2 JP 5330184B2
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- Japan
- Prior art keywords
- interposer
- wiring board
- chip
- electronic component
- wiring
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/147—Semiconductor insulating substrates
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009232372A JP5330184B2 (ja) | 2009-10-06 | 2009-10-06 | 電子部品装置 |
| US12/897,082 US8379400B2 (en) | 2009-10-06 | 2010-10-04 | Interposer mounted wiring board and electronic component device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009232372A JP5330184B2 (ja) | 2009-10-06 | 2009-10-06 | 電子部品装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2011082293A JP2011082293A (ja) | 2011-04-21 |
| JP2011082293A5 JP2011082293A5 (enExample) | 2012-08-16 |
| JP5330184B2 true JP5330184B2 (ja) | 2013-10-30 |
Family
ID=43823030
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2009232372A Active JP5330184B2 (ja) | 2009-10-06 | 2009-10-06 | 電子部品装置 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US8379400B2 (enExample) |
| JP (1) | JP5330184B2 (enExample) |
Families Citing this family (63)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8557700B2 (en) | 2008-05-09 | 2013-10-15 | Invensas Corporation | Method for manufacturing a chip-size double side connection package |
| JP4998503B2 (ja) * | 2009-04-07 | 2012-08-15 | パナソニック株式会社 | 電子部品実装システムおよび電子部品実装方法 |
| US9254532B2 (en) | 2009-12-30 | 2016-02-09 | Intel Corporation | Methods of fabricating low melting point solder reinforced sealant and structures formed thereby |
| US8895380B2 (en) | 2010-11-22 | 2014-11-25 | Bridge Semiconductor Corporation | Method of making semiconductor assembly with built-in stiffener and semiconductor assembly manufactured thereby |
| KR101719636B1 (ko) * | 2011-01-28 | 2017-04-05 | 삼성전자 주식회사 | 반도체 장치 및 그 제조 방법 |
| TWI424544B (zh) * | 2011-03-31 | 2014-01-21 | 聯詠科技股份有限公司 | 積體電路裝置 |
| US9627337B2 (en) * | 2011-03-31 | 2017-04-18 | Novatek Microelectronics Corp. | Integrated circuit device |
| US8803269B2 (en) * | 2011-05-05 | 2014-08-12 | Cisco Technology, Inc. | Wafer scale packaging platform for transceivers |
| US20130003336A1 (en) * | 2011-06-28 | 2013-01-03 | Delphi Technologies, Inc. | Machine placeable circuit board interposer |
| KR20130025205A (ko) * | 2011-09-01 | 2013-03-11 | 삼성전자주식회사 | 휴대용 데이터 저장 장치 |
| US8780576B2 (en) * | 2011-09-14 | 2014-07-15 | Invensas Corporation | Low CTE interposer |
| JP5167516B1 (ja) * | 2011-11-30 | 2013-03-21 | 株式会社フジクラ | 部品内蔵基板及びその製造方法並びに部品内蔵基板実装体 |
| US9607921B2 (en) | 2012-01-12 | 2017-03-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package on package interconnect structure |
| US9257333B2 (en) | 2013-03-11 | 2016-02-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structures and methods of forming same |
| US9401308B2 (en) * | 2013-03-12 | 2016-07-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging devices, methods of manufacture thereof, and packaging methods |
| US10015888B2 (en) | 2013-02-15 | 2018-07-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect joint protective layer apparatus and method |
| US9263839B2 (en) | 2012-12-28 | 2016-02-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and method for an improved fine pitch joint |
| US9589862B2 (en) | 2013-03-11 | 2017-03-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structures and methods of forming same |
| US9368398B2 (en) | 2012-01-12 | 2016-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure and method of fabricating same |
| JP5845105B2 (ja) * | 2012-02-17 | 2016-01-20 | キヤノン株式会社 | 電子部品の実装用基板と電子部品を実装した基板 |
| US9082776B2 (en) | 2012-08-24 | 2015-07-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package having protective layer with curved surface and method of manufacturing same |
| CN103050414B (zh) * | 2012-11-28 | 2016-06-29 | 贵州振华风光半导体有限公司 | 三维集成高密度厚薄膜多芯片组件的集成方法 |
| CN103107105B (zh) * | 2012-12-12 | 2015-06-24 | 贵州振华风光半导体有限公司 | 多芯片组件同质键合系统质量一致性改进方法 |
| US9312219B2 (en) * | 2012-12-28 | 2016-04-12 | Dyi-chung Hu | Interposer and packaging substrate having the interposer |
| US8884427B2 (en) | 2013-03-14 | 2014-11-11 | Invensas Corporation | Low CTE interposer without TSV structure |
| JP6196815B2 (ja) * | 2013-06-05 | 2017-09-13 | 新光電気工業株式会社 | 冷却装置及び半導体装置 |
| US20150016045A1 (en) * | 2013-07-11 | 2015-01-15 | Integrated Silicon Solution, Inc. | Memory assembly with processor matching pin-out |
| US9735082B2 (en) * | 2013-12-04 | 2017-08-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC packaging with hot spot thermal management features |
| US9318474B2 (en) * | 2013-12-16 | 2016-04-19 | Apple Inc. | Thermally enhanced wafer level fan-out POP package |
| US10431564B2 (en) * | 2014-01-27 | 2019-10-01 | Mediatek Inc. | Structure and formation method of chip package structure |
| US20150262902A1 (en) * | 2014-03-12 | 2015-09-17 | Invensas Corporation | Integrated circuits protected by substrates with cavities, and methods of manufacture |
| US9355997B2 (en) | 2014-03-12 | 2016-05-31 | Invensas Corporation | Integrated circuit assemblies with reinforcement frames, and methods of manufacture |
| US9165793B1 (en) | 2014-05-02 | 2015-10-20 | Invensas Corporation | Making electrical components in handle wafers of integrated circuit packages |
| US9741649B2 (en) | 2014-06-04 | 2017-08-22 | Invensas Corporation | Integrated interposer solutions for 2D and 3D IC packaging |
| US9252127B1 (en) | 2014-07-10 | 2016-02-02 | Invensas Corporation | Microelectronic assemblies with integrated circuits and interposers with cavities, and methods of manufacture |
| US9601464B2 (en) | 2014-07-10 | 2017-03-21 | Apple Inc. | Thermally enhanced package-on-package structure |
| EP3037810B1 (fr) * | 2014-12-23 | 2017-10-25 | EM Microelectronic-Marin SA | Capteur d'humidite ameliore |
| JP6352447B2 (ja) * | 2014-12-24 | 2018-07-04 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| KR101672622B1 (ko) | 2015-02-09 | 2016-11-03 | 앰코 테크놀로지 코리아 주식회사 | 반도체 디바이스 및 그 제조 방법 |
| US9478504B1 (en) | 2015-06-19 | 2016-10-25 | Invensas Corporation | Microelectronic assemblies with cavities, and methods of fabrication |
| US9859202B2 (en) * | 2015-06-24 | 2018-01-02 | Dyi-chung Hu | Spacer connector |
| CN111315112A (zh) * | 2015-06-26 | 2020-06-19 | 台达电子工业股份有限公司 | 一种用于芯片供电的组装结构、电子设备 |
| US10109593B2 (en) | 2015-07-23 | 2018-10-23 | Apple Inc. | Self shielded system in package (SiP) modules |
| US10163867B2 (en) | 2015-11-12 | 2018-12-25 | Amkor Technology, Inc. | Semiconductor package and manufacturing method thereof |
| US9892962B2 (en) | 2015-11-30 | 2018-02-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer level chip scale package interconnects and methods of manufacture thereof |
| US9721903B2 (en) | 2015-12-21 | 2017-08-01 | Apple Inc. | Vertical interconnects for self shielded system in package (SiP) modules |
| US10461062B2 (en) * | 2016-02-03 | 2019-10-29 | Shindengen Electric Manufacturing Co., Ltd. | Semiconductor device and method for manufacturing semiconductor device |
| JP6972523B2 (ja) * | 2016-09-13 | 2021-11-24 | セイコーエプソン株式会社 | 電子機器 |
| US10079194B1 (en) | 2017-03-07 | 2018-09-18 | Novatek Microelectronics Corp. | Chip on film package |
| JP6903981B2 (ja) * | 2017-03-23 | 2021-07-14 | セイコーエプソン株式会社 | 検出装置 |
| US10181447B2 (en) | 2017-04-21 | 2019-01-15 | Invensas Corporation | 3D-interconnect |
| US10804115B2 (en) | 2017-08-03 | 2020-10-13 | General Electric Company | Electronics package with integrated interconnect structure and method of manufacturing thereof |
| US10541153B2 (en) * | 2017-08-03 | 2020-01-21 | General Electric Company | Electronics package with integrated interconnect structure and method of manufacturing thereof |
| US10541209B2 (en) * | 2017-08-03 | 2020-01-21 | General Electric Company | Electronics package including integrated electromagnetic interference shield and method of manufacturing thereof |
| US10410999B2 (en) | 2017-12-19 | 2019-09-10 | Amkor Technology, Inc. | Semiconductor device with integrated heat distribution and manufacturing method thereof |
| US20190198460A1 (en) * | 2017-12-21 | 2019-06-27 | AP Memory Technology Corp. | Circuit system having compact decoupling structure |
| US11195789B2 (en) * | 2018-11-30 | 2021-12-07 | International Business Machines Corporation | Integrated circuit module with a structurally balanced package using a bottom side interposer |
| JP7103520B2 (ja) * | 2019-06-25 | 2022-07-20 | 株式会社村田製作所 | 複合部品およびその製造方法 |
| JP7513117B2 (ja) * | 2020-12-24 | 2024-07-09 | 株式会社村田製作所 | 複合部品およびその製造方法 |
| JP7669236B2 (ja) * | 2021-09-03 | 2025-04-28 | 富士フイルム株式会社 | 半導体実装構造体 |
| US12040284B2 (en) | 2021-11-12 | 2024-07-16 | Invensas Llc | 3D-interconnect with electromagnetic interference (“EMI”) shield and/or antenna |
| CN114096078B (zh) * | 2021-11-25 | 2023-07-25 | 四川九洲电器集团有限责任公司 | 不耐高温器件的印制板保护罩制备方法、保护罩及应用 |
| US20250046690A1 (en) * | 2023-08-04 | 2025-02-06 | Avago Technologies International Sales Pte. Limited | Hybrid substrates and manufacturing methods thereof |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07263620A (ja) * | 1994-03-22 | 1995-10-13 | Hitachi Ltd | 半導体装置 |
| JPH10284544A (ja) * | 1997-04-10 | 1998-10-23 | Hitachi Ltd | 半導体装置およびその製造方法 |
| JP2000340736A (ja) * | 1999-05-26 | 2000-12-08 | Sony Corp | 半導体装置及びその実装構造、並びにこれらの製造方法 |
| JP2001203318A (ja) * | 1999-12-17 | 2001-07-27 | Texas Instr Inc <Ti> | 複数のフリップチップを備えた半導体アセンブリ |
| JP2002151648A (ja) * | 2000-11-07 | 2002-05-24 | Mitsubishi Electric Corp | 半導体モジュール |
| JP2002314031A (ja) * | 2001-04-13 | 2002-10-25 | Fujitsu Ltd | マルチチップモジュール |
| US6597575B1 (en) * | 2002-01-04 | 2003-07-22 | Intel Corporation | Electronic packages having good reliability comprising low modulus thermal interface materials |
| JP2004071719A (ja) | 2002-08-02 | 2004-03-04 | Sony Corp | インターポーザおよびその製造方法、並びに電子回路装置およびその製造方法 |
| JP2004079745A (ja) | 2002-08-16 | 2004-03-11 | Sony Corp | インターポーザおよびその製造方法、並びに電子回路装置およびその製造方法 |
| JP2004356619A (ja) * | 2003-03-19 | 2004-12-16 | Ngk Spark Plug Co Ltd | 中継基板、半導体素子付き中継基板、中継基板付き基板、半導体素子と中継基板と基板とからなる構造体 |
| JP4330367B2 (ja) * | 2003-04-03 | 2009-09-16 | 新光電気工業株式会社 | インターポーザー及びその製造方法ならびに電子装置 |
| JP2005167159A (ja) * | 2003-12-05 | 2005-06-23 | Toshiba Corp | 積層型半導体装置 |
| JP4205613B2 (ja) * | 2004-03-01 | 2009-01-07 | エルピーダメモリ株式会社 | 半導体装置 |
| JP4343044B2 (ja) * | 2004-06-30 | 2009-10-14 | 新光電気工業株式会社 | インターポーザ及びその製造方法並びに半導体装置 |
| JP4899406B2 (ja) * | 2005-10-12 | 2012-03-21 | 日本電気株式会社 | フリップチップ型半導体装置 |
| US7545029B2 (en) * | 2006-08-18 | 2009-06-09 | Tessera, Inc. | Stack microelectronic assemblies |
| US8018738B2 (en) * | 2008-06-02 | 2011-09-13 | Oracle America, Inc., | Voltage regulator attach for high current chip applications |
-
2009
- 2009-10-06 JP JP2009232372A patent/JP5330184B2/ja active Active
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- 2010-10-04 US US12/897,082 patent/US8379400B2/en active Active
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