JP5144222B2 - 配線基板及びその製造方法 - Google Patents

配線基板及びその製造方法 Download PDF

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Publication number
JP5144222B2
JP5144222B2 JP2007295519A JP2007295519A JP5144222B2 JP 5144222 B2 JP5144222 B2 JP 5144222B2 JP 2007295519 A JP2007295519 A JP 2007295519A JP 2007295519 A JP2007295519 A JP 2007295519A JP 5144222 B2 JP5144222 B2 JP 5144222B2
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JP
Japan
Prior art keywords
wiring board
warp
electronic component
component mounting
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2007295519A
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English (en)
Japanese (ja)
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JP2009123874A (ja
JP2009123874A5 (https=
Inventor
順一 中村
隆春 宮本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2007295519A priority Critical patent/JP5144222B2/ja
Priority to KR20080112374A priority patent/KR101508782B1/ko
Priority to US12/270,143 priority patent/US8119930B2/en
Priority to TW097144031A priority patent/TWI426845B/zh
Priority to CNA2008101809126A priority patent/CN101436578A/zh
Publication of JP2009123874A publication Critical patent/JP2009123874A/ja
Publication of JP2009123874A5 publication Critical patent/JP2009123874A5/ja
Priority to US13/340,979 priority patent/US20120096711A1/en
Application granted granted Critical
Publication of JP5144222B2 publication Critical patent/JP5144222B2/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09136—Means for correcting warpage
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/0929—Conductive planes
    • H05K2201/09354—Ground conductor along edge of main surface
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7424—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self-supporting substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/655—Fan-out layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)
JP2007295519A 2007-11-14 2007-11-14 配線基板及びその製造方法 Active JP5144222B2 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2007295519A JP5144222B2 (ja) 2007-11-14 2007-11-14 配線基板及びその製造方法
KR20080112374A KR101508782B1 (ko) 2007-11-14 2008-11-12 배선기판 및 그 제조방법
US12/270,143 US8119930B2 (en) 2007-11-14 2008-11-13 Wiring board and method for manufacturing the same
CNA2008101809126A CN101436578A (zh) 2007-11-14 2008-11-14 配线基板和制造配线基板的方法
TW097144031A TWI426845B (zh) 2007-11-14 2008-11-14 佈線板及其製造方法
US13/340,979 US20120096711A1 (en) 2007-11-14 2011-12-30 Wiring board and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007295519A JP5144222B2 (ja) 2007-11-14 2007-11-14 配線基板及びその製造方法

Publications (3)

Publication Number Publication Date
JP2009123874A JP2009123874A (ja) 2009-06-04
JP2009123874A5 JP2009123874A5 (https=) 2010-11-04
JP5144222B2 true JP5144222B2 (ja) 2013-02-13

Family

ID=40640741

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007295519A Active JP5144222B2 (ja) 2007-11-14 2007-11-14 配線基板及びその製造方法

Country Status (5)

Country Link
US (2) US8119930B2 (https=)
JP (1) JP5144222B2 (https=)
KR (1) KR101508782B1 (https=)
CN (1) CN101436578A (https=)
TW (1) TWI426845B (https=)

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KR100704919B1 (ko) * 2005-10-14 2007-04-09 삼성전기주식회사 코어층이 없는 기판 및 그 제조 방법
JP5157587B2 (ja) * 2008-03-31 2013-03-06 凸版印刷株式会社 多層配線基板の製造方法
KR100956688B1 (ko) * 2008-05-13 2010-05-10 삼성전기주식회사 인쇄회로기판 및 그 제조방법
WO2010050627A1 (ja) * 2008-10-31 2010-05-06 太陽誘電株式会社 プリント配線板およびその製造方法
JP5193809B2 (ja) * 2008-11-05 2013-05-08 新光電気工業株式会社 配線基板及びその製造方法
JPWO2010064467A1 (ja) * 2008-12-05 2012-05-10 イビデン株式会社 多層プリント配線板、及び、多層プリント配線板の製造方法
KR101042060B1 (ko) * 2009-05-27 2011-06-16 주식회사 코리아써키트 회로기판의 제조방법
KR101037450B1 (ko) * 2009-09-23 2011-05-26 삼성전기주식회사 패키지 기판
US20110114372A1 (en) * 2009-10-30 2011-05-19 Ibiden Co., Ltd. Printed wiring board
JP5001395B2 (ja) * 2010-03-31 2012-08-15 イビデン株式会社 配線板及び配線板の製造方法
US20120032337A1 (en) * 2010-08-06 2012-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Flip Chip Substrate Package Assembly and Process for Making Same
JP5772134B2 (ja) * 2011-03-26 2015-09-02 富士通株式会社 回路基板、その製造方法および半導体装置
JP2013048205A (ja) * 2011-07-25 2013-03-07 Ngk Spark Plug Co Ltd 配線基板の製造方法
JP5653893B2 (ja) * 2011-12-07 2015-01-14 信越化学工業株式会社 積層基板
US20130241058A1 (en) * 2012-03-16 2013-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Wire Bonding Structures for Integrated Circuits
US8987602B2 (en) * 2012-06-14 2015-03-24 Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. Multilayer electronic support structure with cofabricated metal core
US20130337648A1 (en) * 2012-06-14 2013-12-19 Bridge Semiconductor Corporation Method of making cavity substrate with built-in stiffener and cavity
JP2014045025A (ja) * 2012-08-24 2014-03-13 Sony Corp 配線基板及び配線基板の製造方法
CN103857181A (zh) * 2012-12-06 2014-06-11 华为终端有限公司 Pcb板以及具有该pcb板的电子设备
JP2014229761A (ja) * 2013-05-23 2014-12-08 株式会社東芝 電子機器
US9355967B2 (en) 2013-06-24 2016-05-31 Qualcomm Incorporated Stress compensation patterning
JP2015032649A (ja) * 2013-08-01 2015-02-16 イビデン株式会社 配線板の製造方法および配線板
KR20150125424A (ko) * 2014-04-30 2015-11-09 삼성전기주식회사 강연성 인쇄회로기판 및 강연성 인쇄회로기판의 제조 방법
JP6358431B2 (ja) 2014-08-25 2018-07-18 新光電気工業株式会社 電子部品装置及びその製造方法
JP6373219B2 (ja) * 2015-03-31 2018-08-15 太陽誘電株式会社 部品内蔵基板および半導体モジュール
US10177130B2 (en) * 2015-04-01 2019-01-08 Bridge Semiconductor Corporation Semiconductor assembly having anti-warping controller and vertical connecting element in stiffener
US20170064821A1 (en) * 2015-08-31 2017-03-02 Kristof Darmawikarta Electronic package and method forming an electrical package
KR20190019324A (ko) * 2017-08-17 2019-02-27 엘지이노텍 주식회사 통신 모듈
JP2019179831A (ja) 2018-03-30 2019-10-17 新光電気工業株式会社 配線基板、配線基板の製造方法
JP2020031090A (ja) * 2018-08-21 2020-02-27 イビデン株式会社 プリント配線板
CN110958758A (zh) * 2018-09-26 2020-04-03 奥特斯(中国)有限公司 部件承载件及板件
TWI682517B (zh) * 2019-03-12 2020-01-11 力成科技股份有限公司 超薄型晶片封裝結構及其製造方法
KR102698698B1 (ko) * 2019-08-05 2024-08-27 삼성전자주식회사 반도체 패키지 장치
KR20230019650A (ko) * 2021-08-02 2023-02-09 엘지이노텍 주식회사 회로기판
KR20230065808A (ko) * 2021-11-05 2023-05-12 엘지이노텍 주식회사 회로기판 및 이를 포함하는 패키지 기판
JP7841689B2 (ja) * 2022-03-17 2026-04-07 新光電気工業株式会社 配線基板及びその製造方法
KR20250030755A (ko) * 2023-08-25 2025-03-05 엘지이노텍 주식회사 회로 기판 및 이를 포함하는 반도체 패키지
KR20250129421A (ko) * 2024-02-22 2025-08-29 엘지이노텍 주식회사 회로기판 및 반도체 패키지

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JP3635219B2 (ja) 1999-03-11 2005-04-06 新光電気工業株式会社 半導体装置用多層基板及びその製造方法
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JP4553466B2 (ja) * 2000-09-05 2010-09-29 パナソニック株式会社 プリント回路基板
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JP3492348B2 (ja) * 2001-12-26 2004-02-03 新光電気工業株式会社 半導体装置用パッケージの製造方法
TWI315657B (en) 2005-06-07 2009-10-01 Phoenix Prec Technology Corp Reverse build-up structure of circuit board
JP4452222B2 (ja) * 2005-09-07 2010-04-21 新光電気工業株式会社 多層配線基板及びその製造方法
JP5117692B2 (ja) * 2006-07-14 2013-01-16 ルネサスエレクトロニクス株式会社 半導体装置の製造方法

Also Published As

Publication number Publication date
TW200938045A (en) 2009-09-01
JP2009123874A (ja) 2009-06-04
TWI426845B (zh) 2014-02-11
KR101508782B1 (ko) 2015-04-03
KR20090049998A (ko) 2009-05-19
US20120096711A1 (en) 2012-04-26
US8119930B2 (en) 2012-02-21
US20090126982A1 (en) 2009-05-21
CN101436578A (zh) 2009-05-20

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