JP2009123874A - 配線基板及びその製造方法 - Google Patents
配線基板及びその製造方法 Download PDFInfo
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Abstract
【解決手段】第1の絶縁層である絶縁層25と、電子部品11が接続される接続面24Aを有し、絶縁層25に内設された電子部品搭載用パッド24と、絶縁層25に積層された第2の絶縁層である絶縁層31と、絶縁層25,31に設けられ、電子部品搭載用パッド24と電気的に接続されたビア27,33及び配線パターン28と、を有する配線基板本体21を備えた配線基板10であって、絶縁層25に配線基板本体21の反りを低減する反り低減部材22を内設した。
【選択図】図6
Description
図6は、本発明の第1の実施の形態に係る配線基板の断面図である。
図20は、本発明の第2の実施の形態に係る配線基板の断面図であり、図21は、図20に示す配線基板の平面図である。図20及び図21において、第1の実施の形態の配線基板10と同一構成部分には同一符号を付す。
11 電子部品
12 実装基板
13 外部接続端子
14,43 パッド
21,51 配線基板本体
22,56,61,81,85,87 反り低減部材
22B,24B,25A,25B,31A,57A,62A,81A,86A,88A 面
24 電子部品搭載用パッド
24A 接続面
25,31 絶縁層
27,33 ビア
28 配線パターン
34 外部接続用パッド
34A 端子配設面
36,53 ソルダーレジスト層
36A,41,46,53A,72A,72B,93A,93B 開口部
43 パッド
44 配線
57,62,86,88 反り低減部
71 支持体
71A 上面
71B 下面
72,93 レジスト膜
A 電子部品搭載用パッド形成領域
B,E 配線基板形成領域
C,F 切断位置
D 距離
W1,W2 幅
Claims (10)
- 第1の絶縁層と、電子部品が接続される接続面を有し、前記接続面が露出されるように、前記第1の絶縁層に内設された電子部品搭載用パッドと、前記第1の絶縁層に積層された少なくとも一層の第2の絶縁層と、前記第1の絶縁層及び前記少なくとも一層の第2の絶縁層に設けられ、前記電子部品搭載用パッドと電気的に接続されたビア及び配線パターンと、を有する配線基板本体を備えた配線基板であって、
前記第1の絶縁層に前記配線基板本体の反りを低減する反り低減部材を内設したことを特徴とする配線基板。 - 前記電子部品搭載用パッドの接続面は、前記第1の絶縁層の一方の面と略面一となるように構成されており、
前記電子部品搭載用パッドの接続面側に位置する前記反り低減部材の面は、前記第1の絶縁層の一方の面と略面一となるように構成されていることを特徴とする請求項1記載の配線基板。 - 前記反り低減部材は、前記電子部品搭載用パッドと同一平面上に配置されており、
前記反り低減部材の厚さは、前記電子部品搭載用パッドの厚さと略等しく、かつ前記反り低減部材の材料は、前記電子部品搭載用パッドの材料と略同一であることを特徴とする請求項2記載の配線基板。 - 前記反り低減部材は、金属膜であることを特徴とする請求項1ないし3のうち、いずれか一項記載の配線基板。
- 前記電子部品搭載用パッドの形成領域に対応する部分の前記第1の絶縁層よりも外側に位置する前記第1の絶縁層に前記反り低減部材を配置すると共に、前記反り低減部材の形状を平面視額縁形状としたことを特徴とする請求項1ないし4のうち、いずれか一項記載の配線基板。
- 前記反り低減部材は、複数の反り低減部を有し、
前記複数の反り低減部は、他の前記反り低減部から離間するように配置することを特徴とする請求項1ないし5のうち、いずれか一項記載の配線基板。 - 前記第1の絶縁層の一方の面に、前記電子部品搭載用パッドの接続面を露出すると共に、前記電子部品搭載用パッドの接続面側に位置する前記反り低減部材の面を覆うソルダーレジスト層を設けたことを特徴とする請求項1ないし6のうち、いずれか一項記載の配線基板。
- 第1の絶縁層と、電子部品が接続される接続面を有し、前記接続面が露出されるように、前記第1の絶縁層に内設された電子部品搭載用パッドと、前記第1の絶縁層に積層された少なくとも一層の第2の絶縁層と、前記第1の絶縁層及び前記少なくとも一層の第2の絶縁層に設けられ、前記電子部品搭載用パッドと電気的に接続されたビア及び配線パターンとを有した配線基板本体を備えた配線基板の製造方法であって、
導電性を有した支持体上に前記電子部品搭載用パッドと前記配線基板本体の反りを低減する反り低減部材とを同時に形成する電子部品搭載用パッド及び反り低減部材形成工程と、
前記支持体上に、前記電子部品搭載用パッド及び前記反り低減部材を覆うように前記第1の絶縁層を形成する第1の絶縁層形成工程と、
前記第1の絶縁層、前記少なくとも一層の第2の絶縁層、前記ビア、及び前記配線パターンを形成後に、前記支持体を除去する支持体除去工程と、を含むことを特徴とする配線基板の製造方法。 - 前記電子部品搭載用パッド及び前記反り低減部材は、金属膜であり、
前記金属膜は、めっき法により形成することを特徴とする請求項8記載の配線基板の製造方法。 - 前記支持体除去工程後に、前記電子部品搭載用パッドの接続面側に位置する前記第1の絶縁層の面に、前記電子部品搭載用パッドの接続面を露出する開口部を有したソルダーレジスト層を形成するソルダーレジスト層形成工程を設けたことを特徴とする請求項8又は9記載の配線基板の製造方法。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007295519A JP5144222B2 (ja) | 2007-11-14 | 2007-11-14 | 配線基板及びその製造方法 |
KR20080112374A KR101508782B1 (ko) | 2007-11-14 | 2008-11-12 | 배선기판 및 그 제조방법 |
US12/270,143 US8119930B2 (en) | 2007-11-14 | 2008-11-13 | Wiring board and method for manufacturing the same |
TW097144031A TWI426845B (zh) | 2007-11-14 | 2008-11-14 | 佈線板及其製造方法 |
CNA2008101809126A CN101436578A (zh) | 2007-11-14 | 2008-11-14 | 配线基板和制造配线基板的方法 |
US13/340,979 US20120096711A1 (en) | 2007-11-14 | 2011-12-30 | Wiring board and method for manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007295519A JP5144222B2 (ja) | 2007-11-14 | 2007-11-14 | 配線基板及びその製造方法 |
Publications (3)
Publication Number | Publication Date |
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JP2009123874A true JP2009123874A (ja) | 2009-06-04 |
JP2009123874A5 JP2009123874A5 (ja) | 2010-11-04 |
JP5144222B2 JP5144222B2 (ja) | 2013-02-13 |
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JP (1) | JP5144222B2 (ja) |
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JP2009246107A (ja) * | 2008-03-31 | 2009-10-22 | Toppan Printing Co Ltd | 多層配線基板およびその製造方法、並びに半導体パッケージ |
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JP2011216740A (ja) * | 2010-03-31 | 2011-10-27 | Ibiden Co Ltd | 配線板及び配線板の製造方法 |
JP2012204699A (ja) * | 2011-03-26 | 2012-10-22 | Fujitsu Ltd | 回路基板、その製造方法および半導体装置 |
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001015638A (ja) * | 1999-06-30 | 2001-01-19 | Mitsumi Electric Co Ltd | Icパッケージの基板 |
JP2002076530A (ja) * | 2000-09-05 | 2002-03-15 | Matsushita Electric Ind Co Ltd | プリント回路基板およびプリント回路基板の製造方法 |
JP2003197809A (ja) * | 2001-12-26 | 2003-07-11 | Shinko Electric Ind Co Ltd | 半導体装置用パッケージ及びその製造方法並びに半導体装置 |
JP2008021921A (ja) * | 2006-07-14 | 2008-01-31 | Nec Electronics Corp | 配線基板、半導体装置およびその製造方法 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1895589A3 (en) * | 1997-10-17 | 2013-04-03 | Ibiden Co., Ltd. | Semiconductor package substrate |
JP3635219B2 (ja) | 1999-03-11 | 2005-04-06 | 新光電気工業株式会社 | 半導体装置用多層基板及びその製造方法 |
US6291268B1 (en) * | 2001-01-08 | 2001-09-18 | Thin Film Module, Inc. | Low cost method of testing a cavity-up BGA substrate |
TWI315657B (en) | 2005-06-07 | 2009-10-01 | Phoenix Prec Technology Corp | Reverse build-up structure of circuit board |
JP4452222B2 (ja) * | 2005-09-07 | 2010-04-21 | 新光電気工業株式会社 | 多層配線基板及びその製造方法 |
-
2007
- 2007-11-14 JP JP2007295519A patent/JP5144222B2/ja active Active
-
2008
- 2008-11-12 KR KR20080112374A patent/KR101508782B1/ko active IP Right Grant
- 2008-11-13 US US12/270,143 patent/US8119930B2/en active Active
- 2008-11-14 CN CNA2008101809126A patent/CN101436578A/zh active Pending
- 2008-11-14 TW TW097144031A patent/TWI426845B/zh active
-
2011
- 2011-12-30 US US13/340,979 patent/US20120096711A1/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001015638A (ja) * | 1999-06-30 | 2001-01-19 | Mitsumi Electric Co Ltd | Icパッケージの基板 |
JP2002076530A (ja) * | 2000-09-05 | 2002-03-15 | Matsushita Electric Ind Co Ltd | プリント回路基板およびプリント回路基板の製造方法 |
JP2003197809A (ja) * | 2001-12-26 | 2003-07-11 | Shinko Electric Ind Co Ltd | 半導体装置用パッケージ及びその製造方法並びに半導体装置 |
JP2008021921A (ja) * | 2006-07-14 | 2008-01-31 | Nec Electronics Corp | 配線基板、半導体装置およびその製造方法 |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2009246107A (ja) * | 2008-03-31 | 2009-10-22 | Toppan Printing Co Ltd | 多層配線基板およびその製造方法、並びに半導体パッケージ |
WO2010050627A1 (ja) * | 2008-10-31 | 2010-05-06 | 太陽誘電株式会社 | プリント配線板およびその製造方法 |
US8963016B2 (en) | 2008-10-31 | 2015-02-24 | Taiyo Yuden Co., Ltd. | Printed wiring board and method for manufacturing same |
JP2011216740A (ja) * | 2010-03-31 | 2011-10-27 | Ibiden Co Ltd | 配線板及び配線板の製造方法 |
JP2012204699A (ja) * | 2011-03-26 | 2012-10-22 | Fujitsu Ltd | 回路基板、その製造方法および半導体装置 |
JP2013120840A (ja) * | 2011-12-07 | 2013-06-17 | Shin Etsu Chem Co Ltd | 積層基板 |
JP2014229761A (ja) * | 2013-05-23 | 2014-12-08 | 株式会社東芝 | 電子機器 |
KR20220008932A (ko) * | 2017-08-17 | 2022-01-21 | 엘지이노텍 주식회사 | 통신 모듈 |
KR102409692B1 (ko) | 2017-08-17 | 2022-06-16 | 엘지이노텍 주식회사 | 통신 모듈 |
US10412828B1 (en) | 2018-03-30 | 2019-09-10 | Shinko Electric Industries Co., Ltd. | Wiring substrate |
JP2020031090A (ja) * | 2018-08-21 | 2020-02-27 | イビデン株式会社 | プリント配線板 |
Also Published As
Publication number | Publication date |
---|---|
KR20090049998A (ko) | 2009-05-19 |
US20120096711A1 (en) | 2012-04-26 |
TW200938045A (en) | 2009-09-01 |
US8119930B2 (en) | 2012-02-21 |
KR101508782B1 (ko) | 2015-04-03 |
JP5144222B2 (ja) | 2013-02-13 |
US20090126982A1 (en) | 2009-05-21 |
TWI426845B (zh) | 2014-02-11 |
CN101436578A (zh) | 2009-05-20 |
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