JP4914474B2 - 多層印刷回路基板の製造方法 - Google Patents
多層印刷回路基板の製造方法 Download PDFInfo
- Publication number
- JP4914474B2 JP4914474B2 JP2009225566A JP2009225566A JP4914474B2 JP 4914474 B2 JP4914474 B2 JP 4914474B2 JP 2009225566 A JP2009225566 A JP 2009225566A JP 2009225566 A JP2009225566 A JP 2009225566A JP 4914474 B2 JP4914474 B2 JP 4914474B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- circuit board
- printed circuit
- multilayer printed
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0364—Conductor shape
- H05K2201/0367—Metallic bump or raised conductor not used as solder bump
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09481—Via in pad; Pad over filled via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0502—Patterning and lithography
- H05K2203/054—Continuous temporary metal layer over resist, e.g. for selective electroplating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
- H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
- Y10T156/11—Methods of delaminating, per se; i.e., separating at bonding face
- Y10T156/1168—Gripping and pulling work apart during delaminating
Description
11 金属層
12 分離層
13 接着剤
14 分離部材
15 CCL
20,120 最外絶縁層
25 シード層
27 マスク
30,130 外部接続パッド
35 回路パターン
40,140 ビルドアップ層
41,141 レイヤ
42,142 パターン
43,143 ビア
50,150 第1ソルダレジスト層
55,155 第2ソルダレジスト層
Claims (7)
- 一面に外部接続パッドが形成された多層印刷回路基板を形成する方法であって、
前記外部接続パッドに対応する開口部が形成された最外絶縁層を形成する工程と、
前記最外絶縁層に前記外部接続パッド及び回路パターンに対応する開口部が形成されたマスクを形成する工程と、
前記最外絶縁層の開口部と前記マスクの開口部に前記外部接続パッド及び前記回路パターンを形成する工程と、
前記マスクを除去する工程と、
前記外部接続パッド及び前記回路パターンをカバーするように、前記最外絶縁層にレイヤを積層してビルドアップ層を形成する工程と、
前記ビルドアップ層の上に第1ソルダレジスト層を形成する工程と、
前記最外絶縁層の前記ビルドアップ層が形成された面の反対面に第2ソルダレジスト層を形成する工程と、
前記外部接続パッドが露出するように、前記第2ソルダレジスト層に開口部を形成する工程と、を含む多層印刷回路基板の製造方法。 - 前記最外絶縁層は、キャリアの上に形成され、
前記第2ソルダレジスト層を形成する工程の前に、
前記キャリアを除去する工程をさらに含むことを特徴とする請求項1に記載の多層印刷回路基板の製造方法。 - 前記キャリアは、表面に金属層を含むことを特徴とする請求項2に記載の多層印刷回路基板の製造方法。
- 前記金属層は、前記外部接続パッドとは異なるエッチング液によりエッチングされる物質を含むことを特徴とする請求項3に記載の多層印刷回路基板の製造方法。
- 前記最外絶縁層の開口部は、
前記キャリアの前記金属層に前記最外絶縁層を積層し、
前記最外絶縁層を選択的にレーザードリルで除去することにより形成されることを特徴とする請求項3から4の何れか1項に記載の多層印刷回路基板の製造方法。 - 前記ビルドアップ層は、その周縁に、完成された多層印刷回路基板では除去されるダミー領域を含み、
前記キャリアは、前記金属層の下に、前記ダミー領域に相当する部分にだけ接着剤が塗布された分離層を含み、
前記キャリアを除去する工程は、前記ダミー領域を切断することにより前記分離層の接着剤塗布部分を除去する工程と、
前記金属層をエッチングする工程と、を含むことを特徴とする請求項3から5の何れか1項に記載の多層印刷回路基板の製造方法。 - 前記マスクを形成する工程の前に、シード層を形成する工程をさらに含み、
前記外部接続パッド及び前記回路パターンを形成する工程が、前記シード層の上にメッキ方式で行われ、
前記マスクを除去する工程の後に、前記シード層を除去する工程をさらに含むことを特徴とする請求項1から6の何れか1項に記載の多層印刷回路基板の製造方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020080117921A KR101025520B1 (ko) | 2008-11-26 | 2008-11-26 | 다층 인쇄회로기판 제조방법 |
KR10-2008-0117921 | 2008-11-26 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2010130003A JP2010130003A (ja) | 2010-06-10 |
JP4914474B2 true JP4914474B2 (ja) | 2012-04-11 |
Family
ID=42195191
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009225566A Expired - Fee Related JP4914474B2 (ja) | 2008-11-26 | 2009-09-29 | 多層印刷回路基板の製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20100126765A1 (ja) |
JP (1) | JP4914474B2 (ja) |
KR (1) | KR101025520B1 (ja) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101077380B1 (ko) * | 2009-07-31 | 2011-10-26 | 삼성전기주식회사 | 인쇄회로기판 및 그 제조방법 |
KR101055462B1 (ko) | 2010-01-07 | 2011-08-08 | 삼성전기주식회사 | 인쇄회로기판 제조용 캐리어와 그 제조방법 및 이를 이용한 인쇄회로기판의 제조방법 |
KR101282965B1 (ko) * | 2010-11-05 | 2013-07-08 | 주식회사 두산 | 신규 인쇄회로기판 및 이의 제조방법 |
KR101216926B1 (ko) * | 2011-07-12 | 2012-12-28 | 삼성전기주식회사 | 캐리어 부재와 그 제조방법 및 이를 이용한 인쇄회로기판의 제조방법 |
JP5902931B2 (ja) * | 2011-12-06 | 2016-04-13 | 新光電気工業株式会社 | 配線基板の製造方法、及び、配線基板製造用の支持体 |
KR101970291B1 (ko) | 2012-08-03 | 2019-04-18 | 삼성전자주식회사 | 반도체 패키지의 제조 방법 |
US8963336B2 (en) | 2012-08-03 | 2015-02-24 | Samsung Electronics Co., Ltd. | Semiconductor packages, methods of manufacturing the same, and semiconductor package structures including the same |
KR101814113B1 (ko) * | 2012-11-02 | 2018-01-02 | 삼성전기주식회사 | 인쇄회로기판의 제조방법 |
KR20150062556A (ko) * | 2013-11-29 | 2015-06-08 | 삼성전기주식회사 | 휨방지 부재가 구비된 스트립 레벨 기판 및 이의 제조 방법 |
JP6133227B2 (ja) * | 2014-03-27 | 2017-05-24 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
US10163867B2 (en) | 2015-11-12 | 2018-12-25 | Amkor Technology, Inc. | Semiconductor package and manufacturing method thereof |
KR101761502B1 (ko) * | 2016-01-06 | 2017-07-25 | 앰코 테크놀로지 코리아 주식회사 | 반도체 디바이스 및 그 제조 방법 |
KR101983191B1 (ko) * | 2017-07-25 | 2019-05-28 | 삼성전기주식회사 | 인덕터 및 그 제조방법 |
US10410999B2 (en) | 2017-12-19 | 2019-09-10 | Amkor Technology, Inc. | Semiconductor device with integrated heat distribution and manufacturing method thereof |
CN112105174B (zh) * | 2019-06-18 | 2022-02-22 | 宏启胜精密电子(秦皇岛)有限公司 | 电路板及其制造方法 |
KR102212836B1 (ko) * | 2020-05-19 | 2021-02-05 | 주식회사 코멧네트워크 | 세라믹 회로 기판의 제조방법 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3635219B2 (ja) * | 1999-03-11 | 2005-04-06 | 新光電気工業株式会社 | 半導体装置用多層基板及びその製造方法 |
US6876554B1 (en) * | 1999-09-02 | 2005-04-05 | Ibiden Co., Ltd. | Printing wiring board and method of producing the same and capacitor to be contained in printed wiring board |
JP2002290031A (ja) * | 2001-03-23 | 2002-10-04 | Ngk Spark Plug Co Ltd | 配線基板およびその製造方法 |
JP3800405B2 (ja) * | 2001-12-26 | 2006-07-26 | 富士通株式会社 | 多層回路基板の製造方法 |
JP2004311912A (ja) | 2002-12-06 | 2004-11-04 | Sony Corp | 回路基板モジュール及びその製造方法 |
WO2006040847A1 (ja) * | 2004-10-14 | 2006-04-20 | Ibiden Co., Ltd. | プリント配線板及びプリント配線板の製造方法 |
JP2008078683A (ja) * | 2005-08-29 | 2008-04-03 | Shinko Electric Ind Co Ltd | 多層配線基板 |
TWI295550B (en) * | 2005-12-20 | 2008-04-01 | Phoenix Prec Technology Corp | Structure of circuit board and method for fabricating the same |
JP4764731B2 (ja) * | 2006-01-30 | 2011-09-07 | 富士通株式会社 | 多層構造のプリント配線基板 |
KR100782407B1 (ko) * | 2006-10-30 | 2007-12-05 | 삼성전기주식회사 | 회로기판 제조방법 |
KR100887382B1 (ko) | 2007-03-28 | 2009-03-06 | 삼성전기주식회사 | 인쇄회로기판 제조방법 |
JP2009016818A (ja) * | 2007-07-04 | 2009-01-22 | Samsung Electro-Mechanics Co Ltd | 多層印刷回路基板及びその製造方法 |
-
2008
- 2008-11-26 KR KR1020080117921A patent/KR101025520B1/ko not_active IP Right Cessation
-
2009
- 2009-09-29 JP JP2009225566A patent/JP4914474B2/ja not_active Expired - Fee Related
- 2009-09-29 US US12/569,104 patent/US20100126765A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
JP2010130003A (ja) | 2010-06-10 |
KR20100059227A (ko) | 2010-06-04 |
US20100126765A1 (en) | 2010-05-27 |
KR101025520B1 (ko) | 2011-04-04 |
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