JP2019179831A - 配線基板、配線基板の製造方法 - Google Patents
配線基板、配線基板の製造方法 Download PDFInfo
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- JP2019179831A JP2019179831A JP2018067912A JP2018067912A JP2019179831A JP 2019179831 A JP2019179831 A JP 2019179831A JP 2018067912 A JP2018067912 A JP 2018067912A JP 2018067912 A JP2018067912 A JP 2018067912A JP 2019179831 A JP2019179831 A JP 2019179831A
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- wiring
- layer
- solder resist
- opening
- resist layer
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- 238000004519 manufacturing process Methods 0.000 title claims description 12
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- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 10
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- 239000010931 gold Substances 0.000 description 13
- 239000002184 metal Substances 0.000 description 12
- 229910052751 metal Inorganic materials 0.000 description 12
- 238000005476 soldering Methods 0.000 description 10
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- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
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- H01L23/49838—Geometry or layout
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- H01L23/562—Protection against mechanical damage
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- H05K1/00—Printed circuits
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- H05K1/00—Printed circuits
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- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
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Abstract
Description
なお、添付図面は、理解を容易にするために構成要素を拡大して示している場合がある。構成要素の寸法比率は実際のものと、または別の図面中のものと異なる場合がある。また、断面図では、理解を容易にするために、一部の部材のハッチングを梨地模様に代えて示し、一部の部材のハッチングを省略している場合がある。
以下、第一実施形態を図1〜図12に従って説明する。
図1に示すように、半導体装置1は、配線基板10、電子部品としての半導体素子41、導電性補強板51、導電性接着層52を有している。
配線層12は、基板本体11の上面11aに形成されている。配線層14は、基板本体11の下面11bに形成されている。配線層12,14の材料としては、例えば銅(Cu)等を用いることができる。
(比較例)
先ず、比較例について、図5を用いて説明する。なお、上述した本実施形態と同じ部材については本実施形態と同じ符号を用いて説明する。
図5に示すように、配線基板100のソルダーレジスト層101は、単一の樹脂絶縁層である。ソルダーレジスト層101の開口部101Yによりグランド配線22の一部がグランドパッド17として露出され、そのグランドパッド17に導電性接着層52を介して導電性補強板51が接続されている。
次に、本実施形態を説明する。
図4において、左部分は本実施形態の配線基板10の一部平面図であり、右部分は導電性補強板51と信号配線21及びグランド配線22の接続を示す一部断面図である。
次に、本実施形態の配線基板10、半導体装置1の製造方法について説明する。
なお、ここでは、図1及び図2に示すソルダーレジスト層31及び絶縁被膜32の形成と、導電性補強板51の接着について説明する。また、説明の便宜上、最終的に配線基板10、半導体装置1の各構成要素となる部分には、最終的な構成要素の符号を付して説明する。
図12に示すように、配線基板10に、導電性接着層52を介して導電性補強板51を接着する。例えば、導電性補強板51の下面に導電性ペーストを塗布し、その導電性ペーストを絶縁被膜32に向けて導電性補強板51を配線基板10に向けて横圧する。これにより、導電性ペーストが絶縁被膜32及びソルダーレジスト層31の開口部32Y,31Yの内部と、欠損部31Eを覆う絶縁被膜32の凹部内に充填される。その後、例えば加熱によって導電性ペーストを硬化させることで、導電性接着層52が形成される。そして、絶縁被膜32及びソルダーレジスト層31の開口部32Y,31Yの内部の接続部52Vを有する導電性接着層52により、導電性補強板51がグランド配線22に接続される。
(1)配線基板10は、基板本体11と、基板本体11の上面の配線層12と、配線層12を覆うソルダーレジスト層31と、ソルダーレジスト層31の上面を覆う絶縁被膜32とを有している。導電性補強板51は、導電性接着層52を介して絶縁被膜32の上面に接着される。配線層12は、少なくとも一部が導電性補強板51の直下に配設される第1配線21(信号配線21)及び第2配線22(グランド配線22)を備える。ソルダーレジスト層31は、導電性補強板51の直下に第2配線22の一部を露出する開口部31Yを有する。絶縁被膜32は、導電性補強板51の直下に開口部31Yと連通して第2配線22の一部を露出する開口部32Yを有する。
以下、第二実施形態を図13〜図14に従って説明する。
なお、この実施形態において、上記実施形態と同じ構成部材については同じ符号を付してその説明の一部又は全てを省略する。
ソルダーレジスト層31は、基板本体11の上面と配線層12の一部を覆うように設けられている。配線層12は、第1配線21(信号配線21)と第2配線22(グランド配線22)とを含む。本実施形態において、絶縁被膜32Aは、導電性補強板51に対応する領域であり、接続された導電性補強板51の直下のソルダーレジスト層31の領域を覆うように形成されている。
図13に示すように、導電性補強板51は、導電性接着層52を介して絶縁被膜32Aの上面に接続されている。本実施形態において、絶縁被膜32Aは、絶縁性インク材からなる。
本実施形態において、絶縁被膜32Aは、第一実施形態と同様に、ソルダーレジスト層31に生じた欠損部31E(図4参照)を覆う、つまり欠損部31Eにより露出する信号配線21を覆うことができる。このため、信号配線21とグランド配線22との間の短絡を低減することができる。
(2−1)配線基板10Aは、第1配線21(信号配線21)及び第2配線22(グランド配線22)を覆うソルダーレジスト層31と、ソルダーレジスト層31の上面の一部を覆う絶縁被膜32Aとを備えている。絶縁被膜32Aは、ソルダーレジスト層31に生じた欠損部を覆う、つまり欠損部により露出する信号配線21を覆うことができる。このため、信号配線21とグランド配線22との間の短絡を低減することができる。
・第一実施形態において、絶縁被膜32を、ソルダーレジスト層31の一部、具体的には導電性接着層52を介して導電性補強板51が接続される領域を覆うように形成してもよい。
・上記各実施形態に対して、絶縁被膜32,32Aとしては、ソルダーレジスト層31に生じる欠損部(ボイド)を覆うことができればよく、例えば、エポキシ樹脂などの熱硬化性樹脂を用いることができる。このように、ソルダーレジスト層31と絶縁被膜32,32Aとを備える構成とすることで、グランド配線22以外の配線が露出し難くなり、グランド配線22との間の短絡を低減することができる。
11 基板本体
12 配線層
16 接続パッド
17 グランドパッド
21 第1配線(信号配線)
22 第2配線(グランド配線)
31 ソルダーレジスト層
32,32A 絶縁被膜
31Y 開口部
32Y 開口部
51 導電性補強板
52 導電性接着層
Claims (11)
- 導電性接着層を介して導電性補強板が接着される配線基板であって、
基板本体と、
前記基板本体の上面の第1配線及び第2配線と、
前記第1配線及び前記第2配線を覆い、前記第2配線の一部を露出する第1開口部及び前記第1配線の一部を露出する欠損部を有するソルダーレジスト層と、
前記ソルダーレジスト層の上面の少なくとも一部及び前記欠損部の内壁と前記欠損部により露出する前記第1配線を覆い、前記第1開口部と連通して前記第2配線の一部を露出する第2開口部を有する絶縁被膜と、
を備え、
前記導電性補強板は、前記第1配線及び前記第2配線の少なくとも一部と、前記第1開口部及び前記第2開口部をまたぐように前記絶縁被膜の上面に接着されるものであること、
を特徴とする配線基板。 - 前記導電性接着層を介して前記絶縁被膜の上面に接着された前記導電性補強板を備え、
前記第2配線は、前記第1開口部及び前記第2開口部の中の前記導電性接着層を介して前記導電性補強板と電気的に接続され、
前記第1配線は前記導電性補強板と電気的に絶縁されること
を特徴とする請求項1に記載の配線基板。 - 前記ソルダーレジスト層は樹脂絶縁層であり、前記絶縁被膜はアルミナ絶縁層であることを特徴とする請求項1又は2に記載の配線基板。
- 前記ソルダーレジスト層は樹脂絶縁層であり、前記絶縁被膜は絶縁性インク材であることを特徴とする請求項1又は2に記載の配線基板。
- 前記絶縁被膜は、前記ソルダーレジスト層の上面全体を覆うことを特徴とする請求項1〜4の何れか1項に記載の配線基板。
- 前記ソルダーレジスト層及び前記絶縁被膜は、電子部品を接続する接続パッドとして前記第1配線の一部を露出する開口部を有すること、を特徴とする請求項5に記載の配線
基板。 - 前記絶縁被膜は、枠状に前記ソルダーレジスト層を覆うように形成され、
前記ソルダーレジスト層は、電子部品を接続する接続パッドとして前記第1配線の一部を露出する開口部を有すること、を特徴とする請求項1〜4の何れか1項に記載の配線基板。 - 導電性接着層を介して導電性補強板が接着される配線基板の製造方法であって、
基板本体の上面に第1配線及び第2配線を形成する工程と、
前記基板本体の上面の第1配線及び第2配線と、
前記第1配線及び前記第2配線を覆い、前記第2配線の一部を露出する第1開口部を有するソルダーレジスト層を形成する工程と、
前記ソルダーレジスト層の上面の少なくとも一部及び前記ソルダーレジスト層に生じる欠損部の内壁と前記欠損部により露出する前記第1配線を覆い、前記第1開口部と連通して前記第2配線の一部を露出する第2開口部を有する絶縁被膜を形成する工程と、
を備え、
前記導電性補強板は、前記第1配線及び前記第2配線の少なくとも一部と、前記第1開口部及び前記第2開口部をまたぐように前記絶縁被膜の上面に接着されるものであること、
を特徴とする配線基板の製造方法。 - 前記導電性接着層を介して前記導電性補強板を前記絶縁被膜の上面に接着する工程を備え、
前記第2配線は、前記第1開口部及び前記第2開口部の中の前記導電性接着層を介して前記導電性補強板と電気的に接続され、
前記第1配線は前記導電性補強板と電気的に絶縁されること
を特徴とする請求項8に記載の配線基板の製造方法。 - 樹脂絶縁層により前記ソルダーレジスト層を形成し、アルミナ絶縁層により前記絶縁被膜を形成することを特徴とする請求項8又は9に記載の配線基板の製造方法。
- 樹脂絶縁層により前記ソルダーレジスト層を形成し、絶縁性インク材により前記絶縁被膜を形成することを特徴とする請求項8又は9に記載の配線基板の製造方法。
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