JP2009176791A - 配線基板及びその製造方法 - Google Patents
配線基板及びその製造方法 Download PDFInfo
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- JP2009176791A JP2009176791A JP2008011072A JP2008011072A JP2009176791A JP 2009176791 A JP2009176791 A JP 2009176791A JP 2008011072 A JP2008011072 A JP 2008011072A JP 2008011072 A JP2008011072 A JP 2008011072A JP 2009176791 A JP2009176791 A JP 2009176791A
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/101—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by casting or moulding of conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/107—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0272—Adaptations for fluid transport, e.g. channels, holes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09563—Metal filled via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
- H05K3/4061—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in inorganic insulating substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
- Y10T156/10—Methods of surface bonding and/or assembly therefor
- Y10T156/1052—Methods of surface bonding and/or assembly therefor with cutting, punching, tearing or severing
- Y10T156/1056—Perforating lamina
Abstract
【解決手段】一方の面に所要のパターン形状に形成された凹部RPを有する基材11と、基材12とを、凹部RPが形成されている側の面を内側にして直接貼り合わせた構造体を作製し、その構造体の所要の箇所に、厚さ方向に貫通し、かつ、凹部RPと連通するようにスルーホールTHを形成し、その表面に絶縁層13を形成した後、スルーホールTH及び凹部RPに導電性材料14,15を充填する。
【選択図】図5
Description
11,12…シリコン板(基材)、
13,22,23…絶縁層、
14,14a,14b…スルーホール電極(導体/導電性材料)、
15,15a,15b…内部配線(導体/導電性材料)、
20,21,24,25…配線層、
26,27…ソルダレジスト層(保護膜/絶縁層)、
30…配線基板(半導体パッケージ)、
RP…凹部、
TH…スルーホール。
Claims (5)
- コア基板の少なくとも一方の面側に配線層を積み重ねてなる配線基板であって、
前記コア基板が、一方の面に所要のパターン形状に形成された凹部を有する平板状の第1の基材と、平板状の第2の基材とを、前記凹部が形成されている側の面を内側にして直接貼り合わせた構造体からなり、該構造体の所要の箇所に、厚さ方向に貫通し、かつ、前記凹部と連通するよう形成されたスルーホールと、前記凹部とに、導電性材料が一体的に充填されていることを特徴とする配線基板。 - 前記第1の基材及び第2の基材はそれぞれシリコン板からなり、前記導電性材料は、各シリコン板の表面に形成された絶縁層を介して前記スルーホール及び前記凹部に充填されていることを特徴とする請求項1に記載の配線基板。
- 前記コア基板内の前記凹部に充填されている部分の導体は、グランド用配線もしくは電源用配線として割り当てられていることを特徴とする請求項1に記載の配線基板。
- 所要の厚さに薄化された平板状の第1の基材の一方の面に、所要のパターン形状に凹部を形成する工程と、
所要の厚さに薄化された平板状の第2の基材を用意し、該第2の基材を、前記第1の基材の前記凹部が形成されている側の面と直接接合により貼り合わせる工程と、
貼り合わされた構造体の所要の箇所に、その厚さ方向に貫通し、かつ、前記凹部と連通するようにスルーホールを形成する工程と、
前記スルーホールが形成された構造体の表面に絶縁層を形成する工程と、
前記絶縁層で覆われた構造体に対し、前記スルーホール及び前記凹部に導電性材料を充填する工程とを含むことを特徴とする配線基板の製造方法。 - 前記第1の基材及び第2の基材を直接接合により貼り合わせる工程と前記スルーホールを形成する工程との間に、貼り合わされた構造体の一方の面に、所要の箇所に開口部を有するレジスト層を形成する工程を含み、
該レジスト層を形成する工程において、前記開口部は、平面的に見てその周縁部分が前記凹部の周縁部分と一部重なるような大きさを有して形成されており、該開口部の形状に従って前記スルーホールが形成されていることを特徴とする請求項4に記載の配線基板の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008011072A JP5138395B2 (ja) | 2008-01-22 | 2008-01-22 | 配線基板及びその製造方法 |
US12/349,780 US8119932B2 (en) | 2008-01-22 | 2009-01-07 | Wiring board and method of manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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JP2008011072A JP5138395B2 (ja) | 2008-01-22 | 2008-01-22 | 配線基板及びその製造方法 |
Publications (3)
Publication Number | Publication Date |
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JP2009176791A true JP2009176791A (ja) | 2009-08-06 |
JP2009176791A5 JP2009176791A5 (ja) | 2010-12-24 |
JP5138395B2 JP5138395B2 (ja) | 2013-02-06 |
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JP2008011072A Active JP5138395B2 (ja) | 2008-01-22 | 2008-01-22 | 配線基板及びその製造方法 |
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JP (1) | JP5138395B2 (ja) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011091308A (ja) * | 2009-10-26 | 2011-05-06 | Denso Corp | 配線基板 |
JP2013512583A (ja) * | 2009-12-17 | 2013-04-11 | インテル コーポレイション | 多層ガラスコアを含む集積回路デバイス用基板、及びその製造方法 |
JP2014007243A (ja) * | 2012-06-22 | 2014-01-16 | Kyocera Corp | 配線基板および電子装置 |
US9001520B2 (en) | 2012-09-24 | 2015-04-07 | Intel Corporation | Microelectronic structures having laminated or embedded glass routing structures for high density packaging |
US9445496B2 (en) | 2012-03-07 | 2016-09-13 | Intel Corporation | Glass clad microelectronic substrate |
US9686861B2 (en) | 2009-12-17 | 2017-06-20 | Intel Corporation | Glass core substrate for integrated circuit devices and methods of making the same |
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TWI459876B (zh) * | 2009-10-27 | 2014-11-01 | Panasonic Corp | 導體圖案的形成方法及導體圖案 |
KR20130072608A (ko) * | 2011-12-22 | 2013-07-02 | 삼성전자주식회사 | 디스플레이 장치 |
JP2014179430A (ja) * | 2013-03-14 | 2014-09-25 | Ibiden Co Ltd | 半導体素子搭載用多層プリント配線板 |
KR101607981B1 (ko) * | 2013-11-04 | 2016-03-31 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지용 인터포저 및 이의 제조 방법, 제조된 인터포저를 이용한 반도체 패키지 |
JP2015185754A (ja) * | 2014-03-25 | 2015-10-22 | 株式会社東芝 | 半導体装置 |
CN109803481B (zh) * | 2017-11-17 | 2021-07-06 | 英业达科技有限公司 | 多层印刷电路板及制作多层印刷电路板的方法 |
JP2020188209A (ja) * | 2019-05-16 | 2020-11-19 | イビデン株式会社 | プリント配線板とプリント配線板の製造方法 |
CN112954889A (zh) * | 2021-01-20 | 2021-06-11 | 江门崇达电路技术有限公司 | 一种沉铜工艺测试板及其制作方法 |
US11881461B2 (en) * | 2021-09-30 | 2024-01-23 | Texas Instruments Incorporated | Electric field control for bond pads in semiconductor device package |
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Cited By (15)
Publication number | Priority date | Publication date | Assignee | Title |
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CN102056403A (zh) * | 2009-10-26 | 2011-05-11 | 株式会社电装 | 印制线路板 |
US8426747B2 (en) | 2009-10-26 | 2013-04-23 | Denso Corporation | Printed wiring board |
CN102056403B (zh) * | 2009-10-26 | 2013-09-04 | 株式会社电装 | 印制线路板 |
JP2011091308A (ja) * | 2009-10-26 | 2011-05-06 | Denso Corp | 配線基板 |
JP2013512583A (ja) * | 2009-12-17 | 2013-04-11 | インテル コーポレイション | 多層ガラスコアを含む集積回路デバイス用基板、及びその製造方法 |
US9420707B2 (en) | 2009-12-17 | 2016-08-16 | Intel Corporation | Substrate for integrated circuit devices including multi-layer glass core and methods of making the same |
US10070524B2 (en) | 2009-12-17 | 2018-09-04 | Intel Corporation | Method of making glass core substrate for integrated circuit devices |
US9686861B2 (en) | 2009-12-17 | 2017-06-20 | Intel Corporation | Glass core substrate for integrated circuit devices and methods of making the same |
US9761514B2 (en) | 2009-12-17 | 2017-09-12 | Intel Corporation | Substrate for integrated circuit devices including multi-layer glass core and methods of making the same |
US9793201B2 (en) | 2012-03-07 | 2017-10-17 | Intel Corporation | Glass clad microelectronic substrate |
US9445496B2 (en) | 2012-03-07 | 2016-09-13 | Intel Corporation | Glass clad microelectronic substrate |
JP2014007243A (ja) * | 2012-06-22 | 2014-01-16 | Kyocera Corp | 配線基板および電子装置 |
US9001520B2 (en) | 2012-09-24 | 2015-04-07 | Intel Corporation | Microelectronic structures having laminated or embedded glass routing structures for high density packaging |
US10008452B2 (en) | 2012-09-24 | 2018-06-26 | Intel Corporation | Microelectronic structures having laminated or embedded glass routing structures for high density packaging |
US9642248B2 (en) | 2012-09-24 | 2017-05-02 | Intel Corporation | Microelectronic structures having laminated or embedded glass routing structures for high density packaging |
Also Published As
Publication number | Publication date |
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US20090183910A1 (en) | 2009-07-23 |
JP5138395B2 (ja) | 2013-02-06 |
US8119932B2 (en) | 2012-02-21 |
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