JP4544860B2 - 半導体素子の接触部の製造方法、並びにこれを含む液晶表示装置用薄膜トランジスタアレイ基板の製造方法 - Google Patents
半導体素子の接触部の製造方法、並びにこれを含む液晶表示装置用薄膜トランジスタアレイ基板の製造方法 Download PDFInfo
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- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
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- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
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Description
22 ゲート線
24 ゲートパッド
26 ゲート電極
30 ゲート絶縁膜
40 半導体層
50 非晶質シリコン層
55、54、56 抵抗接触層
60 導電体層
62 データ線
65 ソース電極
66 ドレーン電極
68 データパッド
70 保護膜
72、74、76、78、330 接触孔
73 低誘電率絶縁膜
75、320 有機絶縁膜
82 画素電極
84 補助ゲートパッド
88 補助データパッド
100 基板
110、112、114 感光膜
200 第1配線
300 層間絶縁膜
310 下部絶縁膜
320 上部絶縁膜(有機絶縁膜)
400 第2配線
Claims (10)
- 基板の上部に第1配線を形成する段階と、
前記第1配線の上部に下部膜を形成する段階と、
前記下部膜の上部に、感光性有機物質を用いて上部膜を形成する段階と、
半透過領域を有するマスクで前記上部膜を露光及び現像して接触孔を形成しようとする領域には上部膜が除去され、その周辺の領域には第1厚さの上部膜が存在し、その他の領域には前記第1厚さより厚い第2厚さを有する上部膜を形成する段階と、
前記上部膜をエッチングマスクとして用いて前記下部膜をエッチングして、前記第1配線を露出する接触孔を形成する段階と、
アッシング工程で前記上部膜のうちの第1厚さを有する部分を除去して、前記接触孔を定義する前記下部膜の上部面を露出する段階と、
前記接触孔を介して前記第1配線と連結される第2配線を形成する段階と、
を含み、前記下部膜のエッチング時には前記第1厚さを有する部分の下部でアンダーカットが発生する、半導体素子の製造方法。 - 前記下部膜は、窒化ケイ素又は酸化ケイ素からなる絶縁膜で形成する、請求項1に記載の半導体素子の製造方法。
- 絶縁基板の上にゲート線、前記ゲート線に連結されているゲート電極、及び前記ゲート線の一端に連結されているゲートパッドを含むゲート配線を形成する段階と、
前記ゲート配線上にゲート絶縁膜を積層する段階と、
前記ゲート絶縁膜上にパターニングした半導体層を形成する段階と、
前記ゲート絶縁膜上に、前記ゲート線と交差するデータ線、前記データ線と連結されており、パターニングした半導体層に隣接するソース電極、前記ゲート電極に対して前記ソース電極の対向側に位置するドレーン電極、及び前記データ線の一端に連結されているデータパッドを含むデータ配線を形成する段階と、
下部絶縁膜を積層する段階と、
前記下部絶縁膜の上部に感光性有機絶縁物質で形成された上部絶縁膜を形成する段階と、
半透過領域を有するマスクで前記上部絶縁膜を露光及び現像して接触孔を形成しようとする領域には前記上部絶縁膜が除去され、その周辺の領域には第1厚さの上部絶縁膜が存在し、その他の領域には前記第1厚さより厚い第2厚さを有する上部絶縁膜を形成する段階と、
前記上部絶縁膜をエッチングマスクとして用いて前記下部絶縁膜をエッチングして、前記ゲートパッド又は前記データパッドを露出する第1接触孔を形成する段階と、
アッシング工程を行って、前記上部絶縁膜のうちの第1厚さを有する部分を除去し、前記第1接触孔の周辺の前記下部絶縁膜の上部面を露出する段階と、
前記第1接触孔を介して前記ゲートパッド又は前記データパッドに連結される補助パッドを形成する段階と、
を含み、前記下部絶縁膜のエッチング時には前記第1厚さを有する部分の下部でアンダーカットが発生する、液晶表示装置用薄膜トランジスタアレイ基板の製造方法。 - 前記下部絶縁膜は、窒化ケイ素又は酸化ケイ素からなる絶縁膜で形成する、請求項3に記載の液晶表示装置用薄膜トランジスタアレイ基板の製造方法。
- 第1厚さと第2厚さを有する前記上部絶縁膜を形成する段階の後、前記上部絶縁膜をエッチングマスクとして用いて前記下部絶縁膜をエッチングして、前記ドレーン電極を露出する第2接触孔を形成する段階と、
アッシング工程を行って、前記上部絶縁膜のうちの第1厚さを有する部分を除去し、前記第2接触孔の周辺の前記下部絶縁膜の上部面を露出する段階と、
前記補助パッドと同一層に、前記第2接触孔を介して前記ドレーン電極と電気的に連結される画素電極を形成する段階をさらに含む、請求項3に記載の液晶表示装置用薄膜トランジスタアレイ基板の製造方法。 - 前記第2接触孔は前記第1接触孔と共に形成し、前記第2接触孔の周辺の前記上部絶縁膜は他の部分より薄く形成する、請求項5に記載の液晶表示装置用薄膜トランジスタアレイ基板の製造方法。
- 前記液晶表示装置用薄膜トランジスタアレイ基板は、液晶物質を溜める封印材が形成される部分を有し、
前記部分の前記上部絶縁膜は他の部分より薄く形成する段階と、
前記アッシング工程で前記部分の前記上部絶縁膜を除去する段階とをさらに含む、請求項4に記載の液晶表示装置用薄膜トランジスタアレイ基板の製造方法。 - 前記データ配線及び前記半導体層は、部分的に厚さの異なる感光膜パターンを用いた写真エッチング工程で共に形成する、請求項3に記載の液晶表示装置用薄膜トランジスタアレイ基板の製造方法。
- 基板の上部に第1配線を形成する段階と、
前記第1配線の上部に下部膜及び上部膜を形成する段階と、
前記上部膜の上部に、感光性有機物質を用いて感光膜を形成する段階と、
半透過領域を有するマスクで前記感光膜を露光及び現像して接触孔を形成しようとする領域には感光膜が除去され、その周辺の領域には第1厚さの感光膜が存在し、その他の領域には前記第1厚さより厚い第2厚さを有する感光膜パターンを形成する段階と、
前記感光膜パターンをエッチングマスクとして用いて前記上部膜及び前記下部膜をエッチングして、前記第1配線を露出する接触孔を形成する段階と、
アッシング工程で前記感光膜のうちの第1厚さを有する部分を除去して、前記感光膜をマスクとして前記上部膜をエッチングして前記接触孔を定義する前記下部膜の上部面を露出する段階と、
前記接触孔を介して前記第1配線と連結される第2配線を形成する段階と、
を含み、前記下部膜のエッチング時には前記第1厚さを有する部分の下部でアンダーカットが発生する、半導体素子の製造方法。 - 前記下部膜または上記上部膜は、窒化ケイ素又は酸化ケイ素からなる絶縁膜で形成する、請求項9に記載の半導体素子の製造方法。
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