JP2005510064A - 半導体素子の接触部及びその製造方法、並びにこれを含む液晶表示装置用薄膜トランジスタアレイ基板及びその製造方法 - Google Patents
半導体素子の接触部及びその製造方法、並びにこれを含む液晶表示装置用薄膜トランジスタアレイ基板及びその製造方法 Download PDFInfo
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Abstract
Description
22 ゲート線
24 ゲートパッド
26 ゲート電極
30 ゲート絶縁膜
40 半導体層
50 非晶質シリコン層
55、54、56 抵抗接触層
60 導電体層
62 データ線
65 ソース電極
66 ドレーン電極
68 データパッド
70 保護膜
72、74、76、78、330 接触孔
73 低誘電率絶縁膜
75、320 有機絶縁膜
82 画素電極
84 補助ゲートパッド
88 補助データパッド
100 基板
110、112、114 感光膜
200 第1配線
300 層間絶縁膜
310 下部絶縁膜
320 上部絶縁膜(有機絶縁膜)
400 第2配線
Claims (20)
- 基板の上部に第1配線を形成する段階と、
前記第1配線の上部に下部膜を形成する段階と、
前記下部膜の上部に、感光性有機物質を用いて感光膜パターンを形成する段階と、
前記感光膜パターンをエッチングマスクとして用いて前記下部膜をエッチングして、前記第1配線を露出する接触孔を形成する段階と、
アッシング工程で前記感光膜パターンの一部を除去して、前記接触孔を定義する前記下部膜の境界線を露出する段階と、
前記接触孔を介して前記第1配線と連結される第2配線を形成する段階とを含む、半導体素子の製造方法。 - 前記下部膜は、窒化ケイ素又は酸化ケイ素からなる絶縁膜で形成する、請求項1に記載の半導体素子の製造方法。
- 前記下部膜は、導電膜で形成する、請求項1に記載の半導体素子の製造方法。
- 前記下部膜は、第1絶縁膜及び第2絶縁膜で形成し、
前記下部膜の境界線を露出する段階の後に、前記感光膜パターンで覆わない前記第2絶縁膜をエッチングして、前記接触孔で前記第1絶縁膜の境界線を露出する段階をさらに含む、請求項1に記載の半導体素子の製造方法。 - 前記接触孔の周辺の前記感光膜パターンは他の部分より薄く形成する、請求項1に記載の半導体素子の製造方法。
- 基板と、
前記基板の上部に形成されている第1配線と、
前記第1配線を覆い、前記第1配線を露出する第1接触孔を有する下部絶縁膜と、
前記下部絶縁膜の上部に形成されており、前記第1接触孔の境界線を露出する第2接触孔を有する上部絶縁膜と、
前記上部絶縁膜の上部に形成されており、前記第1及び第2接触孔を介して前記第1配線に連結される第2配線とを含む、半導体素子。 - 前記上部絶縁膜は、有機絶縁膜又は4.0以下の低い誘電率を有し、化学気相蒸着で形成される低誘電率絶縁膜からなる、請求項6に記載の半導体素子。
- 絶縁基板の上にゲート線、前記ゲート線に連結されているゲート電極、及び前記ゲート線の一端に連結されているゲートパッドを含むゲート配線を形成する段階と、
ゲート絶縁膜を積層する段階と、
半導体層を形成する段階と、
前記ゲート線と交差するデータ線、前記データ線と連結されており、前記ゲート電極に隣接するソース電極、前記ゲート電極に対して前記ソース電極の対向側に位置するドレーン電極、及び前記データ線の一端に連結されているデータパッドを含むデータ配線を形成する段階と、
絶縁膜を積層する段階と、
前記絶縁膜の上部に感光性有機絶縁膜パターンを形成する段階と、
前記有機絶縁膜パターンをエッチングマスクとして用いて前記絶縁膜をエッチングして、前記ゲートパッド又は前記データパッドを露出する第1接触孔を形成する段階と、
アッシング工程を行って、前記第1接触孔で前記絶縁膜の境界線を露出する段階と、
前記第1接触孔を介して前記ゲートパッド又は前記データパッドに連結される補助パッドを形成する段階とを含む、液晶表示装置用薄膜トランジスタアレイ基板の製造方法。 - 前記第1接触孔の周辺の前記有機絶縁膜パターンは他の部分より薄く形成する、請求項8に記載の液晶表示装置用薄膜トランジスタアレイ基板の製造方法。
- 前記絶縁膜は、第1及び第2絶縁膜で形成し、
前記絶縁膜の境界線を露出する段階の後に、前記有機絶縁膜パターンで覆わない前記第2絶縁膜をエッチングする段階と、
前記有機絶縁膜パターンを除去する段階とをさらに含む、請求項9に記載の液晶表示装置用液晶表示装置用薄膜トランジスタアレイ基板の製造方法。 - 前記第2絶縁膜は、4.0以下の低い誘電率を有し、化学気相蒸着で形成される低誘電率絶縁膜からなる、請求項10に記載の液晶表示装置用薄膜トランジスタアレイ基板の製造方法。
- 前記有機絶縁膜パターンは、前記絶縁膜と共に前記ドレーン電極を露出する第2接触孔を有し、
前記補助パッドと同一層に、前記第2接触孔を介して前記ドレーン電極と電気的に連結される画素電極を形成する段階をさらに含む、請求項8に記載の液晶表示装置用薄膜トランジスタアレイ基板の製造方法。 - 前記第2接触孔は前記第1接触孔と共に形成し、前記第2接触孔の周辺の前記有機絶縁膜パターンは他の部分より薄く形成する、請求項12に記載の液晶表示装置用薄膜トランジスタアレイ基板の製造方法。
- 前記液晶表示装置用薄膜トランジスタアレイ基板は、液晶物質を溜める封印材が形成される部分を有し、
前記部分の前記有機絶縁膜パターンは他の部分より薄く形成する段階と、
前記アッシング工程で前記部分の前記有機絶縁膜パターンを除去する段階とをさらに含む、請求項8に記載の液晶表示装置用薄膜トランジスタアレイ基板の製造方法。 - 前記データ配線及び前記半導体層は、部分的に厚さの異なる感光膜パターンを用いた写真エッチング工程で共に形成する、請求項8に記載の液晶表示装置用薄膜トランジスタアレイ基板の製造方法。
- 基板の上に形成されており、ゲート線、前記ゲート線に連結されているゲート電極、前記ゲート線の一端に連結されているゲートパッドを含むゲート配線と、
前記ゲート配線を覆うゲート絶縁膜と、
前記ゲート絶縁膜の上部に形成されている半導体層と、
前記ゲート絶縁膜又は半導体層の上部に形成されており、データ線、前記データ線に連結されており、前記ゲート電極に隣接するソース電極、前記ゲート電極に対して前記ソース電極の対向側に位置するドレーン電極、及び前記データ線の一端に連結されているデータパッドを含むデータ配線と、
前記半導体層を覆い、前記ゲートパッド又は前記データパッドを露出する第1接触孔を有する層間絶縁膜と、
前記層間絶縁膜の上部に形成されており、前記第1接触孔を介して前記ゲートパッド又は前記データパッドに連結されている補助パッドとを含む液晶表示装置用薄膜トランジスタアレイ基板であって、
前記層間絶縁膜は、下部絶縁膜と、前記下部絶縁膜の上部に形成されている上部絶縁膜とから構成され、前記第1接触孔で、前記下部絶縁膜の境界線は前記上部絶縁膜の境界線の内側に形成されて前記下部絶縁膜が露出されている、液晶表示装置用薄膜トランジスタアレイ基板。 - 前記上部絶縁膜は、有機絶縁膜又は4.0以下の低い誘電率を有し、化学気相蒸着で形成される低誘電率絶縁膜からなる、請求項16に記載の液晶表示装置用薄膜トランジスタアレイ基板。
- 前記層間絶縁膜は、前記ドレーン電極を露出する第2接触孔を有し、
前記補助パッドと同一層に、前記第2接触孔を介して前記ドレーン電極と電気的に連結される画素電極をさらに含む、請求項16に記載の液晶表示装置用薄膜トランジスタアレイ基板。 - 前記第2接触孔で、前記下部絶縁膜の境界線は前記上部絶縁膜の境界線の内側に形成されて前記下部絶縁膜が露出されている、請求項16に記載の液晶表示装置用薄膜トランジスタアレイ基板。
- 前記液晶表示装置用薄膜トランジスタアレイ基板は、液晶物質を溜める封印材が形成される部分を有し、前記部分は前記上部絶縁膜が除去されている、請求項16に記載の液晶表示装置用薄膜トランジスタアレイ基板。
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PCT/KR2002/001878 WO2003043094A1 (en) | 2001-11-12 | 2002-10-08 | Contact portion of semiconductor device, and thin film transistor array panel for display device including the contact portion |
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US20040241987A1 (en) | 2004-12-02 |
WO2003043094A1 (en) | 2003-05-22 |
US7061015B2 (en) | 2006-06-13 |
CN1491442A (zh) | 2004-04-21 |
CN100411193C (zh) | 2008-08-13 |
KR20030039112A (ko) | 2003-05-17 |
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