JP4198201B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP4198201B2
JP4198201B2 JP02757496A JP2757496A JP4198201B2 JP 4198201 B2 JP4198201 B2 JP 4198201B2 JP 02757496 A JP02757496 A JP 02757496A JP 2757496 A JP2757496 A JP 2757496A JP 4198201 B2 JP4198201 B2 JP 4198201B2
Authority
JP
Japan
Prior art keywords
voltage
power supply
static memory
memory cell
switch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP02757496A
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English (en)
Japanese (ja)
Other versions
JPH0951042A (ja
Inventor
清男 伊藤
孝一郎 石橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP02757496A priority Critical patent/JP4198201B2/ja
Priority to TW085105869A priority patent/TW302535B/zh
Priority to KR1019960018651A priority patent/KR100373223B1/ko
Priority to US08/655,823 priority patent/US5668770A/en
Publication of JPH0951042A publication Critical patent/JPH0951042A/ja
Priority to US08/929,890 priority patent/US5894433A/en
Priority to US09/232,851 priority patent/US6108262A/en
Priority to US09/472,147 priority patent/US6215716B1/en
Priority to US09/790,878 priority patent/US6388936B2/en
Priority to KR1020010015077A priority patent/KR100395261B1/ko
Priority to US10/122,328 priority patent/US6469950B2/en
Priority to US10/243,870 priority patent/US6639828B2/en
Priority to KR1020030032779A priority patent/KR100395260B1/ko
Priority to US10/637,693 priority patent/US6917556B2/en
Priority to US11/148,354 priority patent/US7251183B2/en
Priority to US11/724,158 priority patent/US7706205B2/en
Application granted granted Critical
Publication of JP4198201B2 publication Critical patent/JP4198201B2/ja
Priority to US12/722,222 priority patent/US7978560B2/en
Priority to US13/154,919 priority patent/US8325553B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/18—Peripheral circuit regions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/903—FET configuration adapted for use as static memory cell

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
JP02757496A 1995-06-02 1996-02-15 半導体装置 Expired - Fee Related JP4198201B2 (ja)

Priority Applications (17)

Application Number Priority Date Filing Date Title
JP02757496A JP4198201B2 (ja) 1995-06-02 1996-02-15 半導体装置
TW085105869A TW302535B (enExample) 1995-06-02 1996-05-17
KR1019960018651A KR100373223B1 (ko) 1995-06-02 1996-05-30 반도체장치
US08/655,823 US5668770A (en) 1995-06-02 1996-05-31 Static memory cell having independent data holding voltage
US08/929,890 US5894433A (en) 1995-06-02 1997-09-15 Static memory cell having independent data holding voltage
US09/232,851 US6108262A (en) 1995-06-02 1999-01-19 Static memory cell having independent data holding voltage
US09/472,147 US6215716B1 (en) 1995-06-02 1999-12-27 Static memory cell having independent data holding voltage
US09/790,878 US6388936B2 (en) 1995-06-02 2001-02-23 Static memory cell having independent data holding voltage
KR1020010015077A KR100395261B1 (ko) 1995-06-02 2001-03-23 반도체장치
US10/122,328 US6469950B2 (en) 1995-06-02 2002-04-16 Static memory cell having independent data holding voltage
US10/243,870 US6639828B2 (en) 1995-06-02 2002-09-16 Static memory cell having independent data holding voltage
KR1020030032779A KR100395260B1 (ko) 1995-06-02 2003-05-23 반도체장치
US10/637,693 US6917556B2 (en) 1995-06-02 2003-08-11 Static memory cell having independent data holding voltage
US11/148,354 US7251183B2 (en) 1995-06-02 2005-06-09 Static random access memory having a memory cell operating voltage larger than an operating voltage of a peripheral circuit
US11/724,158 US7706205B2 (en) 1995-06-02 2007-03-15 Static memory cell having independent data holding voltage
US12/722,222 US7978560B2 (en) 1995-06-02 2010-03-11 Static memory cell having independent data holding voltage
US13/154,919 US8325553B2 (en) 1995-06-02 2011-06-07 Static memory cell having independent data holding voltage

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP13634995 1995-06-02
JP7-136349 1995-06-02
JP02757496A JP4198201B2 (ja) 1995-06-02 1996-02-15 半導体装置

Related Child Applications (4)

Application Number Title Priority Date Filing Date
JP2000245519A Division JP2001093993A (ja) 1995-06-02 2000-08-08 半導体装置
JP2006075769A Division JP2006179182A (ja) 1995-06-02 2006-03-20 半導体装置
JP2006075768A Division JP4367715B2 (ja) 1995-06-02 2006-03-20 半導体装置
JP2006075770A Division JP2006221796A (ja) 1995-06-02 2006-03-20 半導体装置

Publications (2)

Publication Number Publication Date
JPH0951042A JPH0951042A (ja) 1997-02-18
JP4198201B2 true JP4198201B2 (ja) 2008-12-17

Family

ID=26365515

Family Applications (1)

Application Number Title Priority Date Filing Date
JP02757496A Expired - Fee Related JP4198201B2 (ja) 1995-06-02 1996-02-15 半導体装置

Country Status (4)

Country Link
US (12) US5668770A (enExample)
JP (1) JP4198201B2 (enExample)
KR (3) KR100373223B1 (enExample)
TW (1) TW302535B (enExample)

Families Citing this family (103)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4198201B2 (ja) 1995-06-02 2008-12-17 株式会社ルネサステクノロジ 半導体装置
US5831910A (en) * 1995-08-18 1998-11-03 Hitachi, Ltd. Semiconductor integrated circuit utilizing overdriven differential amplifiers
JP3560266B2 (ja) * 1995-08-31 2004-09-02 株式会社ルネサステクノロジ 半導体装置及び半導体データ装置
JPH10188571A (ja) * 1996-12-25 1998-07-21 Toshiba Corp 半導体メモリ回路装置及び半導体メモリセルの書き込み方法
US6115307A (en) * 1997-05-19 2000-09-05 Micron Technology, Inc. Method and structure for rapid enablement
US6157974A (en) * 1997-12-23 2000-12-05 Lsi Logic Corporation Hot plugging system which precharging data signal pins to the reference voltage that was generated from voltage detected on the operating mode signal conductor in the bus
JP3467416B2 (ja) * 1998-04-20 2003-11-17 Ｎｅｃエレクトロニクス株式会社 半導体記憶装置及びその製造方法
US5986962A (en) * 1998-07-23 1999-11-16 International Business Machines Corporation Internal shadow latch
JP4030198B2 (ja) * 1998-08-11 2008-01-09 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
US6122760A (en) * 1998-08-25 2000-09-19 International Business Machines Corporation Burn in technique for chips containing different types of IC circuitry
US6141240A (en) * 1998-09-17 2000-10-31 Texas Instruments Incorporated Apparatus and method for static random access memory array
KR100472727B1 (ko) * 1998-12-24 2005-05-27 주식회사 하이닉스반도체 저전압용 인버터 체인 회로_
US6040991A (en) * 1999-01-04 2000-03-21 International Business Machines Corporation SRAM memory cell having reduced surface area
US6181608B1 (en) * 1999-03-03 2001-01-30 Intel Corporation Dual Vt SRAM cell with bitline leakage control
FR2793064B1 (fr) * 1999-04-30 2004-01-02 St Microelectronics Sa Memoire a courant de fuite reduit
JP2001167581A (ja) * 1999-12-09 2001-06-22 Mitsubishi Electric Corp 半導体メモリ
JP4530464B2 (ja) * 2000-03-09 2010-08-25 ルネサスエレクトロニクス株式会社 半導体集積回路
JP4044721B2 (ja) * 2000-08-15 2008-02-06 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
JP5004386B2 (ja) * 2000-09-18 2012-08-22 三洋電機株式会社 表示装置及びその駆動方法
US6529400B1 (en) * 2000-12-15 2003-03-04 Lsi Logic Corporation Source pulsed, dynamic threshold complementary metal oxide semiconductor static RAM cells
DE10104701B4 (de) * 2001-02-02 2014-04-17 Qimonda Ag Verfahren zum Einschreiben von Daten in einen Speicher eines DRAM und DRAM mit einem Speicher
US6946901B2 (en) * 2001-05-22 2005-09-20 The Regents Of The University Of California Low-power high-performance integrated circuit and related methods
JP2003051191A (ja) * 2001-05-31 2003-02-21 Mitsubishi Electric Corp 半導体記憶装置
JP5240792B2 (ja) * 2001-06-05 2013-07-17 ルネサスエレクトロニクス株式会社 半導体装置
JP2002368135A (ja) * 2001-06-12 2002-12-20 Hitachi Ltd 半導体記憶装置
JP2003059273A (ja) 2001-08-09 2003-02-28 Hitachi Ltd 半導体記憶装置
JP4327411B2 (ja) * 2001-08-31 2009-09-09 株式会社ルネサステクノロジ 半導体装置
JP2003132683A (ja) * 2001-10-23 2003-05-09 Hitachi Ltd 半導体装置
JP2003151267A (ja) * 2001-11-09 2003-05-23 Fujitsu Ltd 半導体記憶装置
JP2003188351A (ja) * 2001-12-17 2003-07-04 Hitachi Ltd 半導体集積回路
US6639827B2 (en) * 2002-03-12 2003-10-28 Intel Corporation Low standby power using shadow storage
US6894356B2 (en) * 2002-03-15 2005-05-17 Integrated Device Technology, Inc. SRAM system having very lightly doped SRAM load transistors for improving SRAM cell stability and method for making the same
CA2479682A1 (en) 2002-03-27 2003-10-09 The Regents Of The University Of California Low-power high-performance memory cell and related methods
US6724648B2 (en) * 2002-04-05 2004-04-20 Intel Corporation SRAM array with dynamic voltage for reducing active leakage power
TWI283406B (en) * 2002-08-28 2007-07-01 Brilliance Semiconductor Inc Charging-free ultra-low power virtual dynamic random access memory
JP2004158084A (ja) 2002-11-05 2004-06-03 Renesas Technology Corp 半導体集積回路装置
US6990011B2 (en) * 2003-05-09 2006-01-24 Stmicroelectronics, Inc. Memory circuit and method for corrupting stored data
US6791886B1 (en) * 2003-05-30 2004-09-14 International Business Machines Corporation SRAM cell with bootstrapped power line
JP4282388B2 (ja) * 2003-06-30 2009-06-17 株式会社東芝 半導体記憶装置
US7224600B2 (en) * 2004-01-08 2007-05-29 Stmicroelectronics, Inc. Tamper memory cell
US6985380B2 (en) * 2004-03-26 2006-01-10 Intel Corporation SRAM with forward body biasing to improve read cell stability
CA2482254A1 (en) * 2004-04-07 2005-10-07 Mold-Masters Limited Modular injection nozzle having a thermal barrier
US20050289017A1 (en) * 2004-05-19 2005-12-29 Efraim Gershom Network transaction system and method
US7349681B2 (en) * 2004-07-13 2008-03-25 Taiwan Semiconductor Manufacturing Company, Ltd. Self-biased high-speed receiver
JP4291751B2 (ja) * 2004-07-23 2009-07-08 富士通マイクロエレクトロニクス株式会社 半導体記憶装置
US7196925B1 (en) * 2004-08-26 2007-03-27 Cypress Semiconductor Corporation Memory array with current limiting device for preventing particle induced latch-up
JP4553185B2 (ja) * 2004-09-15 2010-09-29 ルネサスエレクトロニクス株式会社 半導体集積回路装置
TWI290717B (en) * 2004-11-08 2007-12-01 Zmos Technology Inc High speed and low power SRAM macro architecture and method
KR100616199B1 (ko) * 2004-12-06 2006-08-25 주식회사 하이닉스반도체 반도체 메모리 장치의 전압 발생 제어회로 및 방법
ITVA20050018A1 (it) * 2005-03-15 2006-09-16 St Microelectronics Srl Commutatore controllato
JP4912016B2 (ja) 2005-05-23 2012-04-04 ルネサスエレクトロニクス株式会社 半導体記憶装置
JP4917767B2 (ja) * 2005-07-01 2012-04-18 パナソニック株式会社 半導体記憶装置
US7355905B2 (en) 2005-07-01 2008-04-08 P.A. Semi, Inc. Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage
US7313033B2 (en) * 2005-09-28 2007-12-25 Infineon Technologies Ag Random access memory including first and second voltage sources
JP4929668B2 (ja) 2005-10-12 2012-05-09 富士通セミコンダクター株式会社 半導体メモリ
US8134644B2 (en) * 2005-10-15 2012-03-13 Cooper J Carl Audio synchronizer control and communications method and apparatus
US7554843B1 (en) * 2005-11-04 2009-06-30 Alta Analog, Inc. Serial bus incorporating high voltage programming signals
US20070103195A1 (en) * 2005-11-07 2007-05-10 Jeong Duk-Sohn High speed and low power SRAM macro architecture and method
US7411853B2 (en) * 2005-11-17 2008-08-12 Altera Corporation Volatile memory elements with elevated power supply levels for programmable logic device integrated circuits
JP4865360B2 (ja) * 2006-03-01 2012-02-01 パナソニック株式会社 半導体記憶装置
JP4936749B2 (ja) * 2006-03-13 2012-05-23 株式会社東芝 半導体記憶装置
US7292485B1 (en) * 2006-07-31 2007-11-06 Freescale Semiconductor, Inc. SRAM having variable power supply and method therefor
US7359272B2 (en) * 2006-08-18 2008-04-15 Taiwan Semiconductor Manufacturing Company, Ltd. Circuit and method for an SRAM with reduced power consumption
US7492627B2 (en) * 2006-11-17 2009-02-17 Freescale Semiconductor, Inc. Memory with increased write margin bitcells
JP5057430B2 (ja) * 2006-12-18 2012-10-24 ルネサスエレクトロニクス株式会社 半導体集積回路とその製造方法
DE102007002150A1 (de) * 2007-01-15 2008-07-31 Infineon Technologies Ag Konzept zur Reduktion von Leckströmen von integrierten Schaltungen mit wenigstens einem Transistor
US8705300B1 (en) 2007-02-27 2014-04-22 Altera Corporation Memory array circuitry with stability enhancement features
EP2020658B1 (en) * 2007-06-29 2014-06-18 Semiconductor Energy Laboratory Co., Ltd. Semiconductor memory device and semiconductor device
US7606061B2 (en) * 2007-08-07 2009-10-20 Taiwan Semiconductor Manufacturing Co., Ltd. SRAM device with a power saving module controlled by word line signals
JP4775352B2 (ja) * 2007-09-26 2011-09-21 ソニー株式会社 半導体記憶装置の製造方法
JP4420121B2 (ja) * 2008-03-12 2010-02-24 トヨタ自動車株式会社 コラム付けニーエアバッグ装置
JP2009231891A (ja) * 2008-03-19 2009-10-08 Nec Electronics Corp 半導体装置
CN102076282A (zh) * 2008-06-04 2011-05-25 耐利克斯股份有限公司 泊入装置和使用方法
TWI425509B (zh) * 2009-11-17 2014-02-01 Univ Hsiuping Sci & Tech 具放電路徑之雙埠靜態隨機存取記憶體
JP2011123970A (ja) 2009-12-14 2011-06-23 Renesas Electronics Corp 半導体記憶装置
EP2517355B1 (en) * 2009-12-25 2019-05-08 Semiconductor Energy Laboratory Co., Ltd. Memory device, semiconductor device, and electronic device
EP2539897B1 (en) 2010-02-23 2020-03-18 Rambus Inc. Methods and circuits for dynamically scaling dram power and performance
US8320203B2 (en) 2010-03-26 2012-11-27 Intel Corporation Method and system to lower the minimum operating voltage of register files
US8531873B2 (en) * 2011-05-08 2013-09-10 Ben-Gurion University Of The Negev Research And Development Authority Ultra low power SRAM cell circuit with a supply feedback loop for near and sub threshold operation
US20120281459A1 (en) * 2011-05-08 2012-11-08 Ben-Gurion University Of The Negev Research And Development Authority Ultra low power memory cell with a supply feedback loop configured for minimal leakage operation
CN103250239A (zh) * 2011-10-18 2013-08-14 新加坡优尼山帝斯电子私人有限公司 半导体器件
US8611169B2 (en) 2011-12-09 2013-12-17 International Business Machines Corporation Fine granularity power gating
US9093125B2 (en) 2012-01-23 2015-07-28 Qualcomm Incorporated Low voltage write speed bitcell
JP5932133B2 (ja) * 2012-03-30 2016-06-08 インテル コーポレイション 書込マージンを改善されたメモリセル
US9001549B2 (en) * 2012-05-11 2015-04-07 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US9153304B2 (en) * 2012-06-28 2015-10-06 Jaydeep P. Kulkarni Apparatus for reducing write minimum supply voltage for memory
US9111638B2 (en) * 2012-07-13 2015-08-18 Freescale Semiconductor, Inc. SRAM bit cell with reduced bit line pre-charge voltage
US8817528B2 (en) * 2012-08-17 2014-08-26 Globalfoundries Inc. Device comprising a plurality of static random access memory cells and method of operation thereof
US9183906B2 (en) 2012-10-02 2015-11-10 International Business Machines Corporation Fine granularity power gating
US20140119146A1 (en) * 2012-10-30 2014-05-01 Apple Inc. Clock Gated Storage Array
US8942052B2 (en) 2012-11-21 2015-01-27 International Business Machines Corporation Complementary metal-oxide-semiconductor (CMOS) min/max voltage circuit for switching between multiple voltages
KR102112367B1 (ko) * 2013-02-12 2020-05-18 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
US20160172036A1 (en) * 2013-08-16 2016-06-16 Charles Augustine Memory cell with retention using resistive memory
JP2014139860A (ja) * 2014-03-28 2014-07-31 Renesas Electronics Corp 半導体集積回路装置
JP2016092536A (ja) * 2014-10-31 2016-05-23 ルネサスエレクトロニクス株式会社 半導体装置
JP6436821B2 (ja) * 2015-03-19 2018-12-12 エイブリック株式会社 電流検出回路
US9786357B2 (en) * 2016-02-17 2017-10-10 Apple Inc. Bit-cell voltage distribution system
US9922701B2 (en) 2016-08-08 2018-03-20 Taiwan Semiconductor Manufacturing Company Limited Pre-charging bit lines through charge-sharing
KR102714216B1 (ko) * 2016-12-06 2024-10-10 삼성전자주식회사 균일한 쓰기 특성을 갖는 에스램 장치
JP6535120B2 (ja) * 2018-03-29 2019-06-26 ルネサスエレクトロニクス株式会社 半導体装置
EP3888086A4 (en) 2018-11-30 2022-09-07 Rambus Inc. MULTIPLE VOLTAGE RANGE DRAM DEVICE
JP2020149746A (ja) * 2019-03-14 2020-09-17 キオクシア株式会社 半導体記憶装置
KR102814915B1 (ko) * 2022-10-25 2025-05-30 삼성전자주식회사 메모리 컨트롤러의 동-작 방법 및 메모리 장치

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5564686A (en) 1978-11-08 1980-05-15 Nec Corp Memory unit
JPS57130463A (en) * 1981-02-06 1982-08-12 Toshiba Corp Semiconductor memory
JPS57130286A (en) * 1981-02-06 1982-08-12 Fujitsu Ltd Static semiconductor memory
JPS58211391A (ja) 1982-05-31 1983-12-08 Toshiba Corp 半導体記憶装置
JPS5968891A (ja) * 1982-10-12 1984-04-18 Toshiba Corp 半導体メモリ
JPS6038796A (ja) * 1983-08-12 1985-02-28 Hitachi Ltd 半導体集積回路装置
JPS62174968A (ja) * 1986-01-29 1987-07-31 Hitachi Ltd 半導体装置
JPS63108589A (ja) * 1986-10-24 1988-05-13 Mitsubishi Electric Corp 半導体記憶装置
JPH01166399A (ja) * 1987-12-23 1989-06-30 Toshiba Corp スタティック型ランダムアクセスメモリ
US5046052A (en) * 1988-06-01 1991-09-03 Sony Corporation Internal low voltage transformation circuit of static random access memory
JPH0766945B2 (ja) * 1988-09-06 1995-07-19 株式会社東芝 スタティック型メモリ
US4872141A (en) * 1988-09-12 1989-10-03 General Electric Company Radiation hard memory cell having monocrystalline and non-monocrystalline inverters
JPH02108297A (ja) * 1988-10-18 1990-04-20 Nippon Telegr & Teleph Corp <Ntt> メモリセル回路
JPH0383289A (ja) 1989-08-25 1991-04-09 Nec Corp Ｍｏｓ型半導体記憶装置
JPH07109864B2 (ja) * 1989-09-13 1995-11-22 シャープ株式会社 スタティックｒａｍ
US5159215A (en) * 1990-02-26 1992-10-27 Nec Corporation Decoder circuit
DE69117722T2 (de) 1990-08-06 1996-09-19 Fujitsu Ltd Übertragungsvorrichtung mit wiederholter schaltfunktion
US5226014A (en) * 1990-12-24 1993-07-06 Ncr Corporation Low power pseudo-static ROM
JPH04276386A (ja) * 1991-03-01 1992-10-01 Nippon Telegr & Teleph Corp <Ntt> メモリ回路
JP3110113B2 (ja) * 1991-11-21 2000-11-20 株式会社東芝 スタティック型メモリ
US5301147A (en) * 1993-01-08 1994-04-05 Aptix Corporation Static random access memory cell with single logic-high voltage level bit-line and address-line drivers
JP3042203B2 (ja) 1992-09-16 2000-05-15 日本電気株式会社 スタティック型記憶回路
US5303190A (en) * 1992-10-27 1994-04-12 Motorola, Inc. Static random access memory resistant to soft error
KR0141933B1 (ko) * 1994-10-20 1998-07-15 문정환 저전력의 스테이틱 랜덤 억세스 메모리장치
JP4198201B2 (ja) * 1995-06-02 2008-12-17 株式会社ルネサステクノロジ 半導体装置
TW373175B (en) * 1995-10-31 1999-11-01 Matsushita Electric Mfg Corp Data maintaining circuit
US5841707A (en) * 1995-11-29 1998-11-24 Texas Instruments Incorporated Apparatus and method for a programmable interval timing generator in a semiconductor memory
US5805496A (en) * 1996-12-27 1998-09-08 International Business Machines Corporation Four device SRAM cell with single bitline
JP3478953B2 (ja) * 1997-09-03 2003-12-15 Ｎｅｃエレクトロニクス株式会社 半導体記憶装置
JPH11260054A (ja) * 1998-01-08 1999-09-24 Mitsubishi Electric Corp ダイナミック型半導体記憶装置
DE19810918C2 (de) 1998-03-13 2002-11-14 Sachs Race Eng Gmbh Reibungskupplung
US6141240A (en) * 1998-09-17 2000-10-31 Texas Instruments Incorporated Apparatus and method for static random access memory array
US6058060A (en) * 1998-12-31 2000-05-02 Invox Technology Multi-bit-per-cell and analog/multi-level non-volatile memories with improved resolution and signal-to noise ratio
CA2626694C (en) 1999-03-09 2011-08-02 Synthes (U.S.A.) Bone plate with conical screw threads
JP2002368135A (ja) * 2001-06-12 2002-12-20 Hitachi Ltd 半導体記憶装置

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TW302535B (enExample) 1997-04-11
US20100165706A1 (en) 2010-07-01
US6639828B2 (en) 2003-10-28
US6469950B2 (en) 2002-10-22
KR970004020A (ko) 1997-01-29
US6215716B1 (en) 2001-04-10
US7978560B2 (en) 2011-07-12
US20040046188A1 (en) 2004-03-11
US8325553B2 (en) 2012-12-04
KR100395260B1 (ko) 2003-08-21
US7706205B2 (en) 2010-04-27
US6917556B2 (en) 2005-07-12
US20010006476A1 (en) 2001-07-05
KR100373223B1 (ko) 2003-07-22
US20110235439A1 (en) 2011-09-29
US20030012049A1 (en) 2003-01-16
KR100395261B1 (ko) 2003-08-21
US6108262A (en) 2000-08-22
US20070165448A1 (en) 2007-07-19
US6388936B2 (en) 2002-05-14
US5668770A (en) 1997-09-16
US7251183B2 (en) 2007-07-31
US5894433A (en) 1999-04-13
JPH0951042A (ja) 1997-02-18
US20050226077A1 (en) 2005-10-13

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