JP5932133B2 - 書込マージンを改善されたメモリセル - Google Patents
書込マージンを改善されたメモリセル Download PDFInfo
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- JP5932133B2 JP5932133B2 JP2015503172A JP2015503172A JP5932133B2 JP 5932133 B2 JP5932133 B2 JP 5932133B2 JP 2015503172 A JP2015503172 A JP 2015503172A JP 2015503172 A JP2015503172 A JP 2015503172A JP 5932133 B2 JP5932133 B2 JP 5932133B2
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/148—Details of power up or power down circuits, standby circuits or recovery circuits
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Static Random-Access Memory (AREA)
Description
Claims (11)
- SRAMセルであるメモリセルの書込マージンを改善する装置であって、
パルス信号に幅を持たせる第1の回路と、
前記パルス信号を受信し、前記メモリセルのための電源を生成し、該電源を前記メモリセルの供給ノードに供給する第2の回路と
を有し、
前記第2の回路は、前記メモリセルの書込動作の間に、前記電源のレベルを、前記パルス信号の前記幅に対応する時間期間中は、前記メモリセルのデータ保持電圧レベルよりも下回らせ、前記時間期間以外の期間中は、前記データ保持電圧レベルに設定し、
前記時間期間は、未選択メモリセルで保持されているデータが失われ得る閾時間よりも短い、
装置。 - 前記第2の回路は、入力として前記パルス信号を受信するよう動作するインバータを有し、該インバータは、前記メモリセルに前記電源を供給する出力を備える、
請求項1に記載の装置。 - 前記第2の回路は、前記メモリセルの読出動作又はアイドル状態の間、前記電源を、前記データ保持電圧レベルよりも高い電圧レベルに設定するよう動作する、
請求項1に記載の装置。 - 前記第1の回路は、前記パルス信号の前記幅を調整するよう動作する、
請求項1に記載の装置。 - 前記第1の回路は、ヒューズ又はソフトウェア命令のうちの少なくとも1つによって、前記パルス信号の前記幅を調整するよう動作する、
請求項4に記載の装置。 - 前記第1の回路は、調整可能なパルス幅を提供するよう可変遅延を伴うパルス発生器を有する、
請求項1に記載の装置。 - 前記メモリセルは、6T SRAMセルである、
請求項1に記載の装置。 - 前記第2の回路は、前記メモリセルの書込動作の間の前記時間期間中に、接地と前記データ保持電圧レベルとの間にあるように前記電源のレベルを下げるよう動作する、
請求項1に記載の装置。 - 前記第2の回路は、前記メモリセルの書込動作の間の前記時間期間中に、前記電源のレベルを接地に下げるよう動作する、
請求項1に記載の装置。 - 無線アンテナと、
前記無線アンテナを介して他の装置と通信可能なプロセッサと
を有し、
前記プロセッサは、メモリセルのアレイを含み、
パルス信号に幅を持たせる第1の回路と、
前記パルス信号を受信し、前記メモリセルのアレイに含まれるSRAMセルのための電源を生成し、該電源を前記SRAMセルの供給ノードに供給する第2の回路と
を有し、
前記第2の回路は、前記SRAMセルへの書込動作の間に、前記電源のレベルを、前記パルス信号の前記幅に対応する時間期間中は、当該SRAMセルのデータ保持電圧レベルよりも下回らせ、前記時間期間以外の期間中は、前記データ保持電圧レベルに設定し、
前記時間期間は、未選択メモリセルで保持されているデータが失われ得る閾時間よりも短い、
システム。 - 前記プロセッサは、請求項2乃至9のうちいずれか一項に記載の装置を更に有する、
請求項10に記載のシステム。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/US2012/031455 WO2013147848A1 (en) | 2012-03-30 | 2012-03-30 | Memory cell with improved write margin |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2015233754A Division JP6144324B2 (ja) | 2015-11-30 | 2015-11-30 | 書込マージンを改善されたメモリセル |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2015511753A JP2015511753A (ja) | 2015-04-20 |
JP5932133B2 true JP5932133B2 (ja) | 2016-06-08 |
Family
ID=49260903
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2015503172A Active JP5932133B2 (ja) | 2012-03-30 | 2012-03-30 | 書込マージンを改善されたメモリセル |
Country Status (4)
Country | Link |
---|---|
US (3) | US9111600B2 (ja) |
JP (1) | JP5932133B2 (ja) |
CN (1) | CN104321817A (ja) |
WO (1) | WO2013147848A1 (ja) |
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US9311967B2 (en) | 2014-05-30 | 2016-04-12 | Apple Inc. | Configurable voltage reduction for register file |
US9251875B1 (en) * | 2014-09-26 | 2016-02-02 | Qualcomm Incorporated | Register file circuit and method for improving the minimum operating supply voltage |
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US9865355B2 (en) | 2015-02-02 | 2018-01-09 | Micron Technology, Inc. | Apparatuses and methods for transistor protection by charge sharing |
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CN105976859B (zh) * | 2016-05-20 | 2019-05-17 | 西安紫光国芯半导体有限公司 | 一种超低写功耗的静态随机存储器写操作的控制方法 |
US10049724B2 (en) * | 2016-06-07 | 2018-08-14 | Intel Corporation | Aging tolerant register file |
US9934846B1 (en) | 2017-03-01 | 2018-04-03 | Nxp Usa, Inc. | Memory circuit and method for increased write margin |
US9940996B1 (en) * | 2017-03-01 | 2018-04-10 | Nxp Usa, Inc. | Memory circuit having increased write margin and method therefor |
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US10163494B1 (en) * | 2017-05-31 | 2018-12-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Memory device and fabrication method thereof |
US11100962B2 (en) * | 2017-12-26 | 2021-08-24 | SK Hynix Inc. | Semiconductor device with a power-down mode and a power gating circuit and semiconductor system including the same |
US11838020B1 (en) | 2017-12-26 | 2023-12-05 | SK Hynix Inc. | Semiconductor memory device including write driver with power gating structures and operating method thereof |
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US10446223B1 (en) * | 2018-08-29 | 2019-10-15 | Bitfury Group Limited | Data storage apparatus, and related systems and methods |
TWI674754B (zh) * | 2018-12-28 | 2019-10-11 | 新唐科技股份有限公司 | 資料保持電路 |
US10614877B1 (en) | 2019-01-10 | 2020-04-07 | International Business Machines Corporation | 4T static random access memory bitcell retention |
JP6901515B2 (ja) | 2019-04-04 | 2021-07-14 | ウィンボンド エレクトロニクス コーポレーション | 半導体装置 |
US11170844B1 (en) | 2020-07-07 | 2021-11-09 | Aril Computer Corporation | Ultra-low supply-voltage static random-access memory (SRAM) with 8-transistor cell with P and N pass gates to same bit lines |
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US8045402B2 (en) | 2009-06-29 | 2011-10-25 | Arm Limited | Assisting write operations to data storage cells |
US8456939B2 (en) * | 2009-12-11 | 2013-06-04 | Arm Limited | Voltage regulation circuitry |
US8130579B2 (en) | 2009-12-21 | 2012-03-06 | Stmicroelectronics Pvt. Ltd. | Memory device and method of operation thereof |
WO2013147848A1 (en) | 2012-03-30 | 2013-10-03 | Intel Corporation | Memory cell with improved write margin |
-
2012
- 2012-03-30 WO PCT/US2012/031455 patent/WO2013147848A1/en active Application Filing
- 2012-03-30 US US13/997,633 patent/US9111600B2/en active Active
- 2012-03-30 JP JP2015503172A patent/JP5932133B2/ja active Active
- 2012-03-30 CN CN201280071893.8A patent/CN104321817A/zh active Pending
-
2015
- 2015-05-04 US US14/703,723 patent/US9666268B2/en active Active
-
2017
- 2017-04-25 US US15/496,655 patent/US9978447B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
CN104321817A (zh) | 2015-01-28 |
US9978447B2 (en) | 2018-05-22 |
US20140003181A1 (en) | 2014-01-02 |
WO2013147848A1 (en) | 2013-10-03 |
US20170229166A1 (en) | 2017-08-10 |
US20150235696A1 (en) | 2015-08-20 |
US9666268B2 (en) | 2017-05-30 |
JP2015511753A (ja) | 2015-04-20 |
US9111600B2 (en) | 2015-08-18 |
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