JP4014912B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

Info

Publication number
JP4014912B2
JP4014912B2 JP2002103684A JP2002103684A JP4014912B2 JP 4014912 B2 JP4014912 B2 JP 4014912B2 JP 2002103684 A JP2002103684 A JP 2002103684A JP 2002103684 A JP2002103684 A JP 2002103684A JP 4014912 B2 JP4014912 B2 JP 4014912B2
Authority
JP
Japan
Prior art keywords
semiconductor device
semiconductor
support plate
connection terminal
metal wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2002103684A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003174120A (ja
JP2003174120A5 (enExample
Inventor
義彦 根本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP2002103684A priority Critical patent/JP4014912B2/ja
Priority to US10/252,504 priority patent/US20030062631A1/en
Priority to TW91137702A priority patent/TW571416B/zh
Priority to DE10300951A priority patent/DE10300951A1/de
Priority to KR10-2003-0004529A priority patent/KR20030080187A/ko
Publication of JP2003174120A publication Critical patent/JP2003174120A/ja
Priority to US11/150,296 priority patent/US7148576B2/en
Publication of JP2003174120A5 publication Critical patent/JP2003174120A5/ja
Application granted granted Critical
Publication of JP4014912B2 publication Critical patent/JP4014912B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H10W74/019—
    • H10W72/20—
    • H10W74/111—
    • H10W90/00—
    • H10W99/00—
    • H10W70/05—
    • H10W70/60—
    • H10W70/65—
    • H10W72/01225—
    • H10W72/01551—
    • H10W72/07141—
    • H10W72/075—
    • H10W72/07504—
    • H10W72/07507—
    • H10W72/07521—
    • H10W72/07533—
    • H10W72/07553—
    • H10W72/241—
    • H10W72/242—
    • H10W72/251—
    • H10W72/536—
    • H10W72/5363—
    • H10W72/5445—
    • H10W72/552—
    • H10W72/5524—
    • H10W72/583—
    • H10W72/59—
    • H10W72/801—
    • H10W72/932—
    • H10W72/9413—
    • H10W72/944—
    • H10W74/00—
    • H10W74/10—
    • H10W74/142—
    • H10W90/288—
    • H10W90/722—
    • H10W90/756—

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
JP2002103684A 2001-09-28 2002-04-05 半導体装置 Expired - Fee Related JP4014912B2 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2002103684A JP4014912B2 (ja) 2001-09-28 2002-04-05 半導体装置
US10/252,504 US20030062631A1 (en) 2001-09-28 2002-09-24 Semiconductor device and method of fabricating the same
TW91137702A TW571416B (en) 2001-09-28 2002-12-27 Semiconductor device and method of fabricating the same
DE10300951A DE10300951A1 (de) 2002-04-05 2003-01-13 Halbleitervorrichtung und Verfahren zur Herstellung derselben
KR10-2003-0004529A KR20030080187A (ko) 2002-04-05 2003-01-23 반도체장치
US11/150,296 US7148576B2 (en) 2001-09-28 2005-06-13 Semiconductor device and method of fabricating the same

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2001299756 2001-09-28
JP2001-299756 2001-09-28
JP2002103684A JP4014912B2 (ja) 2001-09-28 2002-04-05 半導体装置

Publications (3)

Publication Number Publication Date
JP2003174120A JP2003174120A (ja) 2003-06-20
JP2003174120A5 JP2003174120A5 (enExample) 2005-09-15
JP4014912B2 true JP4014912B2 (ja) 2007-11-28

Family

ID=26623238

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002103684A Expired - Fee Related JP4014912B2 (ja) 2001-09-28 2002-04-05 半導体装置

Country Status (3)

Country Link
US (2) US20030062631A1 (enExample)
JP (1) JP4014912B2 (enExample)
TW (1) TW571416B (enExample)

Families Citing this family (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100536898B1 (ko) * 2003-09-04 2005-12-16 삼성전자주식회사 반도체 소자의 와이어 본딩 방법
US7425759B1 (en) * 2003-11-20 2008-09-16 Bridge Semiconductor Corporation Semiconductor chip assembly with bumped terminal and filler
JP3864952B2 (ja) * 2003-12-01 2007-01-10 セイコーエプソン株式会社 振動子デバイス及びそれを備えた電子機器並びに振動子デバイスの製造方法
US7205178B2 (en) * 2004-03-24 2007-04-17 Freescale Semiconductor, Inc. Land grid array packaged device and method of forming same
WO2006072093A2 (en) * 2004-12-30 2006-07-06 Dor Biopharma, Inc. Treatment of graft-versus-host disease and leukemia with beclomethasone dipropionate and prednisone
US7371676B2 (en) 2005-04-08 2008-05-13 Micron Technology, Inc. Method for fabricating semiconductor components with through wire interconnects
US7393770B2 (en) * 2005-05-19 2008-07-01 Micron Technology, Inc. Backside method for fabricating semiconductor components with conductive interconnects
US7768113B2 (en) * 2005-05-26 2010-08-03 Volkan Ozguz Stackable tier structure comprising prefabricated high density feedthrough
US7919844B2 (en) * 2005-05-26 2011-04-05 Aprolase Development Co., Llc Tier structure with tier frame having a feedthrough structure
WO2007004986A1 (en) * 2005-07-06 2007-01-11 Infineon Technologies Ag An integrated circuit package and a method for manufacturing an integrated circuit package
SG130061A1 (en) 2005-08-24 2007-03-20 Micron Technology Inc Microelectronic devices and microelectronic support devices, and associated assemblies and methods
US7307348B2 (en) 2005-12-07 2007-12-11 Micron Technology, Inc. Semiconductor components having through wire interconnects (TWI)
US20070216033A1 (en) * 2006-03-20 2007-09-20 Corisis David J Carrierless chip package for integrated circuit devices, and methods of making same
US7659612B2 (en) 2006-04-24 2010-02-09 Micron Technology, Inc. Semiconductor components having encapsulated through wire interconnects (TWI)
TWI314774B (en) * 2006-07-11 2009-09-11 Siliconware Precision Industries Co Ltd Semiconductor package and fabrication method thereof
KR100761468B1 (ko) 2006-07-13 2007-09-27 삼성전자주식회사 반도체 장치 및 그 형성 방법
US7969022B1 (en) * 2007-03-21 2011-06-28 Marvell International Ltd. Die-to-die wire-bonding
JP2008306128A (ja) * 2007-06-11 2008-12-18 Shinko Electric Ind Co Ltd 半導体装置およびその製造方法
JP5273956B2 (ja) * 2007-07-02 2013-08-28 スパンション エルエルシー 半導体装置の製造方法
US20090154111A1 (en) * 2007-12-17 2009-06-18 Lynch Thomas W Reticulated heat dissipation
US20090165996A1 (en) * 2007-12-26 2009-07-02 Lynch Thomas W Reticulated heat dissipation with coolant
JP5343359B2 (ja) * 2008-01-09 2013-11-13 富士通セミコンダクター株式会社 半導体装置の製造方法
US8138024B2 (en) * 2008-02-26 2012-03-20 Stats Chippac Ltd. Package system for shielding semiconductor dies from electromagnetic interference
US8189344B2 (en) 2008-06-09 2012-05-29 Stats Chippac Ltd. Integrated circuit package system for stackable devices
US7851893B2 (en) * 2008-06-10 2010-12-14 Stats Chippac, Ltd. Semiconductor device and method of connecting a shielding layer to ground through conductive vias
US8183677B2 (en) * 2008-11-26 2012-05-22 Infineon Technologies Ag Device including a semiconductor chip
US8168458B2 (en) * 2008-12-08 2012-05-01 Stats Chippac, Ltd. Semiconductor device and method of forming bond wires and stud bumps in recessed region of peripheral area around the device for electrical interconnection to other devices
JP2010141066A (ja) * 2008-12-11 2010-06-24 Rohm Co Ltd 半導体装置
JP5112275B2 (ja) * 2008-12-16 2013-01-09 新光電気工業株式会社 半導体装置及び半導体装置の製造方法
JP5588150B2 (ja) * 2009-02-06 2014-09-10 セイコーインスツル株式会社 樹脂封止型半導体装置
US8357563B2 (en) * 2010-08-10 2013-01-22 Spansion Llc Stitch bump stacking design for overall package size reduction for multiple stack
US8304900B2 (en) 2010-08-11 2012-11-06 Stats Chippac Ltd. Integrated circuit packaging system with stacked lead and method of manufacture thereof
JP6246507B2 (ja) * 2012-11-05 2017-12-13 新光電気工業株式会社 プローブカード及びその製造方法
JP5763696B2 (ja) * 2013-03-04 2015-08-12 スパンション エルエルシー 半導体装置およびその製造方法
JP6208486B2 (ja) 2013-07-19 2017-10-04 新光電気工業株式会社 プローブカード及びその製造方法
JP6092729B2 (ja) 2013-07-19 2017-03-08 新光電気工業株式会社 プローブカード及びその製造方法
JP6219227B2 (ja) * 2014-05-12 2017-10-25 東京エレクトロン株式会社 ヒータ給電機構及びステージの温度制御方法
JP6219229B2 (ja) * 2014-05-19 2017-10-25 東京エレクトロン株式会社 ヒータ給電機構
CN106486443A (zh) * 2015-08-27 2017-03-08 冠研（上海）专利技术有限公司 简易半导体芯片封装结构及其封装方法
CN106486429A (zh) * 2015-08-27 2017-03-08 冠研（上海）专利技术有限公司 半导体芯片封装结构及其封装方法
CN105514074B (zh) * 2015-12-01 2018-07-03 上海伊诺尔信息技术有限公司 智能卡芯片封装结构及其制造方法
IT201700073501A1 (it) * 2017-06-30 2018-12-30 St Microelectronics Srl Prodotto a semiconduttore e corrispondente procedimento
US10453820B2 (en) 2018-02-07 2019-10-22 Micron Technology, Inc. Semiconductor assemblies using edge stacking and methods of manufacturing the same
FR3104317A1 (fr) * 2019-12-04 2021-06-11 Stmicroelectronics (Tours) Sas Procédé de fabrication de puces électroniques
US12046525B2 (en) 2020-11-27 2024-07-23 Yibu Semiconductor Co., Ltd. Semiconductor packaging method, semiconductor assembly and electronic device comprising semiconductor assembly
US12159850B2 (en) 2020-12-25 2024-12-03 Yibu Semiconductor Co., Ltd. Semiconductor packaging method, semiconductor assembly and electronic device comprising semiconductor assembly
US12154884B2 (en) 2021-02-01 2024-11-26 Yibu Semiconductor Co., Ltd. Semiconductor packaging method, semiconductor assembly and electronic device comprising semiconductor assembly
US12500203B2 (en) 2021-02-22 2025-12-16 Yibu Semiconductor Co., Ltd. Semiconductor packaging method, semiconductor assembly and electronic device comprising semiconductor assembly

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60117696A (ja) * 1983-11-30 1985-06-25 沖電気工業株式会社 Ｅｐｒｏｍの実装構造
AU2309388A (en) * 1987-08-26 1989-03-31 Matsushita Electric Industrial Co., Ltd. Integrated circuit device and method of producing the same
US6072239A (en) * 1995-11-08 2000-06-06 Fujitsu Limited Device having resin package with projections
JP3007833B2 (ja) 1995-12-12 2000-02-07 富士通株式会社 半導体装置及びその製造方法及びリードフレーム及びその製造方法
JP3207738B2 (ja) * 1996-01-15 2001-09-10 株式会社東芝 樹脂封止型半導体装置及びその製造方法
JP3500015B2 (ja) 1996-09-25 2004-02-23 三洋電機株式会社 半導体装置及びその製造方法
JPH11312749A (ja) * 1998-02-25 1999-11-09 Fujitsu Ltd 半導体装置及びその製造方法及びリードフレームの製造方法
US6451624B1 (en) * 1998-06-05 2002-09-17 Micron Technology, Inc. Stackable semiconductor package having conductive layer and insulating layers and method of fabrication
JP3397725B2 (ja) * 1999-07-07 2003-04-21 沖電気工業株式会社 半導体装置、その製造方法及び半導体素子実装用テープの製造方法
US6247229B1 (en) * 1999-08-25 2001-06-19 Ankor Technology, Inc. Method of forming an integrated circuit device package using a plastic tape as a base
JP2002158312A (ja) * 2000-11-17 2002-05-31 Oki Electric Ind Co Ltd ３次元実装用半導体パッケージ、その製造方法、および半導体装置
JP3798620B2 (ja) * 2000-12-04 2006-07-19 富士通株式会社 半導体装置の製造方法
US6696320B2 (en) * 2001-09-30 2004-02-24 Intel Corporation Low profile stacked multi-chip package and method of forming same

Also Published As

Publication number Publication date
US20030062631A1 (en) 2003-04-03
TW200305264A (en) 2003-10-16
US7148576B2 (en) 2006-12-12
TW571416B (en) 2004-01-11
JP2003174120A (ja) 2003-06-20
US20050224949A1 (en) 2005-10-13

Similar Documents

Publication Publication Date Title
JP4014912B2 (ja) 半導体装置
US7692282B2 (en) Semiconductor device including semiconductor element surrounded by an insulating member wiring structures on upper and lower surfaces of the semiconductor element and insulating member, and manufacturing method thereof
US5874784A (en) Semiconductor device having external connection terminals provided on an interconnection plate and fabrication process therefor
JP2819284B2 (ja) 半導体パッケージ用基板およびその製造方法と その基板を利用した積層型半導体パッケージ
JP5529371B2 (ja) 半導体装置及びその製造方法
US7550833B2 (en) Semiconductor device having a second semiconductor construction mounted on a first semiconductor construction and a manufacturing method thereof
TWI408795B (zh) Semiconductor device and manufacturing method thereof
US6310395B1 (en) Electronic component with anodically bonded contact
CN101388387B (zh) 电子装置和制造电子装置的方法
JP6125332B2 (ja) 半導体装置
JP2004343030A (ja) 配線回路基板とその製造方法とその配線回路基板を備えた回路モジュール
KR20010098592A (ko) 반도체패키지 및 그 제조방법
JP2005167244A (ja) 集積回路積層に用いられる薄いパッケージ
TW201115661A (en) Semiconductor device and method of manufacturing the same
US12283563B2 (en) Semiconductor module with bond wire loop exposed from a molded body and method for fabricating the same
US8217517B2 (en) Semiconductor device provided with wire that electrically connects printed wiring board and semiconductor chip each other
KR20030080187A (ko) 반도체장치
JP2004363319A (ja) 実装基板及び半導体装置
JP4596053B2 (ja) 半導体装置の製造方法および半導体構成体組立体
JP4435074B2 (ja) 半導体装置およびその製造方法
JP4140012B2 (ja) チップ状電子部品、その製造方法及び実装構造
KR100682650B1 (ko) 반도체 장치 및 그 제조방법
JP4619104B2 (ja) 半導体装置
TWI401787B (zh) 封裝基板之製法
US20070290365A1 (en) Electronic Device Including a Component Stack and Connecting Elements, and Connecting Elements, and Method for Producing the Electronic Device

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20050328

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050328

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20051028

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060829

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20061010

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20070904

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20070912

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100921

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110921

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110921

Year of fee payment: 4

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110921

Year of fee payment: 4

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

LAPS Cancellation because of no payment of annual fees