JP5273956B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5273956B2 JP5273956B2 JP2007174660A JP2007174660A JP5273956B2 JP 5273956 B2 JP5273956 B2 JP 5273956B2 JP 2007174660 A JP2007174660 A JP 2007174660A JP 2007174660 A JP2007174660 A JP 2007174660A JP 5273956 B2 JP5273956 B2 JP 5273956B2
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- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
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- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
12 樹脂部
14 第1金属部
16 第2金属部
18 第1ワイヤ
20 第1導電部
22 凹部
24 第1支持体
25 第1フィルム膜
26 第1貫通孔
27 第2フィルム膜
29 第2貫通孔
30 第2支持体
31 上部半導体装置
32 第2導電部
33 下部半導体装置
34 第2半導体チップ
35 半田
36 第2ワイヤ
Claims (12)
- 第1支持体上に複数の第1金属部を形成する工程と、
前記複数の第1金属部のうち一部の第1金属部に隣接するよう、前記第1支持体上に複数の第1半導体チップを搭載する工程と、
前記複数の第1半導体チップのうち隣接する第1半導体チップ同士を前記第1金属部越しに第1ワイヤにより接続する工程と、
第2支持体上に複数の第2金属部を形成する工程と、
前記第1ワイヤを挟むように前記複数の第1金属部と前記複数の第2金属部とをそれぞれ接続させ、前記第1支持体と前記第2支持体とを接合させる工程と、
前記第1支持体と前記第2支持体との間に樹脂を充填させて、前記複数の第1半導体チップを封止する樹脂部を形成する工程と、
前記第1支持体および前記第2支持体を前記樹脂部から引き剥がす工程と、
前記第1半導体チップが含まれるように、前記樹脂部を切断する工程と、を有することを特徴とする半導体装置の製造方法。 - 前記複数の第1金属部を形成する工程は、前記第1支持体に設けられた複数の凹部に前記第1金属部を圧入することにより、前記複数の第1金属部を形成する工程であり、
前記複数の第2金属部を形成する工程は、前記第2支持体に設けられた複数の凹部に前記第2金属部を圧入することにより、前記複数の第2金属部を形成する工程であることを特徴とする請求項1記載の半導体装置の製造方法。 - 前記隣接する第1半導体チップ同士を第1金属部越しに第1ワイヤにより接続する工程の前に、前記複数の第1金属部の上部を平坦化させる工程を有し、
前記第1支持体と第2支持体とを接合させる工程の前に、前記複数の第2金属部の上部を平坦化させる工程を有することを特徴とする請求項1または2記載の半導体装置の製造方法。 - 前記複数の第1金属部を形成する工程は、第1フィルム膜を挟んで前記第1支持体上に前記複数の第1金属部を形成する工程であり、
前記複数の第2金属部を形成する工程は、第2フィルム膜を挟んで前記第2支持体上に前記複数の第2金属部を形成する工程であることを特徴とする請求項1から3のいずれか一項記載の半導体装置の製造方法。 - 前記第1支持体は、前記第1支持体を貫通する第1貫通孔を有し、
前記第2支持体は、前記第2支持体を貫通する第2貫通孔を有し、
前記第1支持体および第2支持体を前記樹脂部から引き剥がす工程は、前記第1貫通孔および前記第2貫通孔から気体を送り込みながら、前記第1支持体および第2支持体を前記樹脂部から引き剥がす工程であることを特徴とする請求項1から4のいずれか一項記載の半導体装置の製造方法。 - 前記複数の第1金属部を形成する工程は、第1フィルム膜を挟んで前記第1支持体上に前記複数の第1金属部を形成する工程であり
前記複数の第2金属部を形成する工程は、第2フィルム膜を挟んで前記第2支持体上に前記複数の第2金属部を形成する工程であり、
前記第1支持体は、前記第1フィルム膜の厚さより小さい直径で、前記第1支持体を貫通する第1貫通孔を有し、
前記第2支持体は、前記第2フィルム膜の厚さより小さい直径で、前記第2支持体を貫通する第2貫通孔を有し、
前記第1支持体および第2支持体を前記樹脂部から引き剥がす工程は、前記第1貫通孔および前記第2貫通孔から気体を送り込みながら、前記第1支持体および前記第2支持体を前記樹脂部から引き剥がす工程であることを特徴とする請求項1から3のいずれか一項記載の半導体装置の製造方法。 - 前記第1支持体の周辺部に第1導電部を形成する工程と、
前記第1導電部と前記第1導電部に隣接する前記第1半導体チップとを前記第1金属部越しに前記第1ワイヤにより接続させる工程と、を有することを特徴とする請求項1から6のいずれか一項記載の半導体装置の製造方法。 - 前記隣接する第1半導体チップの間に第2導電部を形成する工程を有し、
前記隣接する第1半導体チップ同士を第1金属部越しに第1ワイヤにより接続させる工程は、前記第2導電部を介して、前記隣接する第1半導体チップ同士を第1金属部越しに第1ワイヤにより接続させる工程を含むことを特徴とする請求項1から7のいずれか一項記載の半導体装置の製造方法。 - 前記第1金属部および前記第2金属部は球状であることを特徴とする請求項1から8のいずれか一項記載の半導体装置の製造方法。
- 前記複数の第1半導体チップそれぞれの上に第2半導体チップを搭載する工程と、
隣接する前記第2半導体チップ同士を前記第1金属部越しに第2ワイヤにより接続させる工程と、を有し、
前記第1支持体と第2支持体とを接合させる工程は、前記第1ワイヤおよび前記第2ワイヤを挟むように前記複数の第1金属部と前記複数の第2金属部とをそれぞれ接続させ、前記第1支持体と第2支持体とを接合させる工程であることを特徴とする請求項1から9のいずれか一項記載の半導体装置の製造方法。 - 前記第1支持体の周辺部に第1導電部を形成する工程と、
前記第1導電部と前記第1導電部に隣接する前記第2半導体チップとを前記第1金属部越しに前記第2ワイヤにより接続させる工程と、を有することを特徴とする請求項10記載の半導体装置の製造方法。 - 前記隣接する第1半導体チップの間に第2導電部を形成する工程を有し、
前記隣接する第2半導体チップ同士を第1金属部越しに第2ワイヤにより接続させる工程は、前記第2導電部を介して、前記隣接する第2半導体チップ同士を第1金属部越しに第2ワイヤにより接続させる工程を含むことを特徴とする請求項10または11記載の半導体装置の製造方法。
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JP2007174660A JP5273956B2 (ja) | 2007-07-02 | 2007-07-02 | 半導体装置の製造方法 |
US12/165,331 US7892892B2 (en) | 2007-07-02 | 2008-06-30 | Semiconductor device and method for manufacturing thereof |
US13/015,072 US8446015B2 (en) | 2007-07-02 | 2011-01-27 | Semiconductor device and method for manufacturing thereof |
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US8168458B2 (en) * | 2008-12-08 | 2012-05-01 | Stats Chippac, Ltd. | Semiconductor device and method of forming bond wires and stud bumps in recessed region of peripheral area around the device for electrical interconnection to other devices |
JP5548159B2 (ja) * | 2010-11-05 | 2014-07-16 | 株式会社アドバンテスト | 欠陥レビュー装置及び欠陥レビュー方法 |
US11388811B1 (en) | 2021-05-21 | 2022-07-12 | Amulaire Thermal Technology, Inc. | Heat-dissipating substrate structure with built-in conductive circuits |
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US4005472A (en) * | 1975-05-19 | 1977-01-25 | National Semiconductor Corporation | Method for gold plating of metallic layers on semiconductive devices |
US5045914A (en) * | 1989-12-26 | 1991-09-03 | Motorola, Inc. | Plastic pad array electronic AC device |
JPH06268101A (ja) * | 1993-03-17 | 1994-09-22 | Hitachi Ltd | 半導体装置及びその製造方法、電子装置、リ−ドフレ−ム並びに実装基板 |
KR0139694B1 (ko) * | 1994-05-11 | 1998-06-01 | 문정환 | 솔더 볼을 이용한 반도체 패키지 및 그 제조방법 |
US5973393A (en) * | 1996-12-20 | 1999-10-26 | Lsi Logic Corporation | Apparatus and method for stackable molded lead frame ball grid array packaging of integrated circuits |
US6534337B1 (en) * | 1997-05-15 | 2003-03-18 | Texas Instruments Incorporated | Lead frame type plastic ball grid array package with pre-assembled ball type contacts |
JPH11274367A (ja) * | 1998-02-17 | 1999-10-08 | Texas Instr Inc <Ti> | ボ―ルグリッドアレ―パッケ―ジの成形方法 |
US6451624B1 (en) * | 1998-06-05 | 2002-09-17 | Micron Technology, Inc. | Stackable semiconductor package having conductive layer and insulating layers and method of fabrication |
JP3798597B2 (ja) * | 1999-11-30 | 2006-07-19 | 富士通株式会社 | 半導体装置 |
JP2001339011A (ja) * | 2000-03-24 | 2001-12-07 | Shinko Electric Ind Co Ltd | 半導体装置およびその製造方法 |
DE10110203B4 (de) * | 2001-03-02 | 2006-12-14 | Infineon Technologies Ag | Elektronisches Bauteil mit gestapelten Halbleiterchips und Verfahren zu seiner Herstellung |
JP3418385B2 (ja) * | 2001-08-10 | 2003-06-23 | 沖電気工業株式会社 | 半導体集積回路パッケージの形成方法およびその製造方法 |
JP4014912B2 (ja) * | 2001-09-28 | 2007-11-28 | 株式会社ルネサステクノロジ | 半導体装置 |
KR20040026530A (ko) * | 2002-09-25 | 2004-03-31 | 삼성전자주식회사 | 반도체 패키지 및 그를 이용한 적층 패키지 |
US6798057B2 (en) * | 2002-11-05 | 2004-09-28 | Micron Technology, Inc. | Thin stacked ball-grid array package |
JP4204989B2 (ja) * | 2004-01-30 | 2009-01-07 | 新光電気工業株式会社 | 半導体装置及びその製造方法 |
US7667338B2 (en) * | 2006-08-08 | 2010-02-23 | Lin Paul T | Package with solder-filled via holes in molding layers |
US7763493B2 (en) * | 2007-06-26 | 2010-07-27 | Stats Chippac Ltd. | Integrated circuit package system with top and bottom terminals |
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US20090121361A1 (en) | 2009-05-14 |
US20120049362A1 (en) | 2012-03-01 |
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