JP2021168398A - Semiconductor device - Google Patents

Abstract

To improve reliability of a light emitting device.SOLUTION: A light emitting device has a driving circuit which includes a driving circuit transistor and a pixel part including a pixel transistor on the same substrate in which the driving circuit transistor and the pixel transistor are inverted staggered transistors each including an oxide semiconductor layer partially contacting an oxide insulation layer. The pixel part includes a color filter layer and a light emitting element which are provided on the oxide insulation layer. The driving circuit transistor includes a conductive layer which overlaps a gate electrode layer and the oxide semiconductor layer, on the oxide insulation layer. Note that, the gate electrode layer, a source electrode layer and a drain electrode layer use a metal conductive film.SELECTED DRAWING: Figure 1

Description

The present invention relates to a light emitting device having a layer containing an organic compound as a light emitting layer and a method for producing the same. For example, the present invention relates to an electronic device equipped with a light emitting display device having an organic light emitting element as a component.

In the present specification, the semiconductor device refers to all devices that can function by utilizing the semiconductor characteristics, and the electro-optical device such as a light emitting device, the semiconductor circuit, and the electronic device are all semiconductor devices.

A light emitting element using an organic compound having features such as thinness and light weight, high-speed response, and DC low-voltage drive as a light emitting body is being studied for application to next-generation flat panel displays and next-generation lighting. In particular, a display device in which light emitting elements are arranged in a matrix is considered to be superior in that it has a wide viewing angle and excellent visibility as compared with a conventional liquid crystal display device.

The light emitting mechanism of the light emitting element is a molecule in which electrons injected from the cathode and holes injected from the anode recombine at the light emitting center of the EL layer by applying a voltage with an EL layer sandwiched between a pair of electrodes. It is said that excitons are formed, and when the molecular excitons relax to the ground state, they release energy and emit light. Singlet and triplet excitations are known as excited states, and it is considered that light emission is possible through either excited state.

The EL layer constituting the light emitting element has at least a light emitting layer. Further, the EL layer may have a laminated structure having a hole injection layer, a hole transport layer, an electron transport layer, an electron injection layer and the like in addition to the light emitting layer.

Further, metal oxides are attracting attention as a material exhibiting semiconductor characteristics. Examples of metal oxides exhibiting semiconductor characteristics include tungsten oxide, tin oxide, indium oxide, zinc oxide, and the like, and thin film transistors having metal oxides exhibiting such semiconductor characteristics as channel forming regions are already known. (Patent Document 1 and Patent Document 2).

Further, the TFT to which the oxide semiconductor is applied has a high field effect mobility. Therefore, the TFT
Can also be used to configure a drive circuit such as a display device.

Japanese Unexamined Patent Publication No. 2007-123861 JP-A-2007-96055

A thin film transistor using an oxide semiconductor film is required to have a high operating speed, a relatively simple manufacturing process, and sufficient reliability.

One of the issues is to improve the operating characteristics and reliability of a thin film transistor using an oxide semiconductor film.

In particular, the operating speed of the thin film transistor used in the drive circuit is preferably high.

For example, if the channel length (L) of the thin film transistor is shortened or the channel width W is widened, the operating speed is increased. However, if the channel length is shortened, there is a problem that the switching characteristic, for example, the on / off ratio becomes small. Further, if the channel width W is widened, there is a problem that the capacitance load of the thin film transistor itself is increased.

Another issue is to provide a light emitting device provided with a thin film transistor having stable electrical characteristics even if the channel length is short.

Further, when a plurality of different circuits are formed on the insulating surface, for example, when the pixel portion and the drive circuit are formed on the same substrate, the thin film transistor used for the pixel portion has excellent switching characteristics, for example, a large on / off ratio. The thin film transistor used in the drive circuit is required to have a high operating speed. In particular, the higher the definition of the display device, the higher the definition.
Since the writing time of the display image is shortened, it is preferable that the thin film transistor used in the drive circuit has a high operating speed.

Another issue is to reduce variations in the electrical characteristics of thin film transistors that use oxide semiconductor films.

One form of the light emitting device of the present invention has a drive circuit unit including a drive circuit transistor and a pixel unit including a pixel transistor on the same substrate, and the drive circuit transistor and the pixel transistor have a gate electrode layer. , The gate insulating layer on the gate electrode layer, the oxide semiconductor layer on the gate insulating layer, the source electrode layer and the drain electrode layer on the oxide semiconductor layer, and the oxide semiconductor layer, the source electrode layer and the drain electrode layer. Has an oxide insulating layer in contact with a part of the oxide semiconductor layer.
In the pixel portion, a color filter layer is provided on the oxide insulating layer, and a first electrode layer, an EL layer, and a second electrode layer that are electrically connected to the pixel transistor are provided on the color filter layer, and are used for a drive circuit. In the transistor, a conductive layer that overlaps the gate electrode layer and the oxide semiconductor layer is provided on the oxide insulating layer, and the gate electrode layer, the source electrode layer, and the drain electrode layer are metal conductive films.

Another form of the light emitting device of the present invention has a drive circuit unit including a drive circuit transistor and a pixel unit including a pixel transistor on the same substrate, and the drive circuit transistor and the pixel transistor are gate electrodes. Layer, gate insulating layer on gate electrode layer, oxide semiconductor layer on gate insulating layer, source electrode layer and drain electrode layer on oxide semiconductor layer, oxide semiconductor layer, source electrode layer and drain electrode An oxide insulating layer in contact with a part of the oxide semiconductor layer is provided on the layer, and in the pixel portion, the color filter layer is placed on the oxide insulating layer, and the pixel transistor and the connecting electrode layer are electrically placed on the color filter layer. A first electrode layer, an EL layer, and a second electrode layer are laminated, and in the drive circuit transistor, a conductive layer that overlaps with the gate electrode layer and the oxide semiconductor layer is provided on the oxide insulating layer. , The gate electrode layer, the source electrode layer and the drain electrode layer are metal conductive films.

A reverse staggered transistor having a bottom gate structure is used as a pixel transistor and a drive circuit transistor. The pixel transistor and the drive circuit transistor are channel-etched transistors provided with an oxide insulating film in contact with the exposed oxide semiconductor layer between the source electrode layer and the drain electrode layer.

The drive circuit transistor has a configuration in which an oxide semiconductor layer is sandwiched between a gate electrode and a conductive layer. As a result, it is possible to reduce the variation in the threshold value of the transistor, and it is possible to provide a light emitting device having a transistor having stable electrical characteristics. The conductive layer may have the same potential as the gate electrode layer, may be a floating potential, or may have a fixed potential, for example, GN.
It may be D potential or 0V. Further, the threshold value of the transistor can be controlled by giving an arbitrary potential to the conductive layer.

The pixel transistor and the pixel electrode may be formed in direct contact with each other, or may be electrically connected to each other via a connection electrode layer. The connection electrode layer is Al, Cr, Cu, Ta, Ti, Mo,
A film containing an element selected from W as a main component or a laminated film in combination with an alloy film thereof can be used.

The conductive layer, the first wiring (also referred to as a terminal or a connecting electrode), and the second wiring (also referred to as a terminal or a connecting electrode) provided on the oxide semiconductor layer of the drive circuit transistor are in the same process as the pixel electrode. It may be formed using an oxide conductive material such as indium oxide, indium tin oxide alloy, indium zinc oxide alloy, or zinc oxide, or Al, Cr, Cu, Ta, in the same step as the connection electrode layer. It may be formed by using a metal material such as a film containing an element selected from Ti, Mo, and W as a main component, or an alloy film thereof.

Further, it is possible to manufacture a light emitting device such as a display by forming a light emitting element having a plurality of kinds of light emitting colors and a transistor for pixels electrically connected to the light emitting element on the same substrate.

Further, a plurality of white light emitting elements may be provided, and an optical film, specifically, a color filter may be provided so as to overlap the light emitting regions of the respective light emitting elements to form a full-color light emitting display device. Here, the color filter does not mean the entire film having three color filter layers (red color filter, blue color filter, green color filter, etc.) including a black matrix and an overcoat, but one. Refers to a color filter of one color.

One embodiment of the method for manufacturing a light emitting device of the present invention for realizing the above structure is to form a gate electrode layer using a metal conductive film on a substrate having an insulating surface including a drive circuit portion and a pixel portion, and to form a gate electrode. After forming a gate insulating layer on the layer, forming an oxide semiconductor layer on the gate insulating layer, dehydrating or dehydrogenating the oxide semiconductor layer, water to the oxide semiconductor layer without contacting the atmosphere. To prevent re-mixing of hydrogen and hydrogen, a source electrode layer and a drain electrode layer are formed on the oxide semiconductor layer using a metal conductive film, and an oxide semiconductor layer is formed on the oxide semiconductor layer, the source electrode layer and the drain electrode layer. An oxide insulating layer in contact with a part of the above is formed, a drive circuit transistor is formed in the drive circuit portion, and a pixel transistor is formed in the pixel portion. A first electrode layer electrically connected to the pixel transistor is formed on the filter layer, an EL layer is formed on the first electrode layer, and a second electrode layer is formed on the EL layer. A conductive layer is formed on the oxide insulating layer that overlaps the gate electrode layer and the oxide semiconductor layer of the drive circuit transistor in the same process as the first electrode layer.

One embodiment of the method for manufacturing the light emitting device of the present invention for realizing the above structure is to form a gate electrode layer using a metal conductive film on a substrate having an insulating surface including a drive circuit portion and a pixel portion, and to form a gate electrode. After forming a gate insulating layer on the layer, forming an oxide semiconductor layer on the gate insulating layer, and dehydrating or dehydrogenating the oxide semiconductor layer, water to the oxide semiconductor layer is not exposed to the atmosphere. To prevent re-mixing of hydrogen and hydrogen, a source electrode layer and a drain electrode layer are formed on the oxide semiconductor layer using a metal conductive film, and an oxide semiconductor layer is formed on the oxide semiconductor layer, the source electrode layer and the drain electrode layer. An oxide insulating layer in contact with a part of the oxide insulating layer is formed, a drive circuit transistor is formed in the drive circuit portion, and a pixel transistor is formed in the pixel portion. A first electrode layer that is electrically connected to the pixel transistor via a connection electrode layer is formed on the filter layer, an EL layer is formed on the first electrode layer, and a second electrode layer is formed on the EL layer. ,
In the drive circuit section, a conductive layer is formed on the gate electrode layer of the drive circuit transistor and the oxide insulating layer overlapping the oxide semiconductor layer in the same process as the connection electrode layer.

In the photolithography step in the manufacturing step of the light emitting device described above, the etching step may be performed using a mask layer formed by a multi-gradation mask which is an exposure mask in which the transmitted light has a plurality of intensities.

Since the mask layer formed by using the multi-gradation mask has a shape having a plurality of film thicknesses and the shape can be further deformed by etching the mask layer, a plurality of etching steps for processing into different patterns. Can be used for. Therefore, it is possible to form a mask layer corresponding to at least two or more different patterns by using one multi-tone mask. Therefore, the number of exposure masks can be reduced, and the corresponding photolithography process can also be reduced, so that the process can be simplified.

The above configuration solves at least one of the above problems.

Further, the oxide semiconductor used in the present specification _{forms a thin film represented by InMO 3} (ZnO) _m (m> 0), and the thin film is used as the oxide semiconductor layer to produce a thin film transistor. In addition, M represents one metal element selected from Ga, Fe, Ni, Mn and Co, or a plurality of metal elements. For example, M may be Ga, or may contain the above metal elements other than Ga, such as Ga and Ni or Ga and Fe. Further, in the above oxide semiconductor, in addition to the metal element contained as M, there is a case where Fe, Ni or other transition metal element, or an oxide of the transition metal is contained as an impurity element. In this specification, In
Of the oxide semiconductor layers having a structure represented by MO ₃ (ZnO) _m (m> 0), Ga is defined as M.
An oxide semiconductor having a structure containing is called an In-Ga-Zn-O-based oxide semiconductor, and its thin film is called I.
It is also called an n-Ga-Zn-O system non-single crystal film.

In addition to the above, In-Sn-Zn-O can be used as a metal oxide applied to the oxide semiconductor layer.
System, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn
-Al-Zn-O system, In-Zn-O system, Sn-Zn-O system, Al-Zn-O system, In-
O-based, Sn—O-based, and Zn—O-based metal oxides can be applied. Further, silicon oxide may be contained in the oxide semiconductor layer made of the metal oxide.

When the heat treatment is performed in an inert gas atmosphere of nitrogen or a rare gas (argon, helium, etc.), the oxide semiconductor layer becomes oxygen-deficient by the heat treatment, resulting in low resistance, that is, N-type (N-type).
N ^- reduction, etc.) was, then, a high resistance by the oxide semiconductor layer in an oxygen-excess state by performing formation and the oxide insulating film in contact with the oxide semiconductor layer, the heat treatment after formation, i.e. I
It can be said that it is typed. It can also be said that solid-phase oxidation is performed to bring the oxide semiconductor layer into a state of excess oxygen. This makes it possible to manufacture and provide a light emitting device having a thin film transistor having good electrical characteristics and high reliability.

Dehydration or dehydrogenation is carried out by heat-treating nitrogen or a rare gas (argon, helium, etc.) under an inert gas atmosphere at 400 ° C. or higher and 750 ° C. or lower, preferably 425 ° C. or higher and 750 ° C. or lower, and oxides. Reduce impurities such as moisture contained in the semiconductor layer. In addition, the water after that (H ₂₎
Re-impregnation of O) can be prevented.

Heat treatment for dehydration or dehydrogenation is preferably H 2 _O is carried out in a nitrogen atmosphere 20 ppm. Further, it may be carried out in ultra-dry air having _{H 2 O of 20 ppm or less.}

The dehydrated or dehydrogenated oxide semiconductor layer has two peaks of water, at least 300, even when the oxide semiconductor layer after dehydration or dehydrogenation is measured up to 450 ° C. by TDS.
One peak appearing near ° C. is set under heat treatment conditions to the extent that it is not detected. Therefore, for a thin film transistor using a dehydrated or dehydrogenated oxide semiconductor layer, TDS 4
Even if the measurement is performed up to 50 ° C., the peak of water appearing at least around 300 ° C. is not detected.

Then, from the heating temperature T at which the oxide semiconductor layer is dehydrated or dehydrogenated, water or hydrogen may not be mixed again without being exposed to the atmosphere in the same furnace where the dehydration or dehydrogenation was performed. is important. A thin film transistor is produced using an oxide semiconductor layer that has been dehydrated or dehydrogenated to reduce the resistance of the oxide semiconductor layer, that is, to make it N-type (N ^−, etc.), and then to increase the resistance to make it I-type. Then, the threshold voltage (Vth) of the thin film transistor can be made positive, and a so-called normally-off switching element can be realized. It is desirable for a semiconductor device (light emitting device) that a channel is formed at a positive threshold voltage at which the gate voltage of the thin film transistor is as close to 0 V as possible. If the threshold voltage of the thin film transistor is negative, a current flows between the source electrode and the drain electrode even if the gate voltage is 0 V, which tends to be a so-called normally-on. In the active matrix type display device, the electrical characteristics of the thin film transistors constituting the circuit are important, and these electrical characteristics affect the performance of the display device.
In particular, the threshold voltage is important among the electrical characteristics of the thin film transistor. Even if the electric field effect mobility is high, if the threshold voltage value is high or the threshold voltage value is negative, it is difficult to control the circuit. In the case of a thin film transistor having a high threshold voltage value and a large absolute value of the threshold voltage, the switching function as a TFT cannot be fulfilled when the drive voltage is low, which may cause a load. In the case of n-channel thin film transistor
A transistor in which a channel is formed only when a positive voltage is applied to the gate voltage and a drain current flows out is desirable. A transistor in which a channel is not formed unless the drive voltage is increased, or a transistor in which a channel is formed and a drain current flows even in a negative voltage state is not suitable as a thin film transistor used in a circuit.

Further, the gas atmosphere lowered from the heating temperature T may be switched to a gas atmosphere different from the gas atmosphere raised to the heating temperature T. For example, without being exposed to the air in the same furnace to perform dehydration or dehydrogenation, high-purity oxygen gas or the N _{2 O} gas in the furnace, ultra-dry air (having a dew point of -40 ℃ or less, preferably - Fill with 60 ° C. or lower) to cool.

After reducing the water content in the membrane by heat treatment for dehydration or dehydrogenation, slow cooling (or cooling) in a water-free atmosphere (dew point is -40 ° C or lower, preferably -60 ° C or lower).
The oxide semiconductor film is used to improve the electrical characteristics of the thin film transistor and to realize a thin film transistor having both mass productivity and high performance.

In the present specification, the heat treatment of nitrogen or a rare gas (argon, helium, etc.) under an inert gas atmosphere is referred to as a heat treatment for dehydration or dehydrogenation. In the present specification, dehydrogenation is not only referred to as dehydrogenation as _{H 2 by this heat treatment.}
, OH, etc. will be referred to as dehydration or dehydrogenation for convenience, including desorption.

When the heat treatment is performed in an inert gas atmosphere of nitrogen or a rare gas (argon, helium, etc.), the oxide semiconductor layer becomes oxygen-deficient by the heat treatment, resulting in low resistance, that is, N-type (N-type).
N ^- of, etc.) make.

In addition, a high resistance drain region (HRD (High)) that is an oxygen-deficient type that overlaps with the drain electrode layer
A Response Drain) region) is formed. In addition, a high resistance source region (HRS (High Resistanc)) that is an oxygen-deficient type that overlaps with the source electrode layer.
The e Source) region) is formed.

Specifically, the carrier concentration in the high resistance drain region is in ^{the range of 1 × 10 18} / cm ³ or more, and at least in a region higher than ^{the carrier concentration in the channel formation region (less than 1 × 10 18} / cm ^3). be. The carrier concentration in the present specification refers to the value of the carrier concentration obtained from the Hall effect measurement at room temperature.

After that, at least a part of the dehydrated or dehydrogenated oxide semiconductor layer is brought into a state of excess oxygen to increase the resistance, that is, to form an I type to form a channel forming region. The treatment for making a part of the dehydrated or dehydrogenated oxide semiconductor layer in an oxygen-excessive state is performed by any of the following methods. An oxide insulating film in contact with the dehydrated or dehydrogenized oxide semiconductor layer is formed by a sputtering method, or an oxide insulating film is formed so as to be in contact with the dehydrated or dehydrogenated oxide semiconductor layer. Further heat treatment is performed, or an oxide insulating film is formed so as to be in contact with the dehydrated or dehydrogenated oxide semiconductor layer, and further heat treatment is performed in an atmosphere containing oxygen, or dehydration or dehydrogenation is performed. After forming an oxide insulating film so as to be in contact with the oxide semiconductor layer, it is heated in an inert gas atmosphere and further cooled in an oxygen atmosphere, or is in contact with a dehydrated or dehydrogenated oxide semiconductor layer. After the oxide insulating film is formed as described above, it is heated in an inert gas atmosphere, and further cooled with ultra-dry air (dew point is −40 ° C. or lower, preferably −60 ° C. or lower).

Further, since at least a part of the dehydrated or dehydrogenated oxide semiconductor layer (the part overlapping the gate electrode layer) is used as the channel forming region, the resistance is increased by selectively setting the oxygen excess state, that is, It can also be type I. A source electrode layer or drain electrode layer made of a metal electrode such as Ti is formed in contact with a dehydrated or dehydrogenated oxide semiconductor layer, and an exposed region that does not overlap the source electrode layer or drain electrode layer is selectively oxygenated. A channel formation region can be formed as an excess state. When the oxygen is selectively excessive, a first high resistance source region overlapping the source electrode layer and a second high resistance drain region overlapping the drain electrode layer are formed, and the first high resistance source region and the first high resistance source region are formed. The region between the second high resistance drain region and the second high resistance drain region is the channel formation region. That is, the channel forming region is formed in a self-aligned manner between the source electrode layer and the drain electrode layer.

This makes it possible to manufacture and provide a light emitting device having a thin film transistor having good electrical characteristics and high reliability.

By forming a high resistance drain region in the oxide semiconductor layer superimposed on the drain electrode layer, it is possible to improve the reliability when the drive circuit is formed. Specifically, by forming the high resistance drain region, it is possible to form a structure in which the conductivity can be changed stepwise from the drain electrode layer to the high resistance drain region and the channel formation region. Therefore, when operating by connecting to the wiring that supplies the high power supply potential VDD to the drain electrode layer, even if a high electric field is applied between the gate electrode layer and the drain electrode layer, the high resistance drain region becomes a buffer and is local. A high electric field is not applied, and the withstand voltage of the thin film transistor can be improved.

Further, by forming a high resistance drain region and a high resistance source region in the oxide semiconductor layer superimposed on the drain electrode layer and the source electrode layer, the leakage current in the channel formation region when the drive circuit is formed can be reduced. Can be planned. Specifically, by forming a high resistance drain region, the drain electrode layer, the high resistance drain region on the drain electrode layer side, and the channel can be used as a path for the leakage current of the transistor flowing between the drain electrode layer and the source electrode layer. The order is the formation region, the high resistance source region on the source electrode layer side, and the source electrode layer. At this time, in the channel formation region, the leakage current flowing from the high resistance drain region on the drain electrode layer side to the channel region can be concentrated near the interface between the gate insulating layer and the channel formation region, which have high resistance when the transistor is off. Leakage current in the back channel portion (a part of the surface of the channel forming region away from the gate electrode layer) can be reduced.

Further, the high resistance source region overlapping the source electrode layer and the high resistance drain region overlapping the drain electrode layer overlap with a part of the gate electrode layer via the gate insulating layer, depending on the width of the gate electrode layer. The electric field strength near the end of the drain electrode layer can be effectively relaxed.

Further, an oxide conductive layer may be formed between the oxide semiconductor layer and the source electrode and the drain electrode. The oxide conductive layer preferably contains zinc oxide as a component, and preferably does not contain indium oxide. For example, zinc oxide, zinc aluminum oxide, zinc aluminum oxynitride, gallium zinc oxide and the like can be used. The oxide conductive layer has a low resistance drain region (LRN (Low Resistance N-type conduct).
It also functions as an ivity) region and an LRD (Low Response Drain) region). Specifically, the carrier concentration in the low resistance drain region is larger than that in the high resistance drain region (HRD region), for example, 1 × 10 ²⁰ / cm ³ or more and 1 × 10 ²¹ / c.
It is preferably within the range of m ^{3 or less.} By providing the oxide conductive layer between the oxide semiconductor layer and the source electrode and the drain electrode, the contact resistance can be reduced and the high-speed operation of the transistor can be realized, so that the frequency characteristics of the peripheral circuit (drive circuit) can be improved. Can be improved.

The oxide conductive layer and the metal layer for forming the source electrode and the drain electrode can be continuously formed.

Further, the first wiring and the second wiring described above may be laminated wiring composed of the same material and metal material as the oxide conductive layer functioning as LRN or LRD. By laminating the metal and the oxide conductive layer, the covering property against the step over the lower layer wiring and the opening can be improved, and the wiring resistance can be reduced. Further, since the effect of locally increasing the resistance of the wiring and preventing the disconnection due to migration or the like can be expected, it is possible to provide a highly reliable light emitting device.

Further, also when connecting the first wiring and the second wiring described above, the insulating oxide is formed on the metal surface of the connecting portion (contact portion) by connecting the oxide conductive layer with the oxide conductive layer sandwiched between them. It can be expected to prevent an increase in contact resistance (contact resistance) due to this, and a highly reliable light emitting device can be provided.

Further, since the thin film transistor is easily destroyed by static electricity or the like, it is preferable to provide a protection circuit for protecting the thin film transistor in the pixel portion on the same substrate with respect to the gate line or the source line. The protection circuit is preferably configured by using a non-linear element using an oxide semiconductor layer.

The ordinal numbers attached as the first and second numbers are used for convenience and do not indicate the process order or the stacking order. In addition, this specification does not indicate a unique name as a matter for specifying the invention.

By using an oxide semiconductor layer, it is possible to realize a light emitting device which is a semiconductor device equipped with a thin film transistor having excellent electrical characteristics and reliability.

The figure explaining the light emitting device. The figure explaining the manufacturing method of the light emitting device. The figure explaining the manufacturing method of the light emitting device. The figure explaining the manufacturing method of the light emitting device. The figure explaining the manufacturing method of the light emitting device. The figure explaining the manufacturing method of the light emitting device. The figure explaining the manufacturing method of the light emitting device. The figure explaining the manufacturing method of the light emitting device. The figure explaining the manufacturing method of the light emitting device. The figure explaining the light emitting device. The figure explaining the light emitting device. The figure explaining the block diagram of a light emitting device. The figure explaining the structure of the signal line drive circuit. The circuit diagram which shows the structure of the shift register. A timing chart for explaining the circuit diagram and operation of the shift register. The figure explaining the light emitting device. The figure explaining the manufacturing method of the light emitting device. The figure explaining the manufacturing method of the light emitting device. The figure explaining the pixel equivalent circuit of a light emitting device The figure explaining the light emitting device. The figure explaining the light emitting element. The figure explaining the light emitting device. The figure which shows the electronic device. The figure which shows the electronic device. The figure which shows the electronic device. The figure which shows the electronic device.

The embodiment will be described in detail with reference to the drawings. However, it is not limited to the following description, and it is easily understood by those skilled in the art that a person skilled in the art can change the form and details in various ways without departing from the purpose and the scope thereof. Therefore, the interpretation is not limited to the description of the embodiments shown below. In the configuration described below, the same reference numerals are commonly used between different drawings for the same parts or parts having similar functions, and the repeated description thereof will be omitted.

(Embodiment 1)
FIGS. 1 to 5 and 11 show a light emitting device including a thin film transistor and a manufacturing process thereof.
Will be described with reference to.

A light emitting device according to an embodiment of the present invention is shown in FIG. The light emitting device of FIG. 1 has a pixel unit including a light emitting element, a thin film transistor 170, and a capacity of 147, and a thin film transistor 180 on a substrate 100.
A drive circuit unit including the above is provided, and a first terminal 121 is further provided at the terminal portion of the gate wiring.
, The connection electrode 120, the terminal electrode 128 for connection, and the second terminal 1 at the terminal portion of the source wiring.
22 and a terminal electrode 129 for connection are provided. Further, an oxide insulating film 107 and a protective insulating layer 106 are formed on the thin film transistor 180 and the thin film transistor 170.

The light emitting element is composed of a stack of a first electrode layer 110, an EL layer 194, and a second electrode layer 195, and is formed by contacting the drain electrode layer of the thin film transistor 170 with the first electrode layer 110. , Electrically connected to the thin film transistor 170. In the pixel part
A color filter layer 191 is formed on the protective insulating layer 106, and the color filter layer 191 is covered with an overcoat layer 192 and further covered with a protective insulating layer 109. 1st
The electrode layer 110 is formed on the protective insulating layer 109. Further, a partition wall 193 that separates the light emitting elements is formed on the thin film transistor 170.

In the drive circuit section, the thin film transistor 180 is provided with a conductive layer 111 above the gate electrode layer and the semiconductor layer, and the drain electrode layer 165b is electrically connected to the conductive layer 162 formed in the same process as the gate electrode layer. ..

Hereinafter, the production method will be described in detail with reference to FIGS. 2 to 5 and 11. 2 to 5 correspond to a cross-sectional view of the light emitting device.

After forming a conductive layer on the entire surface of the substrate 100, which is a substrate having an insulating surface, a first photolithography step is performed to form a resist mask, and unnecessary parts are removed by etching to remove unnecessary parts for wiring and electrodes. (Gate electrode layer 101, gate electrode layer 161 and conductive layer 162
, Capacitive wiring layer 108, and first terminal 121). As shown in FIG. 2A, etching so that a tapered shape is formed at the ends of the wiring and the electrode is preferable because the coating property of the film to be laminated is improved. The gate electrode layer 101 and the gate electrode layer 161 are included in the gate wiring, respectively.

There is no major limitation on the substrate that can be used for the substrate 100 having an insulating surface, but at least it is necessary to have heat resistance enough to withstand the subsequent heat treatment. A glass substrate can be used for the substrate 100 having an insulating surface.

Further, as the glass substrate, when the temperature of the subsequent heat treatment is high, it is preferable to use a glass substrate having a strain point of 730 ° C. or higher. Further, for the glass substrate, for example, glass materials such as aluminosilicate glass, aluminoborosilicate glass, and bariumborosilicate glass are used. By adding more barium oxide (BaO) than boric acid, more practical heat-resistant glass can be obtained. _Therefore, it is preferred that from B 2 _{O 3} is used a glass substrate containing more BaO.

Instead of the above glass substrate, a substrate made of an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. In addition, crystallized glass or the like can be used. Since the light emitting device shown in this embodiment is a bottom surface injection type that extracts light emission from the surface on the substrate 100 side,
A translucent substrate is used as the substrate 100, but in the case of a top injection type that extracts light emission from the surface opposite to the substrate 100, a substrate such as a non-translucent metal substrate may be used as the substrate 100. good.

The insulating film to be the base film is the substrate 100, the gate electrode layer 101, the gate electrode layer 161 and the conductive layer 1.
It may be provided between 62, the capacitive wiring layer 108, and the first terminal 121. The undercoat film has a function of preventing the diffusion of impurity elements from the substrate 100, and has a laminated structure of one or more films selected from a silicon nitride film, a silicon oxide film, a silicon nitride film, or a silicon nitride film. Can be formed.

Gate electrode layer 101, gate electrode layer 161, conductive layer 162, capacitive wiring layer 108, and first
The material of the terminal 121 is formed in a single layer or laminated using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, or an alloy material containing these as main components. be able to.

For example, the gate electrode layer 101, the gate electrode layer 161 and the conductive layer 162, the capacitive wiring layer 108,
The two-layer laminated structure of the first terminal 121 is a two-layer laminated structure in which a molybdenum layer is laminated on an aluminum layer, a two-layer structure in which a molybdenum layer is laminated on a copper layer, or a copper layer. It is preferable to have a two-layer structure in which a titanium nitride layer or tantalum nitride is laminated, or a two-layer structure in which a titanium nitride layer and a molybdenum layer are laminated. The three-layer laminated structure is preferably a laminate in which a tungsten layer or tungsten nitride, an alloy of aluminum and silicon, an alloy of aluminum and titanium, and titanium nitride or a titanium layer are laminated.

Next, the gate electrode layer 101, the gate electrode layer 161 and the conductive layer 162, the capacitive wiring layer 108,
And a gate insulating layer 102 is formed on the first terminal 121 (see FIG. 2 (A)).

The gate insulating layer 102 is formed by using a plasma CVD method, a sputtering method, or the like to form a silicon oxide layer, a silicon nitride layer, a silicon nitride layer, a silicon nitride layer, or an aluminum oxide layer as a single layer or by laminating them. Can be done. For example, a silicon oxide layer may be formed by a plasma CVD method using _{SiH 4} , oxygen and nitrogen as the film forming gas. The film thickness of the gate insulating layer 102 is 100 nm or more and 500 nm or less, and in the case of lamination, for example, the film thickness is 50 nm or more 2
On the first gate insulating layer of 00 nm or less and the first gate insulating layer, the film thickness is 5 nm or more and 300 n.
A second gate insulating layer of m or less is laminated.

In the present embodiment, a silicon nitride layer having a film thickness of 200 nm or less is formed as the gate insulating layer 102 by a plasma CVD method.

Next, the oxide semiconductor film 13 having a film thickness of 2 nm or more and 200 nm or less is placed on the gate insulating layer 102.
Form 0 (see FIG. 2B).

Before forming the oxide semiconductor film by the sputtering method, it is preferable to perform reverse sputtering in which argon gas is introduced to generate plasma to remove dust adhering to the surface of the gate insulating layer 102. Reverse sputtering is a method of modifying the surface by applying a voltage to the substrate side using an RF power supply in an argon atmosphere to form plasma in the vicinity of the substrate. Nitrogen, helium, or the like may be used instead of the argon atmosphere. Further, oxygen argon, may be carried out in an atmosphere or the like is added N 2 _O. Also, Cl in an argon atmosphere
_{2. It} may be performed in an atmosphere in which CF _{4, etc. are added.}

Even if heat treatment for dehydration or dehydrogenation is performed after the formation of the oxide semiconductor film 130, the oxide semiconductor film is in an amorphous state, so that the film thickness is preferably as thin as 50 nm or less.
When heat treatment is performed after the oxide semiconductor layer is formed by reducing the film thickness of the oxide semiconductor film,
It is possible to suppress crystallization.

The oxide semiconductor film 130 includes an In-Ga-Zn-O-based non-single crystal film, an In-Sn-Zn-O system, an In-Al-Zn-O system, a Sn-Ga-Zn-O system, and Al-Ga. -Zn-O system, Sn-
Al-Zn-O system, In-Zn-O system, Sn-Zn-O system, Al-Zn-O system, In-O
A system, Sn—O system, or Zn—O system oxide semiconductor film is used. In this embodiment, In-Ga
A film is formed by a sputtering method using a −Zn—O oxide semiconductor target. again,
The oxide semiconductor film 130 can be formed by a sputtering method under a noble gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically argon) and an oxygen atmosphere. When the sputtering method is used, _{a film is formed using a target containing SiO 2 in an amount} of 2% by weight or more and 10% by weight or less, and the oxide semiconductor film 130 is impregnated with SiOx (x> 0) that inhibits crystallization. It is preferable to prevent crystallization during the heat treatment for dehydration or dehydrogenation performed in a later step.

Here, an oxide semiconductor target containing In, Ga, and Zn (In ₂ O ₃ : Ga ₂ O).
₃ : ZnO = 1: 1: 1 [mol%], In: Ga: Zn = 1: 1: 0.5 [at%])
The distance between the substrate and the target is 100 mm, the pressure is 0.2 Pa, and the direct current (DC) is used.
The film is formed under a power source of 0.5 kW and an atmosphere of argon and oxygen (argon: oxygen = 30 sccm: 20 sccm, oxygen flow rate ratio 40%). It is preferable to use a pulsed direct current (DC) power source because dust can be reduced and the film thickness distribution becomes uniform. The film thickness of the In-Ga-Zn-O-based non-single crystal film is 5 nm or more and 200 nm or less. In the present embodiment, an In-Ga-Zn-O-based non-single crystal film having a thickness of 20 nm is formed as the oxide semiconductor film by a sputtering method using an In-Ga-Zn-O-based oxide semiconductor target. ..

The sputtering method includes an RF sputtering method in which a high-frequency power source is used as a power source for sputtering, a DC sputtering method, and a pulse DC sputtering method in which a pulse bias is applied. The RF sputtering method is mainly used when forming an insulating film, and DC.
The sputtering method is mainly used when forming a metal film.

There is also a multi-dimensional sputtering device that can install a plurality of targets made of different materials. The multi-dimensional sputtering apparatus can form a laminated film of different material films in the same chamber, or can simultaneously discharge a plurality of types of materials in the same chamber to form a film.

In addition, a sputtering device that uses a magnetron sputtering method with a magnet mechanism inside the chamber, or an E that uses plasma generated using microwaves without using glow discharge.
There is a sputtering apparatus that uses the CR sputtering method.

Further, as a film forming method using a sputtering method, a reactive sputtering method in which a target substance and a sputtering gas component are chemically reacted to form a thin film of these compounds during film formation, or a voltage is applied to a substrate during film formation. There is also a bias sputtering method.

Next, a second photolithography step is performed on the oxide semiconductor film 130 to form a resist mask 137, and unnecessary portions of the oxide semiconductor film 130 and the gate insulating layer 102 are removed by etching to remove the gate insulating layer. A contact hole 119 reaching the first terminal 121 and a contact hole 118 reaching the conductive layer 162 are formed in 102 (see FIG. 2C).
).

When the step of forming a contact hole in the gate insulating layer 102 is performed in the state where the oxide semiconductor film 130 is laminated on the entire surface of the gate insulating layer 102 in this way, the resist mask does not come into direct contact with the surface of the gate insulating layer 102. Contamination of the surface of the gate insulating layer 102 (adhesion of impurities and the like) can be prevented. Therefore, the interface state between the gate insulating layer 102 and the oxide semiconductor film 130 can be improved, which leads to improvement in reliability.

A resist pattern may be formed directly on the gate insulating layer to open a contact hole. In that case, heat treatment is performed after the resist is peeled off to dehydrate the surface of the gate insulating film.
It is preferable to carry out dehydrogenation and dehydroxylation treatments. For example, the inert gas atmosphere (nitrogen,
Alternatively, heat treatment (400 ° C. or higher and 750 ° C. or lower) may be performed under an oxygen atmosphere under helium, neon, argon, etc. to remove impurities such as hydrogen and water contained in the gate insulating layer.

Next, the resist mask 137 is removed, and the oxide semiconductor film 130 is etched with the resist masks 135a and 135b formed by the third photolithography step to form island-shaped oxide semiconductor layers 131 and 132 (the island-shaped oxide semiconductor layers 131 and 132 are formed). See FIG. 3 (A).). Further, the resist masks 135a and 135b for forming the island-shaped oxide semiconductor layer may be formed by an inkjet method. When the resist mask is formed by the inkjet method, the photomask is not used, so that the manufacturing cost can be reduced.

Next, the oxide semiconductor layers 131 and 132 are dehydrated or dehydrogenated to form the dehydrated or dehydrogenated oxide semiconductor layers 133 and 134 (see FIG. 3B). The temperature of the first heat treatment for dehydration or dehydrogenation is 400 ° C. or higher and 750 ° C. or lower, preferably 4.
The temperature is 25 ° C or higher and 750 ° C or lower. If the temperature is 425 ° C. or higher, the heat treatment time may be 1 hour or less, but if the temperature is lower than 425 ° C., the heat treatment time is longer than 1 hour.
Here, after introducing the substrate into an electric furnace, which is one of the heat treatment devices, and heat-treating the oxide semiconductor layer in a nitrogen atmosphere, water is applied to the oxide semiconductor layer without touching the atmosphere. And hydrogen are prevented from being remixed, and oxide semiconductor layers 133 and 134 are obtained. In the present embodiment, the same furnace is used from the heating temperature T for dehydrating or dehydrogenating the oxide semiconductor layer to a sufficient temperature at which water does not enter again, specifically 100 than the heating temperature T. Slowly cool in a nitrogen atmosphere until the temperature drops to ℃ or higher. Further, dehydration or dehydrogenation is performed in a noble gas atmosphere such as helium, neon, and argon without being limited to a nitrogen atmosphere.

The oxide semiconductor layer by heat treatment at a temperature of 700 ° C. from 400 ° C., the dehydration of the oxide semiconductor layer, the dehydrogenation is achieved, it is possible to prevent subsequent re-impregnation water (H 2 _O) ..

The heat treatment device is not limited to the electric furnace, and for example, GRTA (Gas Rapid Th).
ermal Anneal) device, LRTA (Lamp Rapid Thermal)
An RTA (Rapid Thermal Anneal) device such as an Anneal) device can be used. The LRTA device is a device that heats an object to be processed by radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high pressure sodium lamps, and high pressure mercury lamps. Also, LR
The TA device may include not only a lamp but also a device that heats an object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element. GRTA is a method of performing heat treatment using a high-temperature gas. As the gas, a rare gas such as argon or an inert gas such as nitrogen that does not react with the object to be treated by heat treatment is used. 600 using the RTA method
Heat treatment may be performed at ° C. to 750 ° C. for several minutes.

In the first heat treatment, it is preferable that nitrogen or a rare gas such as helium, neon, or argon does not contain water, hydrogen, or the like. 400 ° C, especially for the oxide semiconductor layer
Dehydration performed at to 750 ° C., a heat treatment of the dehydrogenation is _{preferably H 2} O is carried out in a nitrogen atmosphere 20 ppm. Alternatively, the purity of nitrogen or a rare gas such as helium, neon, or argon to be introduced into the heat treatment apparatus is 6N (99.99999%) or more, preferably 7N (preferably 7N).
99.99999% or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm)
The following) is preferable.

Further, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, it may be crystallized to become a microcrystalline film or a polycrystalline film. For example, it may be a microcrystalline oxide semiconductor film having a crystallization rate of 90% or more, or 80% or more. Further, depending on the conditions of the first heat treatment or the material of the oxide semiconductor film, an amorphous oxide semiconductor film containing no crystal component may be obtained.

Further, the first heat treatment of the oxide semiconductor layer can also be performed on the oxide semiconductor film 130 before being processed into the island-shaped oxide semiconductor layers 131 and 132. In that case, after the first heat treatment, the substrate is taken out from the heating device and a photolithography step is performed.

In the heat treatment for dehydration and dehydrogenation of the oxide semiconductor layer, after the oxide semiconductor layer is formed, the source electrode and the drain electrode are laminated on the oxide semiconductor layer, and then the passivation film is formed on the source electrode and the drain electrode. After forming the above, any of the above may be performed.

Further, the step of forming the contact holes 118 and 119 in the gate insulating layer 102 as shown in FIG. 2C may be performed after the oxide semiconductor film 130 has been dehydrated or dehydrogenated.

The etching of the oxide semiconductor film here is not limited to wet etching, and dry etching may be used.

Etching gases used for dry etching include chlorine-containing gases (chlorine-based gases such as chlorine (Cl ₂ ), boron chloride (BCl ₃ ), silicon chloride (SiCl ₄ ), and carbon tetrachloride (CC).
l ₄ ) etc.) is preferable.

In addition, a gas containing fluorine (fluorine-based gas, for example, carbon tetrafluoride (CF ₄ ), sulfur fluoride (SF)
₆ ), nitrogen fluoride (NF ₃ ), trifluoromethane (CHF ₃ ), etc.), hydrogen bromide (HBr)
), Oxygen (O ₂ ), a gas obtained by adding a rare gas such as helium (He) or argon (Ar) to these gases, or the like can be used.

As a dry etching method, a parallel plate type RIE (Reactive Ion Etch) is used.
The ing) method and the ICP (Inductively Coupled Plasma) etching method can be used. Etching conditions (the amount of power applied to the coil-shaped electrode, the amount of power applied to the electrode on the substrate side, the electrode temperature on the substrate side, etc.) are appropriately adjusted so that the etching can be performed into a desired processing shape.

As the etching solution used for wet etching, a solution obtained by mixing phosphoric acid, acetic acid and nitric acid, aqueous ammonia (31 wt% hydrogen peroxide: 28 wt% aqueous ammonia: water = 5: 2: 2) and the like can be used. .. Further, ITO07N (manufactured by Kanto Chemical Co., Inc.) may be used.

Further, the etching solution after wet etching is removed by washing together with the etched material. The waste liquid of the etching solution containing the removed material may be purified and the contained material may be reused. By recovering and reusing a material such as indium contained in the oxide semiconductor layer from the waste liquid after etching, resources can be effectively utilized and the cost can be reduced.

Etching conditions (etching liquid, etching time, temperature, etc.) are appropriately adjusted according to the material so that etching can be performed in a desired processing shape.

Next, a metal conductive film made of a metal material is formed on the oxide semiconductor layers 133 and 134 by a sputtering method or a vacuum vapor deposition method.

Examples of the material of the metal conductive film include an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, an alloy containing the above-mentioned elements as a component, an alloy film in which the above-mentioned elements are combined, and the like. Be done. Further, the metal conductive film may have a single-layer structure or a laminated structure of two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on an aluminum film, a Ti film, an aluminum film laminated on the Ti film, and a Ti film formed on the Ti film. Examples thereof include a three-layer structure with a film. In addition, Al contains titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd).
), A film in which a single element or a combination of elements selected from scandium (Sc), an alloy film,
Alternatively, a nitride film may be used.

When heat treatment is performed after the metal conductive film, it is preferable that the metal conductive film has heat resistance to withstand this heat treatment.

Next, a fourth photolithography step is performed to resist masks 136a, 136b, 13
6c, 136d, 136e, 136f, 136g are formed, and unnecessary parts are removed by etching the metal conductive film to remove unnecessary parts, source electrode layer 105a, drain electrode layer 105b, source electrode layer 165a, drain electrode layer 165b, capacitive electrode layer 149. , The connection electrode 120, and the second terminal 122 are formed (see FIG. 3C).

When etching the metal conductive film, the respective materials and etching conditions are appropriately adjusted so that the oxide semiconductor layers 133 and 134 are not removed.

In the present embodiment, a Ti film is used as the metal conductive film, and an In-Ga-Zn-O-based oxide is used for the oxide semiconductor layers 133 and 134 as an etching solution for the oxide semiconductor layers 133 and 134. , Ammonia superwater (31 wt% hydrogen peroxide: 28 wt% ammonia water: water = 5:
2: 2) etc. are used.

In this fourth photolithography step, the connection electrode 120 and the second terminal 122, which are the same materials as the source electrode layers 105a and 165a and the drain electrode layers 105b and 165b, are formed in the terminal portions, respectively. The second terminal 122 is connected to the source wiring (source electrode layer 105a).
, 165a) and electrically connected. Further, the connection electrode 120 is formed in contact with the first terminal 121 in the contact hole 119 and is electrically connected.

The resist masks 136a and 13 for forming the source electrode layer and the drain electrode layer.
6b, 136c, 136d, 136e, 136f, 136g may be formed by an inkjet method. When the resist mask is formed by the inkjet method, the photomask is not used, so that the manufacturing cost can be reduced.

Next, the resist masks 136a, 136b, 136c, 136d, 136e, 136f,
136 g is removed to form an oxide insulating film 107 as a protective insulating film in contact with the oxide semiconductor layers 133 and 134.

At this stage, the oxide semiconductor layers 133 and 134 are formed with regions in contact with the oxide insulating film.
Of this region, the region that overlaps with the oxide insulating film 107 via the gate electrode layer and the gate insulating layer is the channel forming region.

The oxide insulating film 107 has a film thickness of at least 1 nm or more, and can be formed by appropriately using a method such as a sputtering method in which impurities such as water and hydrogen are not mixed in the oxide insulating film 107. In the present embodiment, a silicon oxide film having a film thickness of 300 nm is formed as the oxide insulating film 107 by a sputtering method. The substrate temperature at the time of film formation may be room temperature or higher and 300 ° C. or lower, and in the present embodiment, it is room temperature. The film formation of the silicon oxide film by the sputtering method is performed in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically argon).
And can be done in an oxygen atmosphere. Further, a silicon oxide target or a silicon target can be used as the target. For example, using a silicon target, silicon oxide can be formed by a sputtering method in an oxygen atmosphere. The oxide insulating film formed in contact with the low-resistance oxide semiconductor layer ^{uses an inorganic insulating film that does not contain water, hydrogen ions, OH −,} or other impurities and blocks the invasion of these from the outside. , Typically, a silicon oxide film, a silicon nitride film, an aluminum oxide film, an aluminum oxide nitride, or the like is used.

The second heat treatment (preferably 2) is then performed under an inert gas atmosphere or a nitrogen gas atmosphere.
00 ° C. or higher and 400 ° C. or lower, for example, 250 ° C. or higher and 350 ° C. or lower). For example, a second heat treatment at 250 ° C. for 1 hour is performed in a nitrogen atmosphere. When the second heat treatment is performed, a part of the oxide semiconductor layers 133 and 134 overlapping with the oxide insulating film 107 is heated in a state of being in contact with the oxide insulating film 107.

Through the above steps, the oxide semiconductor layer after film formation is heat-treated for dehydration or dehydrogenation to reduce the resistance, and then a part of the oxide semiconductor layer is selectively selected. It is in a state of excess oxygen.

As a result, in the oxide semiconductor layer 133, the channel forming region 166 overlapping the gate electrode layer 161 becomes type I, and the high resistance source region 167a overlapping the source electrode layer 165a is formed.
The high resistance drain region 167b overlapping the drain electrode layer 165b is formed in a self-aligned manner, and the oxide semiconductor layer 163 is formed. Similarly, in the oxide semiconductor layer 134, the channel forming region 116 overlapping the gate electrode layer 101 is type I, and the high resistance source region 117a overlapping the source electrode layer 105a and the high resistance drain region 117b overlapping the drain electrode layer 105b are formed. Is formed in a self-aligned manner, and the oxide semiconductor layer 103 is formed.

The high resistance drain regions 117b and 167b (and the high resistance drain regions 117b and 167b) in the oxide semiconductor layers 103 and 163 superimposed on the drain electrode layers 105b and 165b (and the source electrode layers 105a and 165a).
Alternatively, by forming the high resistance source regions 117a and 167a), it is possible to improve the reliability when the circuit is formed. Specifically, the high resistance drain regions 117b and 167b
By forming the drain electrode layers 105b and 165b to the high resistance drain region 117b.
, 167b, and the channel formation regions 116 and 166 can be configured so that the conductivity can be changed stepwise. Therefore, when the drain electrode layers 105b and 165b are connected to the wiring that supplies the high power supply potential VDD and operated, even if a high electric field is applied between the gate electrode layers 101 and 161 and the drain electrode layers 105b and 165b, the electric field is high. The resistance drain region serves as a buffer, and a local high electric field is not applied, so that the withstand voltage of the transistor can be improved.

Further, in the oxide semiconductor layers 103 and 163 superimposed on the drain electrode layers 105b and 165b (and the source electrode layers 105a and 165a), the high resistance drain regions 117b and 167b (and the high resistance drain regions 117b and 167b)
Alternatively, by forming the high resistance source regions 117a and 167a), it is possible to reduce the leakage current in the channel formation regions 116 and 166 when the circuit is formed.

In the present embodiment, a silicon oxide film is formed as the oxide insulating film 107 by a sputtering method, and then heat treatment is performed at 250 ° C. to 350 ° C. to expose the oxide semiconductor layer between the source region and the drain region. Oxygen is impregnated and diffused into the oxide semiconductor layer from the portion (channel forming region). By producing the silicon oxide film by the sputtering method, excess oxygen can be contained in the silicon oxide film, and the oxygen can be impregnated and diffused in the oxide semiconductor layer by heat treatment. By impregnating and diffusing oxygen into the oxide semiconductor layer, it is possible to increase the resistance (type I) of the channel region. As a result, a thin film transistor that is normally off can be obtained.

Further, the high resistance source region or the high resistance drain region in the oxide semiconductor layer is formed over the entire film thickness direction when the film thickness of the oxide semiconductor layer is as thin as 15 nm or less, but the film thickness of the oxide semiconductor layer is high. When it is thicker, such as 30 nm or more and 50 nm or less, a part of the oxide semiconductor layer, a region in contact with the source electrode layer or the drain electrode layer and its vicinity become low resistance, and a high resistance source region or a high resistance drain region is formed, and the oxide The region of the semiconductor layer close to the gate insulating film may be type I.

A protective insulating layer may be further formed on the oxide insulating film 107. For example, a silicon nitride film is formed using the RF sputtering method. The RF sputtering method is preferable as a method for forming a protective insulating layer because it has good mass productivity. The protective insulating layer uses an inorganic insulating film that does not contain moisture, hydrogen ions, OH ^−, or other impurities and blocks the invasion of these from the outside, and uses a silicon nitride film, an aluminum nitride film, a silicon oxide film, and the like. Use aluminum nitride or the like. In the present embodiment, the protective insulating layer 106 is formed as the protective insulating layer by using the silicon nitride film. (
See FIG. 4 (A). ).

Through the above steps, a thin film transistor 180 can be manufactured in the drive circuit section, a thin film transistor 170 in the pixel section, and a capacitance 147 can be manufactured on the same substrate. Thin film transistor 17
Reference numerals 0 and 180 are bottom gate type thin film transistors including an oxide semiconductor layer including a high resistance source region, a high resistance drain region, and a channel forming region. Therefore, the thin film transistors 170 and 180 have a configuration in which the high resistance drain region or the high resistance source region serves as a buffer even when a high electric field is applied, and a local high electric field is not applied, so that the withstand voltage of the transistor is improved.

The capacitance 147 is formed by the capacitance wiring layer 108 and the capacitance electrode layer 149 with the gate insulating layer 102 in the capacitance portion as a dielectric.

By forming the drive circuit and the pixel portion on the same substrate, the connection wiring between the drive circuit and the external signal can be shortened, and the light emitting device can be miniaturized and the cost can be reduced.

Next, the color filter layer 191 is formed on the protective insulating layer 106. As the color filter layer, a green color filter layer, a blue color filter layer, a red color filter layer, etc. can be used, and a green color filter layer, a blue color filter layer, and a red color filter layer are sequentially formed. .. Each color filter layer is formed by a printing method, an inkjet method, an etching method using a photolithography technique, or the like. By providing the color filter layer, the alignment between the color filter layer and the light emitting region of the light emitting element can be performed without depending on the bonding accuracy of the sealing substrate. In the present embodiment, the fifth, sixth, and seventh photolithography steps are performed to form each green color filter layer, blue color filter layer, and red color filter layer.

Next, an overcoat layer 192 that covers the color filter layers (green color filter layer, blue color filter layer, and red color filter layer) is formed. Overcoat layer 1
92 uses a translucent resin. In this embodiment, the eighth photolithography step is performed to form the overcoat layer 192.

Here, an example of full-color display using three colors of RGB is shown, but the present invention is not particularly limited and RG is used.
Full-color display may be performed using the four colors of BW.

Next, the protective insulating layer 109 that covers the overcoat layer 192 and the protective insulating layer 106 is formed (see FIG. 4B). The protective insulating layer 109 uses an inorganic insulating film, and uses a silicon nitride film, an aluminum nitride film, a silicon nitride film, aluminum nitride, and the like. Protective insulation layer 109
As for the insulating film having the same composition as that of the protective insulating layer 106, it is preferable because it can be etched in one step when the contact hole is formed later.

Next, a ninth photolithography step is performed to form a resist mask, and the oxide insulating film 1 is formed.
Drain electrode layer 105 by etching 07, protective insulating layer 106, and protective insulating layer 109
A contact hole 125 reaching b is formed and the resist mask is removed (see FIG. 5 (A)). Further, the contact hole 1 that reaches the second terminal 122 by etching here.
27, a contact hole 126 that reaches the connection electrode 120 is also formed. Further, the resist mask for forming the contact hole may be formed by an inkjet method. When the resist mask is formed by the inkjet method, the photomask is not used, so that the manufacturing cost can be reduced.

Next, a light-transmitting conductive film is formed. As the material of the conductive film having translucency, indium oxide (In ₂ O ₃ ), indium tin oxide alloy (In ₂ O _3- SnO ₂ , IT)
(Abbreviated as O) and the like are formed by using a sputtering method, a vacuum vapor deposition method, or the like. As another material of the conductive film having translucency, an Al—Zn—O-based non-single crystal film impregnated with nitrogen, that is, Al—
A Zn—ON-based non-single crystal film, a Zn—O-based non-single crystal film containing nitrogen, or a Sn—Zn—O-based non-single crystal film containing nitrogen may be used. The composition ratio (atomic%) of zinc in the Al-Zn-ON-based non-single crystal film is 47 atomic% or less, which is larger than the composition ratio (atomic%) of aluminum in the non-single crystal film and is non-single. The composition ratio of aluminum in the crystal film (atomic%) is larger than the composition ratio of nitrogen in the non-single crystal film (atom%). Etching treatment of such a material is performed with a hydrochloric acid-based solution. However, since the etching of ITO tends to generate a residue, an indium zinc oxide alloy (In ₂ O _3- ZnO) may be used in order to improve the etching processability.

The unit of the composition ratio of the light-transmitting conductive film is atomic%, and an electron probe microanalyzer (EPMA: Electron Probe X-ray Micro Analyzer) is used.
) Shall be evaluated by analysis.

Next, a tenth photolithography step is performed, a resist mask is formed, and an unnecessary portion of the translucent conductive film is removed by etching to remove the first electrode layer 110, the conductive layer 111, and the like.
The terminal electrodes 128 and 129 are formed and the resist mask is removed.

The capacitance 147 formed by the capacitive wiring layer 108 and the capacitive electrode layer 149 with the gate insulating layer 102 as a dielectric can also be formed on the same substrate. Further, in the light emitting device, the capacitive electrode layer 1
Reference numeral 49 denotes a part of the power supply line, and the capacitance wiring layer 108 is a part of the gate electrode layer of the drive TFT.

The terminal electrodes 128 and 129 formed on the terminal portion serve as electrodes or wiring used for connection with the FPC. The terminal electrode 128 formed on the first terminal 121 via the connection electrode 120 is
It is a terminal electrode for connection that functions as an input terminal for gate wiring. The terminal electrode 129 formed on the second terminal 122 is a connection terminal electrode that functions as an input terminal for source wiring.

Further, FIGS. 11 (A1) and 11 (A2) show a cross-sectional view and a top view of the gate wiring terminal portion at this stage, respectively. FIG. 11 (A1) corresponds to a cross-sectional view taken along the line C1-C2 in FIG. 11 (A2). In FIG. 11A, the conductive film 155 formed on the oxide insulating film 107 is a terminal electrode for connection that functions as an input terminal. In addition, FIG. 11 (A1)
In the terminal portion, the first terminal 151 formed of the same material as the gate wiring and the connection electrode 153 formed of the same material as the source wiring are overlapped with each other via the gate insulating layer 102 and are directly in contact with each other to conduct conduction. There is. Further, the connection electrode 153 and the conductive film 155 are in direct contact with each other through a contact hole provided in the oxide insulating film 107 to conduct conduction.

Further, FIGS. 11 (B1) and 11 (B2) show a cross-sectional view and a top view of the source wiring terminal portion, respectively. Further, FIG. 11 (B1) corresponds to a cross-sectional view taken along the line D1-D2 in FIG. 11 (B2). In FIG. 11 (B1), the conductive film 155 formed on the oxide insulating film 107 is a terminal electrode for connection that functions as an input terminal. Further, in FIG. 11 (B1), in the terminal portion, the electrode 156 formed of the same material as the gate wiring is placed below the second terminal 150 electrically connected to the source wiring via the gate insulating layer 102. Overlap. Electrode 1
56 is not electrically connected to the second terminal 150, and if the electrode 156 is set to a potential different from that of the second terminal 150, for example, floating, GND, 0V, etc., capacitance or static electricity for noise suppression can be obtained. Capacity for countermeasures can be formed. Also, the second terminal 150
Is electrically connected to the conductive film 155 via the oxide insulating film 107.

A plurality of gate wirings, source wirings, and capacitance wirings are provided according to the pixel density. Further, in the terminal portion, a plurality of first terminals having the same potential as the gate wiring, second terminals having the same potential as the source wiring, and third terminals having the same potential as the capacitive wiring are arranged side by side. The number of each terminal may be an arbitrary number, and the practitioner may make an appropriate decision.

The thin film transistor and the holding capacity can be arranged in a matrix corresponding to each pixel to form a pixel portion, and can be used as one substrate for manufacturing an active matrix type display device. In the present specification, such a substrate is referred to as an active matrix substrate for convenience.

By providing the conductive layer 111 at a position overlapping the channel forming region 166 of the oxide semiconductor layer, a bias-thermal stress test (hereinafter referred to as BT) for examining the reliability of the thin film transistor
In the test), the amount of change in the threshold voltage of the thin film transistor 180 before and after the BT test can be reduced. Further, the conductive layer 111 may have the same potential as the gate electrode layer 161 or may have a different potential, and may function as a second gate electrode layer. Further, the potential of the conductive layer 111 may be GND, 0V, or a floating state.

Next, the partition wall 193 is formed so as to cover the peripheral edge of the first electrode layer 110. The partition wall 193 is formed by using an organic resin film such as polyimide, acrylic, polyamide, or epoxy, an inorganic insulating film, or a siloxane-based resin.

The siloxane-based resin is Si—O—S formed using a siloxane-based material as a starting material.
Corresponds to a resin containing an i-bond. As the substituent of the siloxane-based resin, an organic group (for example, an alkyl group or an aryl group) or a fluoro group may be used. Moreover, the organic group may have a fluoro group.

As the partition wall 193, PSG (phosphorus glass), BPSG (phosphorus glass) and the like can also be used. By stacking a plurality of insulating films formed of these materials, the partition wall 1
93 may be formed.

The method for forming the partition wall 193 is not particularly limited, and a sputtering method or SOG can be used depending on the material.
A method, spin coating, dip, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife coater, etc. can be used. Further, as another insulating layer used in the light emitting device, the partition wall 1
The above materials and methods shown as an example of 93 may be used.

The partition wall 193 uses a particularly photosensitive resin material to form an opening on the first electrode layer 110.
It is preferable to form the side wall of the opening so as to be an inclined surface formed with a continuous curvature. When a photosensitive resin material is used as the partition wall 193, the step of forming the resist mask can be omitted. In the present embodiment, the eleventh photolithography step is performed, and the partition wall 1 is performed.
Form 93.

The EL layer 194 is formed on the first electrode layer 110, and the second electrode layer 195 is formed on the EL layer 194 to form a light emitting element. The second electrode layer 195 is electrically connected to the common potential line. Various materials can be used for the second electrode layer 195, but materials having a small work function, for example, alkali metals such as Li and Cs, and alkaline earth metals such as Mg, Ca, and Sr. , And alloys containing these (Mg: Ag, Al: Li, etc.), as well as Yb and E.
Rare earth metals such as r are preferable. In this embodiment, an aluminum film is used as the second electrode layer 195.

In this way, by 11 photolithography steps, using 11 photomasks, a drive circuit unit having a thin film transistor 180, a thin film transistor 170, a pixel unit having a light emitting element, a capacity 147 having a holding capacity, and an external extraction terminal unit. The light emitting device of the present embodiment shown in FIG. 1 can be manufactured.

Further, in the present embodiment, the oxide insulating film 107, the protective insulating layer 106, and the protective insulating layer 10
Although an example in which the contact hole to 9 is formed in one photolithography step is shown, different photomasks may be used and the contact hole may be divided into a plurality of photolithography steps. for example,
A fifth photolithography step is first performed on the oxide insulating film 107 and the protective insulating layer 106 to be the interlayer insulating layer to form contact holes, and the RGB color filter layer is formed by the sixth to ninth photolithography steps. After forming the overcoat layer, a tenth photolithography step may be further performed to form a contact hole in the protective insulating layer 109. In this case, the number of photolithography steps and photomasks is increased by one, and the light emitting device is manufactured by using 12 photolithography steps and 12 photomasks.

In the above-mentioned photolithography step, the etching step may be performed using a mask layer formed by a multi-gradation mask which is an exposure mask in which the transmitted light has a plurality of intensities.

Since the mask layer formed by using the multi-gradation mask has a shape having a plurality of film thicknesses and the shape can be further deformed by etching the mask layer, a plurality of etching steps for processing into different patterns. Can be used for. Therefore, it is possible to form a mask layer corresponding to at least two or more different patterns by using one multi-tone mask. Therefore, the number of exposure masks can be reduced, and the corresponding photolithography process can also be reduced, so that the process can be simplified.

Further, when manufacturing a light emitting device, a power supply line that is electrically connected to the source electrode layer of the driving TFT is provided, and the power supply line intersects the gate wiring and intersects the source wiring, and
It is formed by the same material and the same process as the gate electrode layer.

Further, when manufacturing a light emitting device, one electrode of the light emitting element is electrically connected to the drain electrode layer of the driving TFT, and a common potential line electrically connected to the other electrode of the light emitting element is provided. The common potential line can be formed by the same material and the same process as the gate electrode layer.

Further, when manufacturing a light emitting device, one pixel has a plurality of thin film transistors, and a connecting portion for connecting the gate electrode layer of one thin film transistor and the drain electrode layer of the other is provided.

The manufacturing cost can be reduced by forming the thin film transistor using an oxide semiconductor. In particular, a thin film transistor having stable electrical characteristics can be produced and provided by forming an oxide insulating film in contact with the oxide semiconductor layer by the above method. Therefore, it is possible to provide a light emitting device having a thin film transistor having good electrical characteristics and high reliability.

Since the semiconductor layer in the channel formation region is a high resistance region, the electrical characteristics of the thin film transistor can be stabilized and an increase in off-current can be prevented. Therefore, it is possible to obtain a light emitting device having a thin film transistor having good electrical characteristics and high reliability.

Further, since the thin film transistor is easily destroyed by static electricity or the like, it is preferable to provide a protection circuit on the same substrate as the pixel portion or the drive circuit. The protection circuit is preferably configured by using a non-linear element using an oxide semiconductor layer. For example, the protection circuit is arranged between the pixel unit and the scanning line input terminal and the signal line input terminal. In the present embodiment, a plurality of protection circuits are provided so that a surge voltage is not applied to the scanning line, the signal line, and the capacitive bus line due to static electricity or the like, and the pixel transistor or the like is not destroyed. Therefore, when a surge voltage is applied to the protection circuit, the electric charge is released to the common wiring. Further, the protection circuit is composed of non-linear elements arranged in parallel with the scanning line. Non-linear elements are composed of two-terminal elements such as diodes or three-terminal elements such as transistors. for example,
It can be formed in the same process as the thin film transistor 170 of the pixel portion, and for example, by connecting the gate terminal and the drain terminal, it is possible to have the same characteristics as the diode.

This embodiment can be implemented in combination with the configurations described in other embodiments as appropriate.

(Embodiment 2)
In the present embodiment, FIGS. 6 and 7 show an example in which the oxide conductive layer is provided as a source region and a drain region between the oxide semiconductor layer and the source electrode layer or the drain electrode layer in the first embodiment. .. Therefore, other parts can be performed in the same manner as in the first embodiment, and the description of the same part as that of the first embodiment or the part having the same function and the repetition of the process will be omitted. Further, since FIGS. 6 and 7 are the same as FIGS. 1 to 5 except that the steps are partially different, the same reference numerals are used for the same parts, and detailed description of the same parts will be omitted.

First, according to the first embodiment, the steps up to the step of FIG. 3B in the first embodiment are performed. Figure 6 (
A) is the same as FIG. 3 (B).

The oxide conductive film 140 is formed on the dehydrated or dehydrogenized oxide semiconductor layers 133 and 134, and the metal conductive film made of a metal conductive material is laminated on the oxide conductive film 140.

As a film forming method of the oxide conductive film 140, a sputtering method, a vacuum vapor deposition method (electron beam vapor deposition method, etc.), an arc discharge ion plating method, or a spray method is used. Oxide conductive film 14
As the material of 0, a material containing zinc oxide as a component is preferable, and a material containing indium oxide is preferable. As such an oxide conductive film 140, zinc oxide, zinc aluminum oxide, zinc aluminum oxynitride, gallium zinc oxide and the like can be applied. The film thickness is appropriately selected within the range of 50 nm or more and 300 nm or less. When the sputtering method is used, _{a film is formed using a target containing SiO 2 in an amount} of 2% by weight or more and 10% by weight or less, and the oxide conductive film is impregnated with SiOx (X> 0) that inhibits crystallization. It is preferable to prevent crystallization during the heat treatment for dehydration or dehydrogenation performed in the above step.

Next, a fourth photolithography step is performed to resist masks 136a, 136b, 13
6c, 136d, 136e, 136f, 136g are formed, and unnecessary parts of the metal conductive film are removed by etching to remove the source electrode layer 105a, the drain electrode layer 105b, the source electrode layer 165a, the drain electrode layer 165b, and the capacitance electrode layer 149. , The connection electrode 120, and the second terminal 122 are formed (see FIG. 6B).

When etching the metal conductive film, the oxide conductive film 140 and the oxide semiconductor layer 133,
Each material and etching conditions are appropriately adjusted so that 134 is not removed as well.

Next, the resist masks 136a, 136b, 136c, 136d, 136e, 136f,
136 g was removed, and the source electrode layer 105a, the drain electrode layer 105b, and the source electrode layer 16 were removed.
Using 5a and the drain electrode layer 165b as a mask, the oxide conductive film 140 is etched to form the oxide conductive layers 164a and 164b, the oxide conductive layers 104a and 104b, and the capacitive electrode layer 185 (see FIG. 6C). ). The oxide conductive film 140 containing zinc oxide as a component can be easily etched with an alkaline solution such as a stripping solution of a resist. Further, in the same step, the oxide conductive layers 138 and 139 are also formed on the terminal portion.

Utilizing the difference in etching rate between the oxide semiconductor layer and the oxide conductive layer, an etching process for dividing the oxide conductive layer in order to form a channel region is performed. The oxide conductive layer on the oxide semiconductor layer is selectively etched by utilizing the fact that the etching rate of the oxide conductive layer is faster than that of the oxide semiconductor layer.

Therefore, the resist masks 136a, 136b, 136c, 136d, 136e, 136f
The removal of 136 g is preferably removed by an ashing step. In the case of etching using a stripping solution, the etching conditions (type of etchant, concentration, etching time) are appropriately adjusted so that the oxide conductive film 140 and the oxide semiconductor layers 133 and 134 are not excessively etched.

As in the present embodiment, after the oxide semiconductor layer is etched in an island shape, the oxide conductive film and the metal conductive film are laminated, and the wiring pattern including the source electrode layer and the drain electrode layer is etched with the same mask. Thereby, the oxide conductive film can be left under the wiring pattern of the metal conductive film.

Even in the contact between the gate wiring (conductive layer 162) and the source wiring (drain electrode layer 165b), the oxide conductive layer 164b is formed in the lower layer of the source wiring, so that it becomes a buffer and only the series resistance corresponding to the thickness is used. Yes, it is preferable because it does not form an insulating oxide with metal.

An oxide insulating film 107 is formed as a protective insulating film in contact with the oxide semiconductor layers 133 and 134. In the present embodiment, a silicon oxide film having a film thickness of 300 nm is formed as the oxide insulating film 107 by using a sputtering method.

The second heat treatment (preferably 2) is then performed under an inert gas atmosphere or a nitrogen gas atmosphere.
00 ° C. or higher and 400 ° C. or lower, for example, 250 ° C. or higher and 350 ° C. or lower). For example, a second heat treatment at 250 ° C. for 1 hour is performed in a nitrogen atmosphere. When the second heat treatment is performed, a part of the oxide semiconductor layers 133 and 134 overlapping with the oxide insulating film 107 is heated in a state of being in contact with the oxide insulating film 107.

Through the above steps, the oxide semiconductor layer after film formation is heat-treated for dehydration or dehydrogenation to reduce the resistance, and then a part of the oxide semiconductor layer is selectively selected. It is in a state of excess oxygen.

As a result, in the oxide semiconductor layer 133, the channel forming region 166 overlapping the gate electrode layer 161 becomes type I, and the high resistance source region 167a overlapping the source electrode layer 165a and the oxide conductive layer 164a, the drain electrode layer 165b, and the drain electrode layer 165b. The high resistance drain region 167b overlapping the oxide conductive layer 164b is formed in a self-aligned manner, and the oxide semiconductor layer 163 is formed. Similarly, in the oxide semiconductor layer 134, the channel forming region 116 overlapping the gate electrode layer 101 becomes type I, and the high resistance source region 117a overlapping the source electrode layer 105a and the oxide conductive layer 104a, the drain electrode layer 105b, and the drain electrode layer 105b. The high resistance drain region 117b overlapping the oxide conductive layer 164b is formed in a self-aligned manner, and the oxide semiconductor layer 103 is formed.

The oxide conductive layers 104b and 164b provided between the oxide semiconductor layers 103 and 163 and the drain electrode layer 105b and the drain electrode layer 165b made of a metal material are low resistance drain regions (
It also functions as an LRN (Low Response N-type consistency) region, also referred to as an LRD (Low Response Drain) region). Similarly, the source electrode layer 105a made of the oxide semiconductor layers 103 and 163 and the metal material.
, The oxide conductive layers 104a and 164a provided between the source electrode layers 165a form a low resistance source region (LRN (Low Resistance N-type conducivi).
It also functions as a ty) region and an LRS (Low Response Source) region). By configuring the oxide semiconductor layer, the low resistance drain region, and the drain electrode layer made of a metal material, the withstand voltage of the transistor can be further improved. Specifically, the carrier concentration in the low resistance drain region is larger than that in the high resistance drain region (HRD region), and is preferably in the range of ^{, for example, 1 × 10 20} / cm ³ or more and 1 × 10 ²¹ / cm ^{3 or less.} ..

Through the above steps, the thin film transistor 181 can be produced in the drive circuit section and the thin film transistor 171 can be formed in the pixel section on the same substrate. The thin film transistors 171 and 181 are bottom gate type thin film transistors including an oxide semiconductor layer including a high resistance source region, a high resistance drain region, and a channel forming region. Therefore, the thin film transistors 171 and 18
In No. 1, even if a high electric field is applied, the high resistance drain region or the high resistance source region serves as a buffer and a local high electric field is not applied, so that the withstand voltage of the transistor is improved.

Further, in the capacitance section, the capacitance wiring layer 108, the gate insulating layer 102, and the oxide conductive layer 104b
The capacitance 146 is formed by laminating the capacitance electrode layer 185 and the drain electrode layer 105b formed in the same step as above and the capacitance electrode layer 149 formed in the same step.

Next, the protective insulating layer 106 is formed on the oxide insulating film 107, and the color filter layer 191 is formed on the protective insulating layer 106 in the pixel portion. The overcoat layer 192 is formed so as to cover the color filter layer 191, and the protective insulating layer 109 is formed so as to cover the protective insulating layer 106 and the overcoat layer 192.

Next, a ninth photolithography step is performed in the same manner as in the first embodiment, a resist mask is formed, and a contact that reaches the drain electrode layer 105b by etching the oxide insulating film 107, the protective insulating layer 106, and the protective insulating layer 109. Hole 125 is formed and the resist mask is removed (see FIG. 6 (D)). Further, the contact hole 126 reaching the connection electrode 120 and the contact hole 127 reaching the second terminal 122 are also formed by etching here.

Next, a conductive conductive film having translucency is formed, a tenth photolithography step is performed, a resist mask is formed, and unnecessary portions are removed by etching to remove the unnecessary portions, and the first electrode layer 110, the conductive layer 111, and the like. Terminal electrodes 128 and 129 are formed and the resist mask is removed (see FIG. 7 (A)).

Similarly to the first embodiment, the eleventh photolithography step is performed to form the partition wall 193, and the partition wall 193 is formed.
An EL layer 194 and a second electrode layer 195 are laminated on the first electrode layer 110 to produce a light emitting device of the present embodiment having a light emitting element (see FIG. 7B).

By providing the oxide conductive layer between the oxide semiconductor layer and the source electrode layer and the drain electrode layer as the source region and the drain region, it is possible to reduce the resistance of the source region and the drain region, and the high speed of the transistor can be achieved. Can work. The use of the oxide conductive layer as the source region and the drain region is effective for improving the frequency characteristics of the peripheral circuit (drive circuit). This is because the contact between the metal electrode (Ti or the like) and the oxide conductive layer can reduce the contact resistance as compared with the contact between the metal electrode (Ti or the like) and the oxide semiconductor layer.

Molybdenum (Mo) used as a part of the wiring material in the light emitting device (for example,
Mo / Al / Mo), the contact resistance with the oxide semiconductor layer was high, which was a problem. This is Ti
This is because Mo is less likely to oxidize and therefore has a weaker action of extracting oxygen from the oxide semiconductor layer, and the contact interface between Mo and the oxide semiconductor layer is not n-typed. However, even in such a case, the contact resistance can be reduced by interposing the oxide conductive layer between the oxide semiconductor layer and the source electrode layer and the drain electrode layer, and the frequency characteristics of the peripheral circuit (drive circuit) can be improved. Can be done.

Since the channel length of the thin film transistor is determined at the time of etching the oxide conductive layer, the channel length can be further shortened. For example, shorten the channel length to L0.1 μm or more and 2 μm or less.
The operating speed can be increased.

This embodiment can be implemented in combination with the configurations described in other embodiments as appropriate.

(Embodiment 3)
In the present embodiment, another example in which the oxide conductive layer is provided as a source region and a drain region between the oxide semiconductor layer and the source electrode layer or the drain electrode layer in the first embodiment or the second embodiment. It is shown in FIGS. 8 and 9. Therefore, other parts can be performed in the same manner as in the first or second embodiment, and the description of the same part or the same function as that of the first or second embodiment and the repetition of the process will be omitted. .. Further, since FIGS. 8 and 9 are the same as FIGS. 1 to 7 except that the steps are partially different, the same reference numerals are used for the same parts, and detailed description of the same parts will be omitted.

First, according to the first embodiment, a metal conductive film is formed on the substrate 100, and the metal conductive film is etched by using a resist mask formed by the first photolithography step, and the first terminal 121 and the gate electrode layer 161 are formed. , Conductive layer 162, Gate electrode layer 101, Capacitive wiring layer 108
To form.

Next, the gate insulating layer 102 is formed on the first terminal 121, the gate electrode layer 161, the conductive layer 162, the gate electrode layer 101, and the capacitive wiring layer 108, and the oxide semiconductor film and the oxide conductive film are laminated. The gate insulating layer, the oxide semiconductor film, and the oxide conductive film can be continuously formed without being exposed to the atmosphere.

A resist mask is formed on the oxide conductive film by a second photolithography step. Etching the gate insulating layer, oxide semiconductor film, and oxide conductive film using a resist mask
A contact hole 119 reaching the first terminal 121 and a contact hole 118 reaching the conductive layer 162 are formed.

The resist mask by the second photolithography step is removed, and then the resist mask is formed on the oxide conductive film by the third photolithography step. An island-shaped oxide semiconducting layer and an oxide conductive layer are formed using a resist mask obtained by a third photolithography step.

In this way, if the step of forming a contact hole in the gate insulating layer is performed with the oxide semiconductor film and the oxide conductive film laminated on the entire surface of the gate insulating layer, the resist mask does not come into direct contact with the surface of the gate insulating layer. , Contamination of the gate insulating layer surface (adhesion of impurities, etc.) can be prevented. Therefore, the interface state between the gate insulating layer, the oxide semiconductor film, and the oxide conductive film can be improved, which leads to improvement in reliability.

Next, heat treatment for dehydration and dehydrogenation is performed in a state where the oxide semiconductor layer and the oxide conductive layer are laminated. By heat treatment at a temperature of 700 ° C. from 400 ° C., the dehydration of the oxide semiconductor layer, the dehydrogenation is achieved, it is possible to prevent subsequent re-impregnation of water (H 2 _O).

By this heat treatment, the oxide conductive layer crystallizes unless the oxide conductive layer contains a crystallization inhibitor such as silicon oxide. The crystals of the oxide conductive layer grow in columns with respect to the underlying surface. As a result, when the metal conductive film on the upper layer of the oxide conductive layer is etched in order to form the source electrode layer and the drain electrode layer, it is possible to prevent the formation of an undercut.

Further, the conductivity of the oxide conductive layer can be improved by the heat treatment of dehydration and dehydrogenation of the oxide semiconductor layer. Only the oxide conductive layer may be heat-treated at a lower temperature than the heat treatment of the oxide semiconductor layer.

Further, the first heat treatment of the oxide semiconductor layer and the oxide conductive layer can also be performed on the oxide semiconductor film and the oxide conductive film before being processed into the island-shaped oxide semiconductor layer and the oxide conductive layer. .. In that case, after the first heat treatment, the substrate is taken out from the heating device and a photolithography step is performed.

By the above steps, the oxide semiconductor layers 133 and 134 and the oxide conductive layers 142 and 143 are obtained (see FIG. 8A). The oxide semiconductor layer 133 and the oxide conductive layer 142, and the oxide semiconductor layer 134 and the oxide conductive layer 143 are island-shaped laminates formed by using the same mask.

Next, a fourth photolithography step is performed to resist masks 136a, 136b, 13
6c, 136d, 136e, 136f, 136g are formed, and unnecessary parts of the metal conductive film are removed by etching to remove the source electrode layer 105a, the drain electrode layer 105b, the source electrode layer 165a, the drain electrode layer 165b, and the capacitance electrode layer 149. , The connection electrode 120, and the second terminal 122 are formed (see FIG. 8B).

The materials and etching conditions are appropriately adjusted so that the oxide conductive layers 142 and 143 and the oxide semiconductor layers 133 and 134 are not removed during the etching of the metal conductive film.

Next, the resist masks 136a, 136b, 136c, 136d, 136e, 136f,
136 g was removed, and the source electrode layer 105a, the drain electrode layer 105b, and the source electrode layer 16 were removed.
Using 5a and the drain electrode layer 165b as a mask, the oxide conductive layers 142 and 143 are etched to form the oxide conductive layers 164a and 164b and the oxide conductive layers 104a and 104b (.
See FIG. 8 (C). ). The oxide conductive layers 142 and 143 containing zinc oxide as a component can be easily etched with an alkaline solution such as a stripping solution of a resist.

Therefore, the resist masks 136a, 136b, 136c, 136d, 136e, 136f
The removal of 136 g is preferably removed by an ashing step. In the case of etching using a stripping solution, the etching conditions (type of etchant, concentration, etching time) are appropriately adjusted so that the oxide conductive layers 142 and 143 and the oxide semiconductor layers 133 and 134 are not excessively etched.

An oxide insulating film 107 is formed as a protective insulating film in contact with the oxide semiconductor layers 133 and 134. In the present embodiment, a silicon oxide film having a film thickness of 300 nm is formed as the oxide insulating film 107 by using a sputtering method.

The second heat treatment (preferably 2) is then performed under an inert gas atmosphere or a nitrogen gas atmosphere.
00 ° C. or higher and 400 ° C. or lower, for example, 250 ° C. or higher and 350 ° C. or lower). For example, a second heat treatment at 250 ° C. for 1 hour is performed in a nitrogen atmosphere. When the second heat treatment is performed, a part of the oxide semiconductor layers 133 and 134 overlapping with the oxide insulating film 107 is heated in a state of being in contact with the oxide insulating film 107.

Through the above steps, the oxide semiconductor layer after film formation is heat-treated for dehydration or dehydrogenation to reduce the resistance, and then a part of the oxide semiconductor layer is selectively selected. It is in a state of excess oxygen.

As a result, in the oxide semiconductor layer 133, the channel forming region 166 overlapping the gate electrode layer 161 becomes type I, and the high resistance source region 167a overlapping the source electrode layer 165a and the oxide conductive layer 164a, the drain electrode layer 165b, and the drain electrode layer 165b. The high resistance drain region 167b overlapping the oxide conductive layer 164b is formed in a self-aligned manner, and the oxide semiconductor layer 163 is formed. Similarly, in the oxide semiconductor layer 134, the channel forming region 116 overlapping the gate electrode layer 101 becomes type I, and the high resistance source region 117a overlapping the source electrode layer 105a and the oxide conductive layer 104a, the drain electrode layer 105b, and the drain electrode layer 105b. The high resistance drain region 117b overlapping the oxide conductive layer 164b is formed in a self-aligned manner, and the oxide semiconductor layer 103 is formed.

The oxide conductive layers 104b and 164b provided between the oxide semiconductor layers 103 and 163 and the drain electrode layer 105b and the drain electrode layer 165b made of a metal material are low resistance drain regions (
It also functions as an LRN region and an LRD region). Similarly, the oxide semiconductor layer 103,
The oxide conductive layers 104a and 164a provided between the source electrode layer 105a made of 163 and the metal material and the source electrode layer 165a also function as low resistance source regions (also referred to as LRN regions and LRS regions). By configuring the oxide semiconductor layer, the low resistance drain region, and the drain electrode layer made of a metal material, the withstand voltage of the transistor can be further improved. Specifically, the carrier concentration in the low resistance drain region is larger than that in the high resistance drain region (HRD region), and is preferably in the range of ^{, for example, 1 × 10 20} / cm ³ or more and 1 × 10 ²¹ / cm ^{3 or less.} ..

Through the above steps, the thin film transistor 182 can be produced in the drive circuit portion and the thin film transistor 172 can be produced in the pixel portion on the same substrate. The thin film transistors 172 and 182 are bottom gate type thin film transistors including an oxide semiconductor layer including a high resistance source region, a high resistance drain region, and a channel forming region. Therefore, the thin film transistors 172 and 18
In No. 2, even if a high electric field is applied, the high resistance drain region or the high resistance source region serves as a buffer and a local high electric field is not applied, so that the withstand voltage of the transistor is improved.

Further, in the capacitance section, the capacitance wiring layer 108, the gate insulating layer 102, and the drain electrode layer 105
A capacitance 146 formed by laminating the capacitance electrode layer 149 formed in the same step as b is formed.

Next, the protective insulating layer 106 is formed on the oxide insulating film 107, and the color filter layer 191 is formed on the protective insulating layer 106 in the pixel portion. The overcoat layer 192 is formed so as to cover the color filter layer 191, and the protective insulating layer 109 is formed so as to cover the protective insulating layer 106 and the overcoat layer 192.

Next, a ninth photolithography step is performed in the same manner as in the first embodiment, a resist mask is formed, and a contact that reaches the drain electrode layer 105b by etching the oxide insulating film 107, the protective insulating layer 106, and the protective insulating layer 109. Hole 125 is formed and the resist mask is removed (see FIG. 8 (D)). Further, the contact hole 127 reaching the second terminal 122 and the contact hole 126 reaching the connection electrode 120 are also formed by etching here.

Next, a conductive conductive film having translucency is formed, a tenth photolithography step is performed, a resist mask is formed, and unnecessary portions are removed by etching to remove the unnecessary portions, and the first electrode layer 110, the conductive layer 111, and the like. Terminal electrodes 128 and 129 are formed and the resist mask is removed (see FIG. 9A).

Similarly to the first embodiment, the eleventh photolithography step is performed to form the partition wall 193, and the partition wall 193 is formed.
An EL layer 194 and a second electrode layer 195 are laminated on the first electrode layer 110 to produce a light emitting device of the present embodiment having a light emitting element (see FIG. 9B).

By providing the oxide conductive layer between the oxide semiconductor layer and the source electrode layer and the drain electrode layer as the source region and the drain region, it is possible to reduce the resistance of the source region and the drain region, and the high speed of the transistor can be achieved. Can work. The use of the oxide conductive layer as the source region and the drain region is effective for improving the frequency characteristics of the peripheral circuit (drive circuit). This is because the contact between the metal electrode (Ti or the like) and the oxide conductive layer can reduce the contact resistance as compared with the contact between the metal electrode (Ti or the like) and the oxide semiconductor layer.

By interposing the oxide conductive layer between the oxide semiconductor layer and the source electrode layer and the drain electrode layer, the contact resistance can be reduced and the frequency characteristics of the peripheral circuit (drive circuit) can be improved.

Since the channel length of the thin film transistor is determined at the time of etching the oxide conductive layer, the channel length can be further shortened. For example, the operating speed can be increased by shortening the channel length L to 0.1 μm or more and 2 μm or less.

This embodiment can be implemented in combination with the configurations described in other embodiments as appropriate.

(Embodiment 4)
In the present embodiment, examples of a light emitting device that electrically connects the thin film transistor of the pixel portion and the first electrode layer of the light emitting element via the connecting electrode layer are shown in FIGS. 16 to 18. In the present embodiment, the same materials and methods can be used except that the method of connecting the transistor of the pixel portion and the first electrode layer of the light emitting element is different. Therefore, other parts can be performed in the same manner as in the first embodiment, and the description of the same part as that of the first embodiment or the part having the same function and the repetition of the process will be omitted. Further, since FIGS. 16 to 18 are the same as those of FIGS. 1 to 5 except that the steps are partially different, the same reference numerals are used for the same parts, and detailed description of the same parts will be omitted.

The light emitting device of this embodiment is shown in FIG. The drain electrode layer 105b of the thin film transistor 170 of the pixel portion is electrically connected to the first electrode layer 110 with the connection electrode layer 196 in between. A method of manufacturing the light emitting device shown in FIG. 16 will be described with reference to FIGS. 17 and 18.

First, according to the first embodiment, the steps up to the step of FIG. 4 (A) in the first embodiment are performed. FIG. 17
(A) is the same as FIG. 4 (A).

Next, a fifth photolithography step is performed to form a resist mask, and the oxide insulating film 1 is formed.
By etching 07 and the protective insulating layer 106, a contact hole 125 reaching the drain electrode layer 105b, a contact hole 127 reaching the second terminal 122, and a contact hole 126 reaching the connection electrode 120 are formed, and the resist mask is removed (FIG. 17). See (B).).

Next, a conductive film is formed, a sixth photolithography step is performed, a resist mask is formed, and unnecessary portions are removed by etching to remove the connection electrode layer 196, the conductive layer 112, and the terminal electrode 1.
13 and 114 are formed and the resist mask is removed (see FIG. 17 (C)). Since a metal conductive film can be used as the conductive film, the connection electrode layer 196, the conductive layer 112, and the terminal electrodes 113, 114 can also be metal conductive layers.

As the connection electrode layer 196, a film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W as a main component, or a laminated film in which an alloy film thereof is combined can be used. Therefore, when the conductive layer 112 and the terminal electrodes 113 and 114 are formed in the same process as the connection electrode layer 196 as in the present embodiment, the conductive layer 112 and the terminal electrodes 113 and 114 are also formed of Al, Cr and Cu.
A film containing an element selected from Ta, Ti, Mo, and W as a main component, or a laminated film in which an alloy film thereof is combined can be used. The conductive film is not limited to a single layer containing the above-mentioned elements, and a laminate of two or more layers can be used. The film forming method of the conductive film includes a sputtering method, a vacuum vapor deposition method (electron beam vapor deposition method, etc.), an arc discharge ion plating method, and the like.
The spray method can be used.

Next, in the pixel portion, the seventh to ninth photolithography steps are performed on the protective insulating layer 106 to form the RGB color filter layer 191, and the tenth photolithography step is performed.
The overcoat layer 192 is formed so as to cover the color filter layer 191. Connection electrode layer 1
96, the conductive layer 112, the terminal electrodes 113 and 114, the protective insulating layer 106 and the overcoat layer 192 are covered to form the protective insulating layer 109 (see FIG. 17 (D)).

Next, the eleventh photolithography step is performed to form a resist mask, and the protective insulating layer 1 is formed.
The contact hole 125 that reaches the connection electrode layer 196 is formed by etching 09, and the resist mask is removed. Further, the protective insulating layer 109 on the terminal electrodes 113 and 114 is also removed by etching here to expose the terminal electrodes 113 and 114 (see FIG. 18A).
).

Next, a light-transmitting conductive film is formed, a twelfth photolithography step is performed, a resist mask is formed, unnecessary portions are removed by etching to form a first electrode layer 110, and a resist is formed. Remove the mask.

Similar to the first embodiment, the thirteenth photolithography step is performed to form the partition wall 193, and the partition wall 193 is formed.
An EL layer 194 and a second electrode layer 195 are laminated on the first electrode layer 110 to produce a light emitting device of the present embodiment having a light emitting element (see FIG. 18B).

When the connection electrode layer 196 is formed, the power supply line can be formed by the same material and the same process as the connection electrode layer 196. Further, the common potential line can also be formed by the same material and the same process as the connection electrode layer 196.

This embodiment can be implemented in combination with the configurations described in the other embodiments as appropriate.

(Embodiment 5)
In the present embodiment, an example in which a part of the manufacturing process of the thin film transistor is different from that of the first embodiment is shown in FIG.
Shown at 0. Since FIG. 10 is the same as FIGS. 1 to 5 except that the steps are partially different, the same reference numerals are used for the same parts, and detailed description of the same parts will be omitted.

First, according to the first embodiment, a gate electrode layer and a gate insulating layer are formed on the substrate, and a contact hole reaching the gate electrode layer is formed in the pixel portion by using a second photolithography step (not shown).

Next, the oxide semiconductor film 130 is formed, and the oxide semiconductor film 130 is processed into island-shaped oxide semiconductor layers 131 and 132 by a third photolithography step.

Next, the oxide semiconductor layers 131 and 132 are dehydrated or dehydrogenated. The temperature of the first heat treatment for dehydration or dehydrogenation is 400 ° C. or higher and 750 ° C. or lower, preferably 425 ° C.
The temperature is 750 ° C or lower. If the temperature is 425 ° C. or higher, the heat treatment time may be 1 hour or less, but if the temperature is lower than 425 ° C., the heat treatment time is longer than 1 hour. Here, after introducing the substrate into an electric furnace, which is one of the heat treatment devices, and heat-treating the oxide semiconductor layer in a nitrogen atmosphere, water is applied to the oxide semiconductor layer without touching the atmosphere. Prevents remixing of hydrogen and hydrogen, and obtains an oxide semiconductor layer. Thereafter, a high-purity oxygen gas, a high-purity N _{2 O} gas, or ultra-dry air (having a dew point of -40 ℃ or less, preferably -60 ° C. or less) into the same furnace. In the oxygen gas or the N _{2 O} gas, water, it is preferred that the hydrogen, and the like be not contained. The purity of the oxygen gas or the _{N 2} O gas is introduced into the heat treatment apparatus, 6N (99.9
999%) or higher, preferably 7N (99.99999%) or higher (ie, oxygen gas or N)
₂ The impurity concentration in the O gas is preferably 1 ppm or less, preferably 0.1 ppm or less).

The heat treatment device is not limited to the electric furnace, and for example, GRTA (Gas Rapid Th).
ermal Anneal) device, LRTA (Lamp Rapid Thermal)
An RTA (Rapid Thermal Anneal) device such as an Anneal) device can be used. The LRTA device is a device that heats an object to be processed by radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high pressure sodium lamps, and high pressure mercury lamps. Also, LR
In addition to the TA device and the lamp, a device for heating the object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element may be provided. GRTA is a method of performing heat treatment using a high-temperature gas. As the gas, a rare gas such as argon or an inert gas such as nitrogen that does not react with the object to be treated by heat treatment is used. 600 ° C using the RTA method
Heat treatment may be performed at ~ 750 ° C. for several minutes.

The first post-heat treatment to 200 ° C. or higher 400 ° C. or less for dehydration or dehydrogenation, preferably by heat treatment in an oxygen gas or the N _{2 O} gas atmosphere at 200 ° C. or higher 300 ° C. temperature below May be good.

Further, the first heat treatment of the oxide semiconductor layers 131 and 132 can also be performed on the oxide semiconductor film 130 before being processed into the island-shaped oxide semiconductor layer. In that case, after the first heat treatment, the substrate is taken out from the heating device and a photolithography step is performed.

By going through the above steps, the entire oxide semiconductor film is brought into a state of excess oxygen, so that the resistance is increased, that is, the type I is formed. Therefore, the oxide semiconductor layers 168 and 198, which are entirely I-shaped, are obtained.

Next, a resist mask is formed on the oxide semiconductor layers 168 and 198 by a fourth photolithography step, and selective etching is performed to form a source electrode layer and a drain electrode layer, and an oxide insulating film is formed by a sputtering method. Form 107.

Next, in order to reduce variations in the electrical characteristics of the thin film transistor, heat treatment (preferably 150 ° C. or higher and lower than 350 ° C.) may be performed in an inert gas atmosphere or a nitrogen gas atmosphere. For example, heat treatment is performed at 250 ° C. for 1 hour in a nitrogen atmosphere.

Next, the protective insulating layer 106 is formed on the oxide insulating film 107, and the color filter layer 191 is formed on the protective insulating layer 106 in the pixel portion. The overcoat layer 192 is formed so as to cover the color filter layer 191, and the protective insulating layer 109 is formed so as to cover the protective insulating layer 106 and the overcoat layer 192.

Next, a ninth photolithography step is performed to form a resist mask, and the gate insulating layer 1 is formed.
02, the oxide insulating film 107, the protective insulating layer 106, and the protective insulating layer 109 are etched to form a contact hole reaching the first terminal 121, the conductive layer 162, the drain electrode layer 105b, and the second terminal 122. After forming a light-transmitting conductive film, a resist mask is formed by a tenth photolithography step and selectively etched to obtain a first electrode layer 110, a terminal electrode 128, a terminal electrode 129, and a wiring layer 145. To form.

In this embodiment, the connection between the first terminal 121 and the terminal electrode 128 is directly performed without going through the connection electrode 120. Further, the drain electrode layer 165b and the conductive layer 162 are connected to each other via the wiring layer 145.

Further, in the capacitance section, a capacitance 147 formed by laminating the capacitance wiring layer 108, the gate insulating layer 102, the source electrode layer and the drain electrode layer with the capacitance electrode layer 149 formed in the same process is formed.

Through the above steps, the thin film transistor 183 can be manufactured in the drive circuit section and the thin film transistor 173 can be manufactured in the pixel section on the same substrate.

Similar to the first embodiment, the partition wall 193 is formed, and the EL layer 194 and the second electrode layer 195 are laminated on the first electrode layer 110 to produce the light emitting device of the present embodiment having a light emitting element. (Fig. 1
See 0. ).

This embodiment can be implemented in combination with the configurations described in the other embodiments as appropriate.

(Embodiment 6)
In the present embodiment, in the light emitting device shown in the first to fifth embodiments, an example of manufacturing an active matrix type light emitting display device by using a thin film transistor and a light emitting element using electroluminescence will be shown.

A light emitting device that utilizes electroluminescence is distinguished by whether the light emitting material is an organic compound or an inorganic compound, and the former is generally called an organic EL element and the latter is called an inorganic EL element.

In the organic EL element, by applying a voltage to the light emitting element, electrons and holes are injected into the layer containing the luminescent organic compound from the pair of electrodes, respectively, and a current flows. Then, when those carriers (electrons and holes) are recombined, the luminescent organic compound forms an excited state, and when the excited state returns to the ground state, it emits light. From such a mechanism, such a light emitting element is called a current excitation type light emitting element.

The inorganic EL element is classified into a dispersed inorganic EL element and a thin film type inorganic EL element according to the element configuration. The dispersed inorganic EL element has a light emitting layer in which particles of a light emitting material are dispersed in a binder, and the light emitting mechanism is donor-acceptor recombination type light emission utilizing a donor level and an acceptor level. In the thin film type inorganic EL element, the light emitting layer is sandwiched between the dielectric layers, and the light emitting layer is sandwiched between the dielectric layers.
Furthermore, it has a structure in which it is sandwiched between electrodes, and the light emission mechanism is localized light emission that utilizes the inner-shell electron transition of metal ions. Here, an organic EL element will be used as the light emitting element.

FIG. 19 is a diagram showing an example of a pixel configuration to which digital time gradation drive can be applied as an example of a light emitting device.

The configuration of pixels to which digital time gradation drive can be applied and the operation of pixels will be described. Here, an example is shown in which two n-channel type transistors using an oxide semiconductor layer in the channel forming region are used in one pixel.

Pixel 6400 is a switching transistor 6401, a driving transistor 6402,
It has a light emitting element 6404 and a capacitive element 6403. Switching transistor 64
In 01, the gate is connected to the scanning line 6406, the first electrode (one of the source electrode and the drain electrode) is connected to the signal line 6405, and the second electrode (the other of the source electrode and the drain electrode) is the gate of the driving transistor 6402. It is connected to the. The drive transistor 6402 is
The gate is connected to the power supply line 6407 via the capacitive element 6403, and the first electrode is the power supply line 640.
The second electrode is connected to the first electrode (pixel electrode) of the light emitting element 6404.
The second electrode of the light emitting element 6404 corresponds to the common electrode 6408. The common electrode 6408 is electrically connected to a common potential line formed on the same substrate.

A low power supply potential is set in the second electrode (common electrode 6408) of the light emitting element 6404. The low power supply potential is a potential in which the high power supply potential is higher than the low power supply potential with reference to the high power supply potential set in the power supply line 6407, and for example, GND, 0V or the like is set as the low power supply potential. You may. Since the potential difference between the high power supply potential and the low power supply potential is applied to the light emitting element 6404 and a current is passed through the light emitting element 6404 to cause the light emitting element 6404 to emit light, the potential difference between the high power supply potential and the low power supply potential is the light emitting element 6404. Set each potential so that it is equal to or higher than the forward threshold voltage of.

The capacitive element 6403 can be omitted by substituting the gate capacitance of the driving transistor 6402. Regarding the gate capacitance of the drive transistor 6402, a capacitance may be formed between the channel region and the gate electrode.

Here, in the case of the voltage input voltage drive system, the gate of the drive transistor 6402 is
A video signal is input so that the drive transistor 6402 is fully turned on or off. That is, the driving transistor 6402 is operated in the linear region.
Since the drive transistor 6402 operates in the linear region, a voltage higher than the voltage of the power supply line 6407 is applied to the gate of the drive transistor 6402. In addition, in the signal line 6405,
Apply a voltage higher than (power supply line voltage + Vth of drive transistor 6402).

Further, when analog gradation drive is performed instead of digital time gradation drive, the same pixel configuration as in FIG. 19 can be used by different signal inputs.

When performing analog gradation drive, the light emitting element 6404 is connected to the gate of the drive transistor 6402.
The forward voltage of + the voltage of Vth or more of the driving transistor 6402 is applied. Light emitting element 64
The forward voltage of 04 refers to a voltage at which a desired brightness is obtained, and includes at least a forward threshold voltage. By inputting a video signal such that the driving transistor 6402 operates in the saturation region, a current can be passed through the light emitting element 6404. In order to operate the drive transistor 6402 in the saturation region, the potential of the power supply line 6407 is made higher than the gate potential of the drive transistor 6402. By making the video signal analog, a current corresponding to the video signal can be passed through the light emitting element 6404 to drive the analog gradation.

The pixel configuration shown in FIG. 19 is not limited to this. For example, a switch, a resistance element, a capacitance element, a transistor, a logic circuit, or the like may be newly added to the pixel shown in FIG.

Next, the configuration of the light emitting element will be described with reference to FIG. Here, the driving TFT is n
The cross-sectional structure of the pixel will be described by taking the case of a mold as an example. The driving TFTs 7001, 7011, and 7021 used in the light emitting device of FIGS. 20 (A), (B), and (C) can be manufactured in the same manner as the thin film transistors shown in the first to fifth embodiments, and include an oxide semiconductor layer. It is a highly reliable thin film transistor.

The light emitting element may have at least one of the anode and the cathode transparent in order to extract light emission. Then, a thin film transistor and a light emitting element are formed on the substrate, and an upper surface injection structure that extracts light emission from the surface opposite to the substrate, a lower surface injection structure that extracts light emission from the surface on the substrate side, and a substrate side and a side opposite to the substrate. There is a light emitting element having a double-sided injection structure that extracts light emission from the surface of the above, and the pixel configuration can be applied to a light emitting element having any injection structure.

A light emitting element having a bottom injection structure will be described with reference to FIG. 20 (A).

The driving TFT 7011 is n-type, and the light emitted from the light emitting element 7012 is the first electrode layer 70.
The cross-sectional view of the pixel at the time of ejecting to 13 side is shown. In FIG. 20 (A), the driving TFT 701
The first electrode layer 7013 of the light emitting element 7012 is formed on the translucent conductive film 7017 electrically connected to No. 1, and the EL layer 7014 and the second are on the first electrode layer 7013. The electrode layers 7015 are laminated in order. The conductive film 7017 is electrically connected to the drain electrode layer of the driving TFT 7011 via the contact holes formed in the protective insulating layer 7035, the protective insulating layer 7032, and the oxide insulating layer 7031.

Examples of the translucent conductive film 7017 include indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, and indium tin oxide. A translucent conductive film such as indium zinc oxide or indium tin oxide to which silicon oxide is added can be used.

Further, various materials can be used for the first electrode layer 7013 of the light emitting element. For example, when the first electrode layer 7013 is used as a cathode, a material having a small work function, specifically,
For example, alkali metals such as Li and Cs, and alkaline earth metals such as Mg, Ca and Sr,
In addition to alloys containing these (Mg: Ag, Al: Li, etc.), rare earth metals such as Yb and Er are preferable. In FIG. 20A, the film thickness of the first electrode layer 7013 is such that light is transmitted (preferably about 5 nm to 30 nm). For example, an aluminum film having a film thickness of 20 nm is used as the first electrode layer 7013.

After laminating and forming a translucent conductive film and an aluminum film, the conductive film 7017 having translucency and the first electrode layer 7013 may be selectively etched to form the first electrode layer 7013.
It is preferable because it can be etched using the same mask.

The peripheral edge of the first electrode layer 7013 is covered with a partition wall 7019. The partition wall 7019 is formed by using an organic resin film such as polyimide, acrylic, polyamide, or epoxy, an inorganic insulating film, or an organic polysiloxane. The partition wall 7019 is formed by using a particularly photosensitive resin material and forming an opening on the first electrode layer 7013 so that the side wall of the opening becomes an inclined surface formed with a continuous curvature. Is preferable. When a photosensitive resin material is used as the partition wall 7019, the step of forming the resist mask can be omitted.

Further, the EL layer 7014 formed on the first electrode layer 7013 and the partition wall 7019 may include at least a light emitting layer, and even if it is composed of a single layer, it is configured so that a plurality of layers are laminated. Either way is fine. When the EL layer 7014 is composed of a plurality of layers, the electron injection layer, the electron transport layer, the light emitting layer, the hole transport layer, and the hole injection layer are laminated in this order on the first electrode layer 7013 that functions as a cathode. It is not necessary to provide all of these layers.

Further, the stacking order is not limited, and the first electrode layer 7013 functions as an anode, and the hole injection layer, the hole transport layer, the light emitting layer, the electron transport layer, and the electron injection layer are laminated in this order on the first electrode layer 7013. You may. However, when comparing the power consumption, the first electrode layer 7013 functions as a cathode, and the electron injection layer, the electron transport layer, the light emitting layer, and the hole transport layer are placed on the first electrode layer 7013.
It is preferable to stack the hole injection layers in this order because the voltage rise of the drive circuit unit can be suppressed and the power consumption can be reduced.

Further, various materials can be used as the second electrode layer 7015 formed on the EL layer 7014. For example, when the second electrode layer 7015 is used as an anode, a material having a large work function, for example, a transparent conductive material such as ZrN, Ti, W, Ni, Pt, Cr or the like, ITO, IZO, ZnO or the like is preferable. Further, a shielding film 7016, for example, a metal that blocks light, a metal that reflects light, or the like is used on the second electrode layer 7015. In the present embodiment, the second electrode layer 7
An ITO film is used as 015, and a Ti film is used as the shielding film 7016.

In the first electrode layer 7013 and the second electrode layer 7015, the region sandwiching the EL layer 7014 including the light emitting layer corresponds to the light emitting element 7012. In the case of the element structure shown in FIG. 20 (A), the light emitted from the light emitting element 7012 is emitted to the first electrode layer 7013 side as shown by an arrow.
It passes through the color filter layer 7033 and is ejected to the outside.

The color filter layer 7033 is formed by a droplet ejection method such as an inkjet method, a printing method, an etching method using a photolithography technique, or the like.

Further, the color filter layer 7033 is covered with the overcoat layer 7034, and further covered with the protective insulating layer 7035. Although the overcoat layer 7034 is shown with a thin film thickness in FIG. 20A, the overcoat layer 7034 has a function of flattening the unevenness caused by the color filter layer 7033.

Next, a light emitting element having a double-sided injection structure will be described with reference to FIG. 20 (B).

In FIG. 20B, a translucent conductive film 7 electrically connected to the driving TFT 7021.
The first electrode layer 7023 of the light emitting element 7022 is formed on 027, and the EL layer 7024 and the second electrode layer 7025 are laminated on the first electrode layer 7023 in this order. The conductive film 7027 is electrically connected to the drain electrode layer of the driving TFT 7021 via contact holes formed in the protective insulating layer 7045, the protective insulating layer 7042, and the oxide insulating layer 7041.

Examples of the translucent conductive film 7027 include indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, and indium tin oxide. A translucent conductive film such as indium zinc oxide or indium tin oxide to which silicon oxide is added can be used.

Further, various materials can be used for the first electrode layer 7023. For example, when the first electrode layer 7023 is used as a cathode, a material having a small work function, specifically, an alkali metal such as Li or Cs, an alkaline earth metal such as Mg, Ca, Sr, and these. In addition to alloys containing (Mg: Ag, Al: Li, etc.), rare earth metals such as Yb and Er are preferable. In the present embodiment, the first electrode layer 7023 is used as a cathode, and the film thickness thereof is such that light is transmitted (preferably about 5 nm to 30 nm). For example, an aluminum film having a film thickness of 20 nm is used as a cathode.

After laminating and forming a translucent conductive film and an aluminum film, the conductive film 7027 having translucency and the first electrode layer 7023 may be selectively etched to form the first electrode layer 7023.
Etching can be performed using the same mask, which is preferable.

The peripheral edge of the first electrode layer 7023 is covered with a partition wall 7029. The partition wall 7029 is formed by using an organic resin film such as polyimide, acrylic, polyamide, or epoxy, an inorganic insulating film, or an organic polysiloxane. The partition wall 7029 is formed by using a particularly photosensitive resin material and forming an opening on the first electrode layer 7023 so that the side wall of the opening becomes an inclined surface formed with a continuous curvature. Is preferable. When a photosensitive resin material is used as the partition wall 7029, the step of forming the resist mask can be omitted.

Further, the EL layer 7024 formed on the first electrode layer 7023 and the partition wall 7029 may include a light emitting layer, and even if it is composed of a single layer, it is configured so that a plurality of layers are laminated. Either is fine. When the EL layer 7024 is composed of a plurality of layers, the electron injection layer, the electron transport layer, the light emitting layer, the hole transport layer, and the hole injection layer are laminated in this order on the first electrode layer 7023 that functions as a cathode. It is not necessary to provide all of these layers.

Further, the stacking order is not limited, and the first electrode layer 7023 may be used as an anode, and the hole injection layer, the hole transport layer, the light emitting layer, the electron transport layer, and the electron injection layer may be laminated in this order on the anode. However, when comparing the power consumption, it is better to use the first electrode layer 7023 as a cathode and to stack the electron injection layer, the electron transport layer, the light emitting layer, the hole transport layer, and the hole injection layer in this order on the cathode. Therefore, it is preferable.

Further, various materials can be used as the second electrode layer 7025 formed on the EL layer 7024. For example, when the second electrode layer 7025 is used as an anode, a material having a large work function, for example, a transparent conductive material such as ITO, IZO, or ZnO can be preferably used. In the present embodiment, the second electrode layer 7025 is used as an anode, and I containing silicon oxide.
Form a TO film.

In the first electrode layer 7023 and the second electrode layer 7025, the region sandwiching the EL layer 7024 including the light emitting layer corresponds to the light emitting element 7022. In the case of the element structure shown in FIG. 20B, the light emitted from the light emitting element 7022 is emitted to both the second electrode layer 7025 side and the first electrode layer 7023 side as shown by arrows.

The color filter layer 7043 is formed by a droplet ejection method such as an inkjet method, a printing method, an etching method using a photolithography technique, or the like.

Further, the color filter layer 7043 is covered with the overcoat layer 7044, and further covered with the protective insulating layer 7045.

However, when using a light emitting element with a double-sided injection structure and displaying both display surfaces in full color,
Since the light from the second electrode layer 7025 side does not pass through the color filter layer 7043, it is preferable to provide a sealing substrate separately provided with the color filter layer above the second electrode layer 7025.

Next, a light emitting element having a top injection structure will be described with reference to FIG. 20 (C).

FIG. 20C shows a cross-sectional view of pixels when the driving TFT 7001 is n-type and the light emitted from the light emitting element 7002 escapes to the second electrode layer 7005 side. FIG. 20 (C
), The first electrode layer 7003 of the light emitting element 7002 electrically connected to the TFT 7001.
Is formed, and the EL layer 7004 and the second electrode layer 7005 are laminated in this order on the first electrode layer 7003.

Further, various materials can be used for the first electrode layer 7003. For example, when the first electrode layer 7003 is used as a cathode, a material having a small work function, specifically, an alkali metal such as Li or Cs, an alkaline earth metal such as Mg, Ca, Sr, and these. In addition to alloys containing (Mg: Ag, Al: Li, etc.), rare earth metals such as Yb and Er are preferable.

The peripheral edge of the first electrode layer 7003 is covered with a partition wall 7009. The partition wall 7009 is formed by using an organic resin film such as polyimide, acrylic, polyamide, or epoxy, an inorganic insulating film, or an organic polysiloxane. The partition wall 7009 is formed by using a particularly photosensitive resin material and forming an opening on the first electrode layer 7003 so that the side wall of the opening becomes an inclined surface formed with a continuous curvature. Is preferable. When a photosensitive resin material is used as the partition wall 7009, the step of forming the resist mask can be omitted.

Further, the EL layer 7004 formed on the first electrode layer 7003 and the partition wall 7009 may include at least a light emitting layer, and even if it is composed of a single layer, it is configured so that a plurality of layers are laminated. Either way is fine. When the EL layer 7004 is composed of a plurality of layers, an electron injection layer, an electron transport layer, a light emitting layer, and a hole transport layer are placed on the first electrode layer 7003 used as a cathode.
Laminate in the order of hole injection layer. It is not necessary to provide all of these layers.

Further, the stacking order is not limited, and the hole injection layer, the hole transport layer, the light emitting layer, the electron transport layer, and the electron injection layer may be laminated in this order on the first electrode layer 7003 used as the anode.

In FIG. 20C, a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer are laminated in this order on a laminated film in which a Ti film, an aluminum film, and a Ti film are laminated in this order, and Mg is placed on the hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer. : A
A laminate of a g-alloy thin film and an ITO film is formed.

However, when the TFT 7001 is n-type, it is better to stack the electron injection layer, the electron transport layer, the light emitting layer, the hole transport layer, and the hole injection layer on the first electrode layer 7003 in this order to suppress the voltage rise in the drive circuit. It is preferable because it can reduce power consumption.

The second electrode layer 7005 is formed by using a light-transmitting conductive material, for example, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, and indium oxide containing titanium oxide. , Indium tin oxide containing titanium oxide, indium tin oxide, indium zinc oxide, indium tin oxide added with silicon oxide, or the like may be used.

The region sandwiching the EL layer 7004 including the light emitting layer between the first electrode layer 7003 and the second electrode layer 7005 corresponds to the light emitting element 7002. In the case of the pixel shown in FIG. 20 (C), the light emitting element 7
The light emitted from 002 is emitted to the second electrode layer 7005 side as shown by an arrow.

Further, in FIG. 20C, the drain electrode layer of the TFT 7001 is an oxide insulating layer 705.
1. It is electrically connected to the first electrode layer 7003 through the contact holes formed in the protective insulating layer 7052 and the protective insulating layer 7055. As the flattening insulating layer 7053, a resin material such as polyimide, acrylic, benzocyclobutene, polyamide, or epoxy can be used.
In addition to the above resin materials, low dielectric constant materials (low-k materials), siloxane-based resins, and PSG
(Phosphorus glass), BPSG (Phosphoron glass) and the like can be used. The flattening insulating layer 7053 may be formed by laminating a plurality of insulating films formed of these materials. The method for forming the flattening insulating layer 7053 is not particularly limited, and depending on the material, a sputtering method, an SOG method, a spin coat, a dip, a spray coating, a droplet ejection method (inkjet method, screen printing, offset printing, etc.) , Doctor knife, roll coater, curtain coater, knife coater and the like can be used.

Further, the partition wall 7 is used to insulate the first electrode layer 7003 and the first electrode layer of adjacent pixels.
009 is provided. The partition wall 7009 is formed by using an organic resin film such as polyimide, acrylic, polyamide, or epoxy, an inorganic insulating film, or an organic polysiloxane. The partition wall 7009 is formed by using a particularly photosensitive resin material and forming an opening on the first electrode layer 7003 so that the side wall of the opening becomes an inclined surface formed with a continuous curvature. Is preferable. When a photosensitive resin material is used as the partition wall 7009, the step of forming the resist mask can be omitted.

Further, in the structure of FIG. 20C, when performing full-color display, for example, the light emitting element 70
02 is a green light emitting element, one adjacent light emitting element is a red light emitting element, and the other light emitting element is a blue light emitting element. Further, a light emitting display device capable of full-color display may be manufactured not only by three types of light emitting elements but also by four types of light emitting elements including a white element.

Further, in the structure of FIG. 20C, the plurality of light emitting elements to be arranged are all white light emitting elements, and a sealing substrate having a color filter or the like is arranged above the light emitting element 7002.
A light emitting display device capable of full-color display may be manufactured. Full-color display can be performed by forming a material that emits a single color such as white and combining it with a color filter and a color conversion layer.

20 (A) to 20 (C) show an example in which the thin film transistor and the first electrode layer are in direct contact with each other, but as in the fourth embodiment, between the drain electrode layer of the thin film transistor and the first electrode layer. It may be configured to be electrically connected with a connection electrode layer interposed therebetween. Also, TFT700
As for 1, 7011 and 7021, thin film transistors as shown in the second embodiment, the third embodiment and the fifth embodiment can also be used.

Of course, monochromatic light emission may be displayed. For example, a white light emitting device may be used to form an illumination device, or a single color light emitting device may be used to form an area color type light emitting device.

Further, if necessary, an optical film such as a polarizing film such as a circular polarizing plate may be provided.

Although the organic EL element has been described here as the light emitting element, the inorganic E as the light emitting element has been described.
It is also possible to provide an L element.

Although an example is shown in which the thin film transistor (driving TFT) that controls the driving of the light emitting element and the light emitting element are electrically connected, the current control TFT is connected between the driving TFT and the light emitting element. It may have a configuration that is present.

This embodiment can be appropriately combined with other embodiments.

(Embodiment 7)
In this embodiment, an example of the element structure of the light emitting element shown in the first to sixth embodiments will be described.

The element structure shown in FIG. 21 (A) has a pair of electrodes (first electrode 1001, second electrode 1002).
), The EL layer 1003 including the light emitting region is sandwiched between them. In the following description of the present embodiment, as an example, the first electrode 1001 is used as an anode and the second electrode 10 is used.
It is assumed that 02 is used as a cathode.

Further, the EL layer 1003 may be formed including at least a light emitting layer, and may have a laminated structure including a functional layer other than the light emitting layer. Functional layers other than the light emitting layer include substances with high hole injection property, substances with high hole transport property, substances with high electron transport property, substances with high electron transport property, and bipolar properties (electron and hole transport property). A layer containing a substance (high substance) or the like can be used. Specifically, functional layers such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer can be appropriately combined and used.

In the light emitting element shown in FIG. 21 (A), a current flows due to the potential difference generated between the first electrode 1001 and the second electrode 1002, and holes and electrons are recombined in the EL layer 1003 to emit light. It is a thing. That is, the structure is such that a light emitting region is formed on the EL layer 1003.

The light emission is taken out through either or both of the first electrode 1001 and the second electrode 1002. Therefore, either one or both of the first electrode 1001 and the second electrode 1002 is made of a translucent substance.

A plurality of EL layers may be laminated between the first electrode 1001 and the second electrode 1002 as shown in FIG. 21 (B). When it has a laminated structure of n (n is a natural number of 2 or more) layers,
It is preferable to provide a charge generation layer 1004 between the m (m is a natural number, m is 1 or more and n-1 or less) th EL layer and the (m + 1) th EL layer, respectively.

The charge generation layer 1004 is formed of a composite material of an organic compound and a metal oxide, a metal oxide, an organic compound and an alkali metal, an alkaline earth metal, or a composite material of these compounds, or a combination thereof as appropriate. Can be done. The composite material of an organic compound and a metal oxide, including, for example, an organic compound as _V 2 _{O 5,} MoO ₃ and WO _3, etc. of a metal oxide. As the organic compound, various compounds such as an aromatic amine compound, a carbazole derivative, an aromatic hydrocarbon, and a polymer compound (oligomer, dendrimer, polymer, etc.) can be used. note that,
As the organic compound, it is preferable to apply a hole-transporting organic compound having a hole mobility of ^10-6 cm ^{2 / Vs or more.} However, any substance other than these may be used as long as it is a substance having a higher hole transport property than electrons. Since these materials used for the charge generation layer 1004 are excellent in carrier injection property and carrier transport property, it is possible to realize low current drive and low voltage drive of the light emitting element.

The charge generation layer 1004 may be formed by combining a composite material of an organic compound and a metal oxide and another material. For example, a layer containing a composite material of an organic compound and a metal oxide may be formed in combination with a layer containing one compound selected from electron-donating substances and a compound having high electron-transporting properties. Further, a layer containing a composite material of an organic compound and a metal oxide may be formed in combination with a transparent conductive film.

A light emitting element having such a configuration is less likely to cause problems such as energy transfer and quenching.
By expanding the range of material selection, it is easy to obtain a light emitting element having both high luminous efficiency and long life. It is also easy to obtain phosphorescence emission from one EL layer and fluorescence emission from the other.

The charge generation layer 1004 injects holes into one EL layer 1003 formed in contact with the charge generation layer 1004 when a voltage is applied to the first electrode 1001 and the second electrode 1002. It has a function of injecting an electron into the other EL layer 1003.

The light emitting element shown in FIG. 21B can obtain various light emitting colors by changing the type of the light emitting substance used for the light emitting layer. Further, by using a plurality of light emitting substances having different light emitting colors as the light emitting substance, it is possible to obtain light emission having a broad spectrum or white light emission.

When white light is obtained by using the light emitting element shown in FIG. 21 (B), the combination of the plurality of light emitting layers may be a configuration that includes red, blue, and green light and emits white light, for example. Examples thereof include a configuration having a first EL layer containing a blue fluorescent material as a luminescent material and a second EL layer containing a green and red phosphorescent material as a luminescent material. Further, the configuration may include a first EL layer that emits red light, a second EL layer that emits green light, and a third EL layer that emits blue light. Alternatively, white light emission can be obtained even with a configuration having a light emitting layer that emits light having a complementary color relationship. In a laminated element in which two EL layers are laminated, when the emission color of light emission obtained from the first EL layer and the emission color of light emission obtained from the second EL layer are to have a complementary color relationship, the relationship of complementary colors is used. Can be blue and yellow, or turquoise and red.

In the above-mentioned configuration of the laminated element, by arranging the charge generating layer between the laminated EL layers, it is possible to realize a long-life element in a high brightness region while keeping the current density low. .. Further, since the voltage drop due to the resistance of the electrode material can be reduced, uniform light emission over a large area becomes possible.

This embodiment can be appropriately combined with the configurations described in other embodiments.

(Embodiment 8)
In the present embodiment, the appearance and cross section of the light emitting display panel (also referred to as a light emitting panel) will be described with reference to FIG. FIG. 22A is a plan view of a panel in which a thin film transistor and a light emitting element formed on the first substrate are sealed between the thin film transistor and the light emitting element with a sealing material.
22 (B) corresponds to the cross-sectional view taken along the line HI of FIG. 22 (A).

Pixel unit 4502 provided on the first substrate 4501, signal line drive circuits 4503a, 450
Sealing material 4505 so as to surround 3b and scanning line drive circuits 4504a and 4504b.
Is provided. A second substrate 4506 is provided on the pixel unit 4502, the signal line drive circuits 4503a and 4503b, and the scanning line drive circuits 4504a and 4504b. Therefore, the pixel unit 4502, the signal line drive circuits 4503a and 4503b, and the scanning line drive circuit 45
04a and 4504b are sealed together with the filler 4507 by the first substrate 4501, the sealing material 4505, and the second substrate 4506. As described above, it is preferable to package (enclose) with a protective film (bonded film, ultraviolet curable resin film, etc.) or a cover material having high airtightness and little degassing so as not to be exposed to the outside air.

Further, a pixel portion 4502 provided on the first substrate 4501 and a signal line drive circuit 4503a, 4
The 503b and the scanning line drive circuits 4504a and 4504b have a plurality of thin film transistors, and FIG. 22B illustrates the thin film transistor 4510 included in the pixel unit 4502 and the thin film transistor 4509 included in the signal line drive circuit 4503a. doing.

As the thin film transistors 4509 and 4510, highly reliable thin film transistors including the oxide semiconductor layer shown in the first to fifth embodiments can be applied. The thin film transistors 4509 for the drive circuit include the thin film transistors 180, 181 shown in the first to fifth embodiments.
182, as thin film transistors 4510 for pixels, thin film transistors 170, 171
, 172 can be used. In this embodiment, the thin film transistor 4509, 4
Reference numeral 510 denotes an n-channel thin film transistor.

The conductive layer 4540 is provided on the insulating layer 4544 at a position overlapping the channel forming region of the oxide semiconductor layer of the thin film transistor 4509 for the drive circuit. By providing the conductive layer 4540 at a position overlapping the channel forming region of the oxide semiconductor layer, it is possible to reduce the amount of change in the threshold voltage of the thin film transistor 4509 before and after the BT test. Further, the conductive layer 4540 may have the same potential as or different from the gate electrode layer of the thin film transistor 4509, and may function as a second gate electrode layer. In addition, the conductive layer 4
The potential of 540 may be GND, 0V, or a floating state.

Although not shown, the protective insulating layer 106 as shown in the first embodiment may be provided between the oxide insulating layer 4542 and the insulating layer 4544.

Further, the thin film transistor 4510 is electrically connected to the first electrode layer 4517.

The oxide insulating layer 4542 may be formed by the same material and method as the oxide insulating film 107 shown in the first embodiment.

A color filter layer 4545 is formed on the oxide insulating layer 4542 so as to overlap the light emitting region of the light emitting element 4511.

Further, the color filter layer 4545 is covered with an overcoat layer 4543 that functions as a flattening insulating film in order to reduce surface irregularities.

Further, an insulating layer 4544 is formed on the overcoat layer 4543. Insulation layer 4544
May be formed by the same material and method as the protective insulating layer 109 shown in the first embodiment.

Further, 4511 corresponds to a light emitting element, and the first electrode layer 4517, which is a pixel electrode of the light emitting element 4511, is electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4510. The light emitting element 4511 is composed of the first electrode layer 4517 and the electroluminescent layer 45.
12. The structure is a laminated structure of the second electrode layer 4513, but the configuration is not limited to the one shown. Light emitting element 4
The configuration of the light emitting element 4511 can be appropriately changed according to the direction of the light extracted from the 511 and the like.

The partition wall 4520 is formed by using an organic resin film, an inorganic insulating film, or an organic polysiloxane.
In particular, it is preferable to use a photosensitive material to form an opening on the first electrode layer 4517 so that the side wall of the opening becomes an inclined surface formed with a continuous curvature.

The electroluminescent layer 4512 may be composed of a single layer or may be configured such that a plurality of layers are laminated.

A protective film may be formed on the second electrode layer 4513 and the partition wall 4520 so that oxygen, hydrogen, water, carbon dioxide, etc. do not enter the light emitting element 4511. As a protective film, a silicon nitride film,
A silicon nitride film, a DLC film, or the like can be formed.

Further, the signal line drive circuits 4503a and 4503b and the scanning line drive circuits 4504a and 4504b
, Or various signals and potentials given to the pixel unit 4502 are FPC4518a, 4518.
It is supplied from b.

The connection terminal electrode 4515 is formed of the same conductive film as the first electrode layer 4517 of the light emitting element 4511, and the terminal electrode 4516 is formed of the same conductive film as the source electrode layer and drain electrode layer of the thin film transistor 4509.

The connection terminal electrode 4515 is electrically connected to the terminal of the FPC 4518a via an anisotropic conductive film 4519.

For a substrate located in the direction of extracting light from the light emitting element 4511, the second substrate must be translucent. In that case, a translucent material such as a glass plate, a plastic plate, a polyester film or an acrylic film is used.

Further, as the filler 4507, in addition to an inert gas such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin can be used, and PVC (polyvinyl chloride), acrylic, etc. can be used.
Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV
A (ethylene vinyl acetate) can be used. For example, nitrogen may be used as the filler.

If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) is provided on the ejection surface of the light emitting element.
An optical film such as a retardation plate (λ / 4 plate, λ / 2 plate) or a color filter may be appropriately provided. Further, an antireflection film may be provided on the polarizing plate or the circular polarizing plate. For example, an anti-glare treatment that can diffuse the reflected light due to the unevenness of the surface and reduce the reflection can be applied.

The signal line drive circuits 4503a and 4503b and the scanning line drive circuits 4504a and 4504b may be mounted by a drive circuit formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate. Further, only the signal line drive circuit, or a part of the signal line drive circuit, or only the scan line drive circuit, or only a part of the scan line drive circuit may be separately formed and mounted, and the configuration is not limited to that shown in FIG.

Through the above steps, a highly reliable light emitting device (display panel) can be manufactured as a semiconductor device.

This embodiment can be implemented in combination with the configurations described in other embodiments as appropriate.

(Embodiment 9)
In the present embodiment, an example of producing at least a part of the drive circuit and a thin film transistor to be arranged in the pixel portion on the same substrate will be described below.

The thin film transistor to be arranged in the pixel portion is formed according to the first to fifth embodiments. Further, since the thin film transistors shown in the first to fifth embodiments are n-channel type TFTs, a part of the drive circuit that can be configured by the n-channel type TFTs is placed on the same substrate as the thin film transistor of the pixel portion. Form.

An example of a block diagram of the active matrix type display device is shown in FIG. 12 (A). On the substrate 5300 of the display device, a pixel unit 5301, a first scanning line driving circuit 5302, a second scanning line driving circuit 5303, and a signal line driving circuit 5304 are provided. A plurality of signal lines extend from the signal line drive circuit 5304 and are arranged in the pixel unit 5301, and a plurality of scan lines extend from the first scan line drive circuit 5302 and the second scan line drive circuit 5303. Have been placed. In the intersection region of the scanning line and the signal line, pixels having a display element are arranged in a matrix. Further, the substrate 5300 of the display device is FPC (Flexible Printed Ci).
Timing control circuit 5305 (controller, control I) via a connection such as rcuit)
It is also connected to C).

In FIG. 12A, the first scanning line driving circuit 5302, the second scanning line driving circuit 5303, and the signal line driving circuit 5304 are formed on the same substrate 5300 as the pixel unit 5301. Therefore, the number of parts such as a drive circuit provided externally is reduced, so that the cost can be reduced. Further, when the drive circuit is provided outside the substrate 5300, the number of connections at the connection portion can be reduced by extending the wiring, and the reliability or the yield can be improved.

The timing control circuit 5305 supplies the first scanning line driving circuit 5302 with, for example, a first scanning line driving circuit start signal (GSP1) and a scanning line driving circuit clock signal (GCLK1). Further, the timing control circuit 5305 has, as an example, a second scanning line driving circuit start signal (GSP2) (also referred to as a start pulse) and a scanning line driving circuit clock signal (also referred to as a start pulse) with respect to the second scanning line driving circuit 5303. GCLK2) is supplied. The timing control circuit 5305 has a signal line drive circuit 5304, a signal line drive circuit start signal (SSP), a signal line drive circuit clock signal (SCLK), and video signal data (DA).
TA) (also simply referred to as a video signal) and a latch signal (LAT) shall be supplied. Each clock signal may be a plurality of clock signals having different periods, or may be supplied together with a signal (CKB) obtained by inverting the clock signal. It is possible to omit one of the first scanning line driving circuit 5302 and the second scanning line driving circuit 5303.

In FIG. 12B, a circuit having a low drive frequency (for example, the first scan line drive circuit 5302 and the second scan line drive circuit 5303) is formed on the same substrate 5300 as the pixel portion 5301, and the signal line drive circuit 5304 is formed. Is shown for a configuration in which is formed on a substrate different from the pixel portion 5301. With this configuration, a drive circuit formed on the substrate 5300 can be configured by a thin film transistor having a smaller field effect mobility than a transistor using a single crystal semiconductor. Therefore, it is possible to increase the size of the display device, reduce the cost, or improve the yield.

Further, the thin film transistors shown in the first to fifth embodiments are n-channel TFTs. Figure 1
3 (A) and FIG. 13 (B) show and explain an example of the configuration and operation of the signal line drive circuit configured by the n-channel TFT.

The signal line drive circuit has a shift register 5601 and a switching circuit 5602.
The switching circuit 5602 has a plurality of circuits called switching circuits 5602_1 to 5602_N (N is a natural number). Each of the switching circuits 5602_1 to 5602_N has a plurality of transistors called thin film transistors 5603_1 to 5603_k (k is a natural number). An example in which the thin film transistors 5603_1 to 5603_k are n-channel TFTs will be described.

The connection relationship of the signal line drive circuit will be described by taking the switching circuit 5602_1 as an example. The first terminals of the thin film transistors 5603_1 to 5603_k are each wired 5604_1.
It is connected to ~ 5604_k. The second terminals of the thin film transistors 5603_1 to 5603_k are connected to the signal lines S1 to Sk, respectively. Thin film transistor 5603_1 to 5603_
The gate of k is connected to the wiring 5605_1.

The shift register 5601 outputs H level (also referred to as H signal, high power supply potential level) signals to the wirings 5605_1 to 5605_N in order, and the switching circuit 5602_1 to 56
It has a function to select 02_N in order.

The switching circuit 5602_1 includes wirings 5604_1 to 5604_k and signal lines S1 to Sk.
Function to control the continuity state with (conduction between the first terminal and the second terminal), that is, wiring 5604_
It has a function of controlling whether or not a potential of 1 to 5604_k is supplied to the signal lines S1 to Sk.
As described above, the switching circuit 5602_1 has a function as a selector. Further, the thin film transistors 5603_1 to 5603_k are respectively wired 5604_1 to 5604_k.
Function to control the conduction state between the signal lines S1 to Sk, that is, wiring 5604_1 to 5604_k
Has a function of supplying the potential of the above to the signal lines S1 to Sk. Thus, the thin film transistor 56
Each of 03_1 to 5603_k has a function as a switch.

Video signal data (DATA) is input to the wirings 5604_1 to 5604_k, respectively. The video signal data (DATA) is often image information or an analog signal corresponding to the image signal.

Next, the operation of the signal line drive circuit of FIG. 13 (A) will be described with reference to the timing chart of FIG. 13 (B). FIG. 13B shows an example of signals Sout_1 to Sout_N and signals Vdata_1 to Vdata_k. The signals Sout_1 to Sout_N are examples of output signals of the shift register 5601, respectively, and the signals Vdata_1 to Vdata
_K is an example of a signal input to the wirings 5604_1 to 5604_k, respectively. note that,
One operation period of the signal line drive circuit corresponds to one gate selection period in the display device. One gate selection period is divided into period T1 to period TN as an example. The periods T1 to TN are periods for writing the video signal data (DATA) to the pixels belonging to the selected row, respectively.

In addition, the bluntness of the signal waveform and the like of each configuration shown in the drawings and the like of the present embodiment may be exaggerated for the sake of clarification. Therefore, it should be added that it is not necessarily limited to that scale.

In the period T1 to the period TN, the shift register 5601 wire the H level signal 560.
Outputs in order from 5-1 to 5605_N. For example, in period T1, shift register 5
The 601 outputs a high level signal to the wiring 5605_1. Then, since the thin film transistors 5603_1 to 5603_k are turned on, the wirings 5604_1 to 5604_k and the signal lines S1 to Sk become conductive. At this time, in the wirings 5604_1 to 5604_k,
Data (S1) to Data (Sk) are input. Data (S1) to Data (Sk)
) Are written to the pixels in the first column to the kth column among the pixels belonging to the selected row via the thin film transistors 5603_1 to 5603_k, respectively. In this way, in the periods T1 to TN, the video signal data (DATA) is written in order of k columns to the pixels belonging to the selected row.

As described above, the number of video signal data (DATA) or the number of wirings can be reduced by writing the video signal data (DATA) to the pixels in a plurality of columns.
Therefore, the number of connections with the external circuit can be reduced. Further, by writing the video signal to the pixels in a plurality of columns, the writing time can be lengthened and the writing shortage of the video signal can be prevented.

As the shift register 5601 and the switching circuit 5602, it is possible to use the circuit composed of the thin film transistors shown in the first to fifth embodiments.

A form of a shift register used as a part of a scanning line driving circuit and / or a signal line driving circuit will be described with reference to FIGS. 14 and 15.

The scanning line drive circuit has a shift register. In some cases, it may have a level shifter, a buffer, or the like. In the scanning line drive circuit, a selection signal is generated by inputting a clock signal (CLK) and a start pulse signal (SP) to the shift register. The generated selection signal is buffer amplified in the buffer and fed to the corresponding scan line. The gate electrode of the transistor of one line of pixels is connected to the scanning line. Then, since the transistors of one line of pixels must be turned on all at once, a buffer capable of passing a large current is used.

The shift register is a first pulse output circuit 10_1 to an Nth pulse output circuit 10_N (
N has a natural number of 3 or more) (see FIG. 14 (A)). In the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N of the shift register shown in FIG. 14A, the first clock signal CK1 from the first wiring 11 and the second clock signal CK1 from the second wiring 12 Clock signal CK2
, The third clock signal CK3 is supplied from the third wiring 13, and the fourth clock signal CK4 is supplied from the fourth wiring 14. Further, in the first pulse output circuit 10_1, the start pulse SP1 (first start pulse) from the fifth wiring 15 is input. Further, in the nth pulse output circuit 10_n (n is a natural number of 2 or more and N or less) in the second and subsequent stages, the signal from the pulse output circuit 10_n-1 of the first stage (referred to as the previous stage signal OUT (n-1)) (referred to as the previous stage signal OUT (n-1)). A natural number (n or more and 2) is input. Further, in the first pulse output circuit 10_1, a signal from the third pulse output circuit 10_3 in the second stage after the second stage is input. Similarly, the nth pulse output circuit 10_n of the second and subsequent stages
Then, the signal from the second (n + 2) pulse output circuit 10_ (n + 2) in the second stage and the second stage (referred to as the latter stage signal OUT (n + 2)) is input. Therefore, from the pulse output circuit of each stage, the first output signal (OUT (1) (SR) for inputting to the pulse output circuit of the rear stage and / or the front stage.
)-OUT (N) (SR)), a second output signal (OUT (1)-
OUT (N)) is output. As shown in FIG. 14A, since the subsequent stage signal OUT (n + 2) is not input to the two final stages of the shift register, as an example, the second start pulse SP2 and the third stage are separately used. The start pulse SP3 may be input respectively.

The clock signal (CK) is a signal that repeats an H level and an L level (also referred to as an L signal or a low power supply potential level) at regular intervals. Here, the first clock signal (CK1) to the fourth clock signal (CK4) are delayed by 1/4 cycle in order (that is, 90 each other).
° out of phase). In the present embodiment, the drive of the pulse output circuit is controlled by using the first clock signal (CK1) to the fourth clock signal (CK4). The clock signal may be GCK or SCK depending on the input drive circuit, but here C
The explanation will be given as K.

FIG. 14B shows one of the pulse output circuits 10_1 to 10_N shown in FIG. 14A.
The first input terminal 21, the second input terminal 22, and the third input terminal 23 are connected to the first wiring 11 to 11.
It is electrically connected to any of the fourth wires 14. For example, in FIG. 14 (A).
In the first pulse output circuit 10_1, the first input terminal 21 is electrically connected to the first wiring 11, the second input terminal 22 is electrically connected to the second wiring 12, and the third The input terminal 23 is electrically connected to the third wiring 13. Further, in the second pulse output circuit 10_2, the first input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 is electrically connected to the third wiring 13. The input terminal 23 of 3 is electrically connected to the 4th wiring 14.

Each of the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N has a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, and a fifth. It is assumed that the input terminal 25, the first output terminal 26, and the second output terminal 27 are provided (see FIG. 14B). In the first pulse output circuit 10_1, the first clock signal CK1 is input to the first input terminal 21, the second clock signal CK2 is input to the second input terminal 22, and the third is
The third clock signal CK3 is input to the input terminal 23 of the above, the start pulse is input to the fourth input terminal 24, the subsequent signal OUT (3) is input to the fifth input terminal 25, and the first output terminal. The first output signal OUT (1) (SR) is output from 26, and the second output signal OUT (1) is output from the second output terminal 27.

The first pulse output circuit 10_1 to the Nth pulse output circuit 10_N may use a 4-terminal thin film transistor described in the above embodiment in addition to a 3-terminal thin film transistor (also referred to as a TFT: Thin Film Transistor). can. In the present specification, when the thin film transistor has two gate electrodes via the semiconductor layer, the gate electrode below the semiconductor layer is referred to as the lower gate electrode, and the gate electrode above the semiconductor layer is referred to as the upper gate electrode. Call.

When an oxide semiconductor is used for a semiconductor layer including a channel forming region of a thin film transistor, the threshold voltage may shift to the minus side or the plus side depending on the manufacturing process. Therefore, in a thin film transistor using an oxide semiconductor for the semiconductor layer including the channel formation region,
A configuration capable of controlling the threshold voltage is preferable. The threshold voltage of the four-terminal thin film transistor can be controlled to a desired value by controlling the potentials of the upper and / or lower gate electrodes.

Next, FIG. 14 shows an example of a specific circuit configuration of the pulse output circuit shown in FIG. 14 (B).
This will be described in (C).

The pulse output circuit shown in FIG. 14C has first transistors 31 to thirteen transistors 43. Further, in addition to the first input terminals 21 to 5 described above, the power supply line 51 to which the first high power supply potential VDD is supplied and the power supply line 52 to which the second high power supply potential VCS is supplied. From the power supply line 53 to which the low power supply potential VSS is supplied, the first transistor 31
A signal or power supply potential is supplied to the thirteenth transistor 43. Further, a signal or the like is output to the first output terminal 26 and the second output terminal 27. Here, regarding the magnitude relationship of the power supply potentials of the power supply lines in FIG. 14C, the first power supply potential VDD is a potential equal to or higher than the second power supply potential VCS, and the second power supply potential VCS is the third power supply potential. The potential is larger than VSS. The first clock signal (CK1) to the fourth clock signal (CK4) are signals that repeat the H level and the L level at regular intervals, and are VDD at the H level and VSS at the L level. And. By making the potential VDD of the power supply line 51 higher than the potential VCS of the power supply line 52, the potential applied to the gate electrode of the transistor can be suppressed low without affecting the operation, and the threshold value of the transistor can be suppressed. Shift can be reduced and deterioration can be suppressed. Of the first transistors 31 to 13 transistors 43, it is preferable to use a four-terminal thin film transistor for the first transistor 31, the sixth transistor 36 to the ninth transistor 39. 1st transistor 31 and 6th transistor 36
The ninth transistor 39 is a transistor that is required to switch the potential of the node to which one of the source or drain electrodes is connected by the control signal of the gate electrode, and is a response to the control signal input to the gate electrode. It is a transistor that can reduce the malfunction of the pulse output circuit due to its high speed (the rise of the on-current is steep).
Therefore, the threshold voltage can be controlled by using the 4-terminal thin film transistor, and the pulse output circuit can further reduce the malfunction.

In FIG. 14C, in the first transistor 31, the first terminal is electrically connected to the power supply line 51, the second terminal is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode. (Lower gate electrode and upper gate electrode) are electrically connected to the fourth input terminal 24. In the second transistor 32, the first terminal is electrically connected to the power supply line 53, the second terminal is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode is the fourth transistor 34. It is electrically connected to the gate electrode. In the third transistor 33, the first terminal is electrically connected to the first input terminal 21, and the second terminal is electrically connected to the first output terminal 26. The first terminal of the fourth transistor 34 is electrically connected to the power supply line 53, and the fourth transistor 34 has a first terminal electrically connected to the power supply line 53.
The second terminal is electrically connected to the first output terminal 26. The fifth transistor 35 is
The first terminal is electrically connected to the power supply line 53, the second terminal is electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34, and the gate electrode is the fourth input terminal. It is electrically connected to 24. In the sixth transistor 36, the first terminal is electrically connected to the power supply line 52, the second terminal is electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34, and the gate is formed. The electrodes (lower gate electrode and upper gate electrode) are electrically connected to the fifth input terminal 25. In the seventh transistor 37, the first terminal is electrically connected to the power supply line 52, and the second terminal is the eighth transistor 38.
Electrically connected to the second terminal of the gate electrode (lower gate electrode and upper gate electrode)
Is electrically connected to the third input terminal 23. In the eighth transistor 38, the first terminal is electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34, and the gate electrode (lower gate electrode and upper gate electrode) is the second. It is electrically connected to the input terminal 22 of 2. In the ninth transistor 39, the first terminal is electrically connected to the second terminal of the first transistor 31 and the second terminal of the second transistor 32, and the second terminal is the gate electrode of the third transistor 33 and the second terminal. It is electrically connected to the gate electrode of the tenth transistor 40, and the gate electrodes (lower gate electrode and upper gate electrode) are connected to the power supply line 52.
Is electrically connected to. In the tenth transistor 40, the first terminal is the first input terminal 2.
It is electrically connected to 1, the second terminal is electrically connected to the second output terminal 27, and the gate electrode is electrically connected to the second terminal of the ninth transistor 39. In the eleventh transistor 41, the first terminal is electrically connected to the power supply line 53, the second terminal is electrically connected to the second output terminal 27, and the gate electrode is the gate electrode of the second transistor 32 and the gate electrode. It is electrically connected to the gate electrode of the fourth transistor 34. In the twelfth transistor 42, the first terminal is electrically connected to the power supply line 53, the second terminal is electrically connected to the second output terminal 27, and the gate electrode is the gate electrode of the seventh transistor 37 ( It is electrically connected to the lower gate electrode and the upper gate electrode). The first terminal of the thirteenth transistor 43 is the power supply line 5.
Electrically connected to 3, the second terminal is electrically connected to the first output terminal 26, and the gate electrode is electrically connected to the gate electrode (lower gate electrode and upper gate electrode) of the seventh transistor 37. It is connected to the.

In FIG. 14C, the gate electrode of the third transistor 33 and the tenth transistor 4
A node A is a connection point between the gate electrode of 0 and the second terminal of the ninth transistor 39.
Further, the gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, the second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, the first terminal of the eighth transistor 38, And the connection point of the gate electrode of the eleventh transistor 41 is the node B.
And.

In FIG. 15 (A), the pulse output circuit described in FIG. 14 (C) is replaced with the first pulse output circuit 10_.
When applied to 1, the first input terminal 21 to the fifth input terminal 25 and the first output terminal 26
And the signal input or output to the second output terminal 27 is shown.

Specifically, the first clock signal CK1 is input to the first input terminal 21, the second clock signal CK2 is input to the second input terminal 22, and the third clock is input to the third input terminal 23. The signal CK3 is input, the start pulse (SP1) is input to the fourth input terminal 24, and the fifth input terminal 24 is input.
The latter-stage signal OUT (3) is input to the input terminal 25 of the above, the first output signal OUT (1) (SR) is output from the first output terminal 26, and the second output signal is output from the second output terminal 27. OUT (
1) is output.

The thin film transistor is an element having at least three terminals including a gate, a drain, and a source. Further, it has a semiconductor in which a channel region is formed in a region superimposed on the gate, and by controlling the potential of the gate, it is possible to control the current flowing between the drain and the source via the channel region. Here, since the source and the drain change depending on the structure and operating conditions of the thin film transistor, it is difficult to limit which is the source or the drain. Therefore, the region that functions as a source and a drain may not be called a source or a drain. In that case, as an example, each is the first
It may be referred to as a terminal or a second terminal.

Note that, in FIGS. 14C and 15A, a capacitive element may be separately provided for performing the bootstrap operation by putting the node A in a floating state. Further, in order to hold the potential of the node B, a capacitive element in which one electrode is electrically connected to the node B may be separately provided.

Here, the timing chart of the shift register including the plurality of pulse output circuits shown in FIG. 15 (A) is shown in FIG. 15 (B). When the shift register is a scanning line drive circuit, the period 61 in FIG. 15B corresponds to the vertical blanking interval, and the period 62 corresponds to the gate selection period.

As shown in FIG. 15A, a ninth power supply potential VCS is applied to the gate electrode.
By providing the transistor 39 of the above, there are the following advantages before and after the bootstrap operation.

When the gate electrode does not have the ninth transistor 39 to which the second power potential VCS is applied, when the potential of the node A rises due to the bootstrap operation, the second transistor 31 of the first transistor 31 is second.
The potential of the source, which is a terminal, rises and becomes larger than the first power supply potential VDD. Then, the source of the first transistor 31 is switched to the first terminal side, that is, the power supply line 51 side. Therefore, in the first transistor 31, a large bias voltage is applied between the gate and the source and between the gate and the drain, so that a large stress is applied, which may cause deterioration of the transistor. Therefore, a ninth power supply potential VCS is applied to the gate electrode.
By providing the transistor 39 of the above, although the potential of the node A rises due to the bootstrap operation, it is possible to prevent the potential of the second terminal of the first transistor 31 from rising. That is, by providing the ninth transistor 39, the value of the negative bias voltage applied between the gate and the source of the first transistor 31 can be reduced. Therefore, by adopting the circuit configuration of the present embodiment, the negative bias voltage applied between the gate and the source of the first transistor 31 can be reduced, so that the deterioration of the first transistor 31 due to stress is suppressed. be able to.

It should be noted that the location where the ninth transistor 39 is provided is the second of the first transistor 31.
The configuration may be such that the terminal and the gate of the third transistor 33 are connected via the first terminal and the second terminal. In the case of the shift register including a plurality of pulse output circuits in the present embodiment, the ninth transistor 39 may be omitted in the signal line drive circuit having more stages than the scan line drive circuit, and the number of transistors is reduced. There is an advantage.

By using an oxide semiconductor as the semiconductor layer of the first transistor 31 to the thirteenth transistor 43, the off-current of the thin film transistor can be reduced, the on-current and the field effect mobility can be increased, and the deterioration can be achieved. Since the degree can be reduced, malfunctions in the circuit can be reduced. Transistors using oxide semiconductors
Compared to a transistor using amorphous silicon, the degree of deterioration of the transistor due to the application of a high potential to the gate electrode is small. Therefore, the same operation can be obtained even if the first power supply potential VDD is supplied to the power supply line that supplies the second power supply potential VCS, and the number of power supply lines running between the circuits can be reduced. The circuit can be miniaturized.

The gate electrode of the seventh transistor 37 (lower gate electrode and upper gate electrode)
The clock signal supplied by the third input terminal 23 and the clock signal supplied by the second input terminal 22 to the gate electrodes (lower gate electrode and upper gate electrode) of the eighth transistor 38 are the seventh. The clock signal supplied by the second input terminal 22 to the gate electrode of the transistor 37 (lower gate electrode and upper gate electrode), and the gate electrode of the eighth transistor 38 (lower gate electrode and upper gate electrode). Third input terminal 23
The same effect is obtained even if the connection relationship is exchanged so that the clock signal is supplied by. In the shift register shown in FIG. 15A, the seventh transistor 37 and the eighth transistor 38 are both on, the seventh transistor 37 is off, the eighth transistor 38 is on, and then By turning off the seventh transistor 37 and turning off the eighth transistor 38, the second input terminal 22 and the third input terminal 23 are turned off.
The decrease in the potential of the node B caused by the decrease in the potential of the node B occurs twice due to the decrease in the potential of the gate electrode of the seventh transistor 37 and the decrease in the potential of the gate electrode of the eighth transistor 38. It becomes. On the other hand, in the shift register shown in FIG. 15A, the seventh transistor 3 is changed from the state in which both the seventh transistor 37 and the eighth transistor 38 are on.
The second input terminal 22 and the third input terminal are turned on by turning 7 on and the eighth transistor 38 off, then turning the seventh transistor 37 off and turning the eighth transistor 38 off, so that the second input terminal 22 and the third input terminal are turned off. The decrease in the potential of the node B caused by the decrease in the potential of the 23 can be reduced to one time due to the decrease in the potential of the gate electrode of the eighth transistor 38. for that reason,
A third to the gate electrode (lower gate electrode and upper gate electrode) of the seventh transistor 37
The clock signal CK3 is supplied from the input terminal 23 of the above, and the clock signal C is supplied from the second input terminal 22 to the gate electrodes (lower gate electrode and upper gate electrode) of the eighth transistor 38.
It is preferable to have a wiring relationship in which K2 is supplied. This is because the number of fluctuations in the potential of the node B can be reduced and noise can be reduced.

In this way, the pulse output is configured so that the H level signal is periodically supplied to the node B during the period in which the potentials of the first output terminal 26 and the second output terminal 27 are held at the L level. It is possible to suppress the malfunction of the circuit.

This embodiment can be implemented in combination with the configurations described in other embodiments as appropriate.

(Embodiment 10)
The light emitting device disclosed in the present specification can be applied to various electronic devices (including gaming machines). Examples of electronic devices include television devices (also referred to as televisions or television receivers), monitors for computers, digital cameras, digital video cameras, digital photo frames, and mobile phones (also referred to as mobile phones and mobile phone devices). ), Portable game machines, mobile information terminals, sound reproduction devices, large game machines such as pachinko machines, and the like.

FIG. 23A shows an example of a mobile phone. The mobile phone 1100 has a housing 1101.
In addition to the display unit 1102 incorporated in the above, it is provided with an operation button 1103, an external connection port 1104, a speaker 1105, a microphone 1106, and the like.

The mobile phone 1100 shown in FIG. 23A can input information by touching the display unit 1102 with a finger or the like. In addition, operations such as making a phone call or typing an e-mail can be performed by touching the display unit 1102 with a finger or the like.

The screen of the display unit 1102 mainly has three modes. The first is a display mode mainly for displaying an image, and the second is an input mode mainly for inputting information such as characters. The third is a display + input mode in which two modes, a display mode and an input mode, are mixed.

For example, when making a phone call or composing an e-mail, the display unit 1102 may be set to a character input mode mainly for inputting characters, and the characters displayed on the screen may be input. In this case, it is preferable to display the keyboard or the number button on most of the screen of the display unit 1102.

Further, by providing a detection device having a sensor for detecting the inclination of a gyro, an acceleration sensor, or the like inside the mobile phone 1100, the orientation (vertical or horizontal) of the mobile phone 1100 can be determined and the screen display of the display unit 1102 can be determined. Can be switched automatically.

Further, the screen mode can be switched by touching the display unit 1102 or by operating the operation button 1103 of the housing 1101. It is also possible to switch depending on the type of the image displayed on the display unit 1102. For example, if the image signal displayed on the display unit is moving image data, the display mode is switched, and if the image signal is text data, the input mode is switched.

Further, in the input mode, the signal detected by the optical sensor of the display unit 1102 is detected, and when there is no input by the touch operation of the display unit 1102 for a certain period of time, the screen mode is switched from the input mode to the display mode. You may control it.

The display unit 1102 can also function as an image sensor. For example, display unit 11
By touching 02 with a palm or a finger, a palm print, a fingerprint, or the like can be imaged to authenticate the person. Further, if a backlight that emits near-infrared light or a sensing light source that emits near-infrared light is used for the display unit, it is possible to image finger veins, palmar veins, and the like.

Since the light emitting device shown in the first to ninth embodiments is used for the display unit 1102, the reliability can be improved.

FIG. 23B is an example of a portable information terminal. The portable information terminal shown in FIG. 23B as an example can be provided with a plurality of functions. For example, in addition to the telephone function, a computer can be built in and various data processing functions can be provided.

The portable information terminal shown in FIG. 23B is composed of two housings, a housing 1800 and a housing 1801. The housing 1801 is provided with a display panel 1802, a speaker 1803, a microphone 1804, a pointing device 1806, a camera lens 1807, an external connection terminal 1808, and the like, and the housing 1800 is provided with a keyboard 1810, an external memory slot 1811, and the like. There is. Further, the antenna is built in the housing 1800 or 1801.

Further, the display panel 1802 is provided with a touch panel, and in FIG. 23B, a plurality of operation keys 1805 displayed as images are shown by dotted lines.

Further, in addition to the above configuration, a non-contact IC chip, a small recording device, or the like may be built in.

The light emitting device can be used for the display panel 1802, and the display direction is appropriately changed according to the usage pattern. Further, since the camera lens 1807 is provided on the same surface as the display panel 1802, a videophone can be made. The speaker 1803 and the microphone 1804 are not limited to voice calls, but can be used for videophones, recording, playback, and the like. Further, the housing 1800 and the housing 1801 can be slid and changed from the unfolded state as shown in FIG. 23B to the overlapping state, and can be miniaturized suitable for carrying.

The external connection terminal 1808 can be connected to various cables such as an AC adapter and a USB cable, and can be charged and data communication with a personal computer or the like is possible. Further, a recording medium can be inserted into the external memory slot 1811 to support storage and movement of a larger amount of data.

Further, in addition to the above functions, an infrared communication function, a television reception function, and the like may be provided.

FIG. 24A shows an example of a television device. The television device 9600 is
A display unit 9603 is incorporated in the housing 9601. The display unit 9603 makes it possible to display an image. Further, here, a configuration in which the housing 9601 is supported by the stand 9605 is shown.

The operation of the television device 9600 can be performed by the operation switch provided in the housing 9601 or the remote control operation device 9610 separately provided. The operation keys 9609 included in the remote controller 9610 can be used to control the channel and volume, and the image displayed on the display unit 9603 can be operated. Further, the remote controller 9610 may be provided with a display unit 9607 for displaying information output from the remote controller 9610.

The television device 9600 is configured to include a receiver, a modem, and the like. The receiver can receive general television broadcasts, and by connecting to a wired or wireless communication network via a modem, it can be unidirectional (sender to receiver) or bidirectional (sender and receiver). It is also possible to perform information communication between (or between recipients, etc.).

Since the light emitting device shown in the first to ninth embodiments is used for the display unit 9603, the reliability can be improved.

FIG. 24B shows an example of the digital photo frame 9700. For example, in the digital photo frame 9700, the display unit 9703 is incorporated in the housing 9701. The display unit 9703 can display various images, and by displaying image data taken by, for example, a digital camera, the display unit 9703 can function in the same manner as a normal photo frame.

Since the light emitting device shown in the first to ninth embodiments is used for the display unit 9703, the reliability can be improved.

The digital photo frame 9700 has an operation unit and an external connection terminal (USB terminal, US).
A terminal that can be connected to various cables such as a B cable), a recording medium insertion part, and the like are provided. These configurations may be incorporated on the same surface as the display unit, but it is preferable to provide them on the side surface or the back surface because the design is improved. For example, a memory that stores image data taken by a digital camera can be inserted into a recording medium insertion unit of a digital photo frame to capture the image data, and the captured image data can be displayed on the display unit 9703.

Further, the digital photo frame 9700 may be configured to be able to transmit and receive information wirelessly. It is also possible to adopt a configuration in which desired image data is captured and displayed wirelessly.

FIG. 25 is a portable game machine, which is composed of two housings, a housing 9881 and a housing 9891, and is openably and closably connected by a connecting portion 9893. Display unit 988 on the housing 9881
2 is incorporated, and a display unit 9883 is incorporated in the housing 9891.

Since the light emitting devices shown in the first to ninth embodiments are used for the display units 9882 and 9883, the reliability can be improved.

In addition, the portable gaming machine shown in FIG. 25 includes a speaker unit 9884 and a recording medium insertion unit 9.
886, LED lamp 9890, input means (operation key 9858, connection terminal 9878, sensor 9888 (force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, voice, voice, It includes a function to measure time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays), microphone 9889) and the like. Of course, the configuration of the portable game machine is not limited to the above, and at least the configuration including the thin film transistor disclosed in the present specification may be used, and other auxiliary equipment may be appropriately provided. The portable game machine shown in FIG. 25 has a function of reading a program or data recorded on a recording medium and displaying it on a display unit, and a function of wirelessly communicating with another portable game machine to share information. .. The functions of the portable game machine shown in FIG. 25 are not limited to this, and can have various functions.

FIG. 26 is an example in which a light emitting device formed by applying the above embodiment is used as an indoor lighting device 3001. Since the light emitting device shown in the above embodiment can have a large area, it can be used as a large area lighting device. Further, the light emitting device shown in the second embodiment can also be used as a tabletop lighting fixture 3000. In addition to ceiling-fixed lighting fixtures and tabletop lighting fixtures, lighting fixtures include wall-mounted lighting fixtures, interior lighting, guide lights, and the like.

As described above, the light emitting devices shown in the first to ninth embodiments can be arranged on the display panels of various electronic devices as described above, and highly reliable electronic devices can be provided.

10 Pulse output circuit 11 Wiring 12 Wiring 13 Wiring 14 Wiring 15 Wiring 21 Input terminal 22 Input terminal 23 Input terminal 24 Input terminal 25 Input terminal 26 Output terminal 27 Output terminal 31 Transistor 32 Transistor 33 Transistor 34 Transistor 35 Transistor 36 Transistor 37 Transistor 38 Transistor 39 Transistor 40 Transistor 41 Transistor 42 Transistor 43 Transistor 51 Power supply line 52 Power supply line 53 Power supply line 100 Substrate 101 Gate electrode layer 102 Gate insulation layer 103 Oxide semiconductor layer 106 Protective insulation layer 107 Oxide insulation film 108 Capacitive wiring layer 109 Protection Insulation layer 110 Electrode layer 111 Conductive layer 112 Conductive layer 113 Terminal electrode 116 Channel formation region 118 Contact hole 119 Contact hole 120 Connection electrode 121 Terminal 122 Terminal 125 Contact hole 126 Contact hole 127 Contact hole 128 Terminal electrode 129 Terminal electrode 130 Oxide semiconductor Film 131 Oxide semiconductor layer 133 Oxide semiconductor layer 134 Oxide semiconductor layer 137 Resist mask 138 Oxide conductive layer 140 Oxide conductive layer 142 Oxide conductive layer 143 Oxide conductive layer 145 Wiring layer 146 Capacity 147 Capacity 149 Capacity Electrode layer 150 Terminal 151 Terminal 153 Connection electrode 155 Conductive electrode 156 Electrode 161 Gate electrode layer 162 Conductive layer 163 Oxide semiconductor layer 166 Channel formation region 168 Oxide semiconductor layer 170 Thin film 171 Thin film 172 Thin film 173 Thin film 180 Thin film 181 Thin film 182 Thin film 183 Thin film 185 Capacitive electrode layer 191 Color filter layer 192 Overcoat layer 193 Partition wall 194 EL layer 195 Electrode layer 196 Connection electrode layer 198 Oxide semiconductor layer 1001 Electrode 1002 Electrode 1003 EL layer 1004 Charge generation layer 104a Oxide conductive layer 104b Oxide conductive layer 105a Source electrode layer 105b Drain electrode layer 1100 Mobile phone 1101 Housing 1102 Display 1103 Operation button 1104 External connection port 1105 Speaker 1106 Mike 117a High resistance source area 117b High resistance drain area 135a Resist mask 136a Resist mask 1 64a Oxide conductive layer 164b Oxide conductive layer 165a Source electrode layer 165b Drain electrode layer 167a High resistance source area 167b High resistance drain area 1800 Housing 1801 Housing 1802 Display panel 1803 Speaker 1804 Microphone 1805 Operation key 1806 Pointing device 1807 For camera Lens 1808 External connection terminal 1810 Keyboard 1811 External memory slot 3000 Desktop lighting equipment 3001 Lighting device 4501 Substrate 4502 Pixel part 4505 Sealing material 4506 Substrate 4507 Filling material 4509 Thin film transistor 4510 Thin film transistor 4511 Light emitting element 4512 Electroelectric light emitting layer 4513 Electrode layer 4515 Connection terminal Electrode 4516 Terminal electrode 4517 Electrometric thin film transistor 4520 Anisotropic thin film transistor 4520 Partition 4540 Conductive layer 4542 Oxide insulation layer 4543 Overcoat layer 4544 Insulation layer 4545 Color filter layer 4546 Insulation layer 5300 Substrate 5301 Pixel part 5302 Scan line drive circuit 5303 Scan line drive circuit 5304 Signal line drive circuit 5305 Timing control circuit 5301 Shift register 5602 Switching circuit 5603 Thin film transistor 5604 Wiring 5605 Wiring 6400 pixels 6401 Switching transistor 6402 Transistor 6403 Capacitive element 6404 Light emitting element 6405 Signal line 6406 Scanning line 6407 Power line 6408 Common electrode 7001 TFT
7002 Light emitting element 7003 Electrode layer 7004 EL layer 7005 Electrode layer 7009 Partition wall 7011 Driving TFT
7012 Light emitting element 7013 Electrode layer 7014 EL layer 7015 Electrode layer 7016 Shielding film 7017 Conductive film 7019 Partition wall 7021 Driving TFT
7022 Light emitting element 7023 Electrode layer 7024 EL layer 7025 Electrode layer 7026 Electrode layer 7027 Conductive 7029 Partition 7031 Oxide insulation layer 7032 Protective insulation layer 7033 Color filter layer 7034 Overcoat layer 7035 Protective insulation layer 7041 Oxide insulation layer 7042 Protective insulation layer 7043 Color filter layer 7044 Overcoat layer 7045 Protective insulation layer 7051 Oxide insulation layer 7052 Protective insulation layer 7053 Flattening insulation layer 7055 Protective insulation layer 9600 Television device 9601 Housing 9603 Display 9605 Stand 9607 Display 9609 Operation key 9610 Remote control Operation device 9700 Digital photo frame 9701 Housing 9703 Display 9883 Housing 9882 Display 9883 Display 9884 Speaker 988 Operation key 9886 Recording medium insertion 9878 Connection terminal 9888 Sensor 9888 Microphone 9890 LED lamp 9891 Housing 4503a Signal line drive circuit 4504a Scan line drive circuit

Claims (1)

It has a drive circuit unit including a drive circuit transistor and a pixel unit including a pixel transistor on the same substrate.
The drive circuit transistor and the pixel transistor include a gate electrode layer, a gate insulating layer on the gate electrode layer, an oxide semiconductor layer on the gate insulating layer, a source electrode layer on the oxide semiconductor layer, and the like. It has a drain electrode layer, an oxide semiconductor layer, a source electrode layer, and an oxide insulating layer in contact with a part of the oxide semiconductor layer on the source electrode layer and the drain electrode layer.
In the pixel portion, a color filter layer is provided on the oxide insulating layer, and a first electrode layer, an EL layer, and a second electrode layer that are electrically connected to the pixel transistor are laminated on the color filter layer. ,
In the drive circuit transistor, a conductive layer that overlaps the gate electrode layer and the oxide semiconductor layer is provided on the oxide insulating layer, and the gate electrode layer, the source electrode layer, and the drain electrode layer are metal conductive films. A light emitting device characterized by being.

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