JP2014075581A - 表示装置および電子機器 - Google Patents
表示装置および電子機器 Download PDFInfo
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- JP2014075581A JP2014075581A JP2013187215A JP2013187215A JP2014075581A JP 2014075581 A JP2014075581 A JP 2014075581A JP 2013187215 A JP2013187215 A JP 2013187215A JP 2013187215 A JP2013187215 A JP 2013187215A JP 2014075581 A JP2014075581 A JP 2014075581A
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- oxide layer
- insulating film
- film
- display device
- oxide
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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Abstract
【解決手段】透光性を有する画素電極と電気的に接続されたトランジスタと、容量素子とを有し、トランジスタは、ゲート電極と、ゲート電極上に設けられたゲート絶縁膜と、ゲート絶縁膜上に設けられ酸化物半導体層を含む第1の多層膜とを含み、容量素子は、画素電極と、画素電極と重なりかつ所定の間隔を開けて配置された第1の多層膜と同じ層構造である第2の多層膜と、を有し、トランジスタのチャネル形成領域は、第1の多層膜のうち、ゲート絶縁膜と接しない少なくとも一層である。
【選択図】図3
Description
本実施の形態では、本発明の一態様である表示装置について、図面を用いて説明する。なお、本実施の形態では、液晶素子を用いた表示装置を例にして説明する。
図1(A)に、表示装置の一例を示す。図1(A)に示す表示装置は、画素部100と、走査線駆動回路104と、信号線駆動回路106と、各々が平行または略平行に配置され、かつ走査線駆動回路104によって電位が制御されるm本の走査線107と、各々が平行または略平行に配置され、かつ信号線駆動回路106によって電位が制御されるn本の信号線109と、を有する。さらに、画素部100はマトリクス状に配置された複数の画素101を有する。また、走査線107に沿って、各々が平行または略平行に配置された容量線115を有する。なお、容量線115は、信号線109に沿って、各々が平行または略平行に配置されていてもよい。
本実施の形態では、先の実施の形態1の図3に示す表示装置の第1の基板102上に設けられた素子部の作製方法について、図4および図5を用いて説明する。
まず、第1の基板102に走査線107および容量線115を形成し、走査線107および容量線115を覆うように後にゲート絶縁膜127に加工される絶縁膜126を形成し、絶縁膜126の走査線107と重畳する領域に多層膜111を形成し、後に画素電極121が形成される領域と重畳するように多層膜119を形成する(図4(A)を参照)。
本実施の形態においては、本発明の一態様である表示装置について、実施の形態1に示す構成と異なる構成について、図6乃至図11を用いて説明する。なお、図6乃至図11に示す表示装置においては、液晶層および対向側の第2の基板に形成される素子等については、図3に示す構成と同様であるため、省略して図示している。
まず、図6および図7を用いて表示装置の構成の変形例1について説明を行う。ここでは、図2および図3で説明した容量素子105と異なる容量素子165についてのみ説明する。図6は画素161の上面図であり、図7は図6の一点鎖線C1−C2間、および一点鎖線D1−D2間の断面図である。
次に、図8および図9を用いて表示装置の構成の変形例2について説明を行う。ここでは、図2および図3で説明した容量素子105と異なる容量素子175について説明する。図8は画素171の上面図であり、図9は図8の一点鎖線E1−E2間、および一点鎖線F1−F2間の断面図である。
次に、図10および図11を用いて表示装置の構成の変形例3について説明を行う。ここでは、図8および図9で説明した容量素子175と異なる容量素子185について説明する。図10は画素181の上面図であり、図11は図10の一点鎖線G1−G2間、および一点鎖線H1−H2間の断面図である。
本実施の形態では、上記実施の形態で説明した表示装置に含まれているトランジスタおよび容量素子において、酸化物半導体層を含む多層膜に適用可能な一態様について説明する。
本実施の形態では、上記実施の形態で一例を示した表示装置と、駆動回路の一部または全体を画素部と同じ基板上に一体形成し、システムオンパネルを形成する例について、図12乃至図14を用いて説明する。なお、図13(A)、図13(B)は、図12(B)中でM−Nの一点鎖線で示した部位の断面構成を示す断面図である。なお、図13において、画素部の構造は一部のみ記載している。
本発明の一態様である表示装置は、さまざまな電子機器(遊技機も含む。)に適用することができる。電子機器としては、テレビジョン装置(テレビ、またはテレビジョン受信機ともいう。)、コンピュータ用などのモニタ、デジタルカメラ、デジタルビデオカメラ、デジタルフォトフレーム、携帯電話機、携帯型ゲーム機、携帯情報端末、音響再生装置、遊技機(パチンコ機、スロットマシン等)、ゲーム筐体が挙げられる。これらの電子機器の一例を図15に示す。
101 画素
102 第1の基板
103 トランジスタ
104 走査線駆動回路
105 容量素子
106 信号線駆動回路
107 走査線
108 液晶素子
109 信号線
111 多層膜
111_1 第1の酸化物層
111_2 第2の酸化物層
111_3 第3の酸化物層
113 導電膜
115 容量線
117 開口
119 多層膜
119_1 第1の酸化物層
119_2 第2の酸化物層
119_3 第3の酸化物層
121 画素電極
123 開口
124 画素電極
125 導電膜
126 絶縁膜
127 ゲート絶縁膜
128 絶縁膜
129 絶縁膜
130 絶縁膜
131 絶縁膜
132 絶縁膜
133 絶縁膜
135 導電膜
137 導電膜
138 開口
139 開口
148 導電膜
149 開口
150 第2の基板
152 遮光膜
154 対向電極
155 配線
156 絶縁膜
158 絶縁膜
160 液晶層
161 画素
165 容量素子
167 導電膜
171 画素
175 容量素子
181 画素
185 容量素子
901 第1の基板
902 画素部
903 信号線駆動回路
904 走査線駆動回路
905 シール材
906 第2の基板
908 液晶層
910 トランジスタ
911 トランジスタ
913 液晶素子
915 接続端子電極
916 端子電極
917 導電膜
918 FPC
918b FPC
919 異方性導電剤
922 ゲート絶縁膜
923 絶縁膜
924 絶縁膜
925 シール材
926 容量素子
927 酸化物半導体膜
928 電極
929 容量配線
930 電極
931 電極
932 絶縁膜
933 絶縁膜
935 スペーサ
940 電極
941 電極
943 液晶素子
945 電極
946 共通配線
971 ソース電極
973 ドレイン電極
975 共通電位線
977 共通電極
985 共通電位線
987 共通電極
9000 テーブル
9001 筐体
9002 脚部
9003 表示部
9004 表示ボタン
9005 電源コード
9033 留め具
9034 スイッチ
9035 電源スイッチ
9036 スイッチ
9038 操作スイッチ
9100 テレビジョン装置
9101 筐体
9103 表示部
9105 スタンド
9107 表示部
9109 操作キー
9110 リモコン操作機
9201 本体
9202 筐体
9203 表示部
9204 キーボード
9205 外部接続ポート
9206 ポインティングデバイス
9630 筐体
9631 表示部
9631a 表示部
9631b 表示部
9632a 領域
9632b 領域
9633 太陽電池
9634 充放電制御回路
9635 バッテリー
9636 DCDCコンバータ
9637 コンバータ
9638 操作キー
9639 ボタン
Claims (14)
- 透光性を有する画素電極と電気的に接続されたトランジスタと、容量素子と
を有し、
前記トランジスタは、
ゲート電極と、前記ゲート電極上に設けられたゲート絶縁膜と、
前記ゲート絶縁膜上に設けられ酸化物半導体層を含む第1の多層膜と
を含み、
前記容量素子は、
前記画素電極と、前記画素電極と重なりかつ所定の間隔を開けて配置された前記第1の多層膜と同じ層構造である第2の多層膜と、を有し、
前記トランジスタのチャネル形成領域は、前記第1の多層膜のうち、前記ゲート絶縁膜と接しない少なくとも一層であること
を特徴とする表示装置。 - 前記第1の多層膜は、
前記ゲート絶縁膜上に接する第1の酸化物層と、
前記第1の酸化物層上に接する第2の酸化物層と、
を含むことを特徴とする
請求項1に記載の表示装置。 - 前記第2の酸化物層は、
前記第1の酸化物層よりも電子親和力が0.2eVよりも大きいことを特徴とする
請求項2に記載の表示装置。 - 前記第1の酸化物層は、
アルミニウム、シリコン、チタン、ガリウム、ゲルマニウム、イットリウム、ジルコニウム、スズ、ランタン、セリウムまたはハフニウムを前記第2の酸化物層よりも1.5倍以上高い濃度で含むことを特徴とする
請求項2または請求項3に記載の表示装置。 - 前記第1の酸化物層および前記第2の酸化物層は、In−Ga−Zn酸化物であり、
前記第1の酸化物層がIn:Ga:Zn=x1:y1:z1[原子数比]、前記第2の酸化物層がIn:Ga:Zn=x2:y2:z2[原子数比]のとき、y1/x1がy2/x2よりも1.5倍以上大きいことを特徴とする
請求項2または請求項3に記載の表示装置。 - 前記第2の酸化物層が結晶質構造であり、
前記第1の酸化物層が前記第2の酸化物層より結晶性の低い構造であることを特徴とする
請求項2乃至請求項5のいずれか一に記載の表示装置。 - 前記第1の多層膜は、
前記ゲート絶縁膜上に接する第1の酸化物層と、
前記第1の酸化物層上に接する第2の酸化物層と、
前記第2の酸化物層上に接する第3の酸化物層と、
を含むことを特徴とする
請求項1に記載の表示装置。 - 前記第2の酸化物層は、
前記第1の酸化物層および前記第3の酸化物層よりも電子親和力が0.2eVよりも大きいことを特徴とする
請求項7に記載の表示装置。 - 前記第1の酸化物層および前記第3の酸化物層は、
アルミニウム、シリコン、チタン、ガリウム、ゲルマニウム、イットリウム、ジルコニウム、スズ、ランタン、セリウムまたはハフニウムを前記第2の酸化物層よりも1.5倍以上高い濃度で含むことを特徴とする
請求項7または請求項8に記載の表示装置。 - 前記第1の酸化物層、前記第2の酸化物層および前記第3の酸化物層は、In−Ga−Zn酸化物であり、
前記第1の酸化物層がIn:Ga:Zn=x1:y1:z1[原子数比]、前記第2の酸化物層がIn:Ga:Zn=x2:y2:z2[原子数比]、前記第3の酸化物層がIn:Ga:Zn=x3:y3:z3[原子数比]のとき、y1/x1およびy3/x3がy2/x2よりも1.5倍以上大きいことを特徴とする
請求項7または請求項8に記載の表示装置。 - 前記第2の酸化物層が結晶質構造であり、
前記第1の酸化物層が前記第2の酸化物層より結晶性の低い構造であることを特徴とする
請求項7乃至請求項10のいずれか一に記載の表示装置。 - 前記第3の酸化物層が結晶質構造であることを特徴とする
請求項11に記載の表示装置。 - 前記ゲート電極と同一工程で形成した容量線を有し、
前記第2の多層膜は、前記容量線に電気的に接続される
ことを特徴とする請求項1乃至請求項12のいずれか一に記載の表示装置。 - 請求項1乃至請求項13のいずれか一に記載の表示装置を用いた電子機器。
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US9018624B2 (en) | 2015-04-28 |
US9711537B2 (en) | 2017-07-18 |
JP7340645B2 (ja) | 2023-09-07 |
JP6499336B2 (ja) | 2019-04-10 |
US9368516B2 (en) | 2016-06-14 |
US20140070208A1 (en) | 2014-03-13 |
JP6710301B2 (ja) | 2020-06-17 |
JP2022089843A (ja) | 2022-06-16 |
US20160293640A1 (en) | 2016-10-06 |
JP2019096912A (ja) | 2019-06-20 |
JP2020145469A (ja) | 2020-09-10 |
JP2023164887A (ja) | 2023-11-14 |
JP2018078338A (ja) | 2018-05-17 |
US20150228676A1 (en) | 2015-08-13 |
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