JP2011514015A - バンプレス・ビルド・アップ・レイヤ(bbul)を使用したパッケージオンパッケージ - Google Patents
バンプレス・ビルド・アップ・レイヤ(bbul)を使用したパッケージオンパッケージ Download PDFInfo
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Abstract
Description
Std802.11の補完)に準拠する場合がある。別の実施の形態では、ネットワークコントローラ510は、Ethernet(登録商標)ネットワークインタフェースカードである場合がある。
Claims (24)
- 活性表面、該活性表面に平行な不活性表面及び少なくとも1つの側部を有するマイクロエレクトロニクスダイと、
少なくとも1つの前記マイクロエレクトロニクスダイに隣接するカプセル化材料であって、前記マイクロエレクトロニクスダイの活性表面に対して実質的に平面である下部表面と前記マイクロエレクトロニクスダイの不活性表面に対して実質的に平面である上部表面とを含むカプセル化材料と、
前記上部表面から前記下部表面に延びる前記カプセル化材料における貫通ビアコネクションと、
前記マイクロエレクトロニクスダイの活性表面と前記カプセル化材料の下部表面の少なくとも1部の上に配置される第一の絶縁材料層と、
前記第一の絶縁材料層の上に配置される複数のビルドアップレイヤと、
前記第一の絶縁材料層と前記ビルドアップレイヤの上に配置され、前記マイクロエレクトロニクスダイの活性表面と電気的に接触する複数の導電性の配線と、
を有することを特徴とする装置。 - 前記カプセル化材料における前記貫通ビアコネクションと電気的に接触する前記上部表面の上の第二のマイクロエレクトロニクスダイのパッケージを更に有する、
請求項1記載の装置。 - 前記第二のマイクロエレクトロニクスダイのパッケージと前記マイクロエレクトロニクスダイの前記不活性表面との間の熱拡散器を更に有する、
請求項2記載の装置。 - 前記貫通ビアコネクションは、スルーホールを有する、
請求項2記載の装置。 - 前記マイクロエレクトロニクスダイの活性表面と電気的に接触する前記貫通ビアコネクションを更に有する、
請求項2記載の装置。 - 前記ビルドアップレイヤ上に形成されるバンプと電気的に接触する前記貫通ビアコネクションを更に有する、
請求項2記載の装置。 - ネットワークコントローラと、
システムメモリと、
プロセッサとを有する電子機器であって、
前記プロセッサは、
活性表面、該活性表面に平行な不活性表面及び少なくとも1つの側部を有するマイクロエレクトロニクスダイと、
少なくとも1つの前記マイクロエレクトロニクスダイに隣接するカプセル化材料であって、前記マイクロエレクトロニクスダイの活性表面に対して実質的に平面である下部表面と前記マイクロエレクトロニクスダイの不活性表面に対して実質的に平面である上部表面とを含むカプセル化材料と、
前記上部表面から前記下部表面に延びる前記カプセル化材料における貫通ビアコネクションと、
前記マイクロエレクトロニクスダイの活性表面と前記カプセル化材料の下部表面の少なくとも1部の上に配置される第一の絶縁材料層と、
前記第一の絶縁材料層の上に配置される複数のビルドアップレイヤと、
前記第一の絶縁材料層と前記ビルドアップレイヤの上に配置され、前記マイクロエレクトロニクスダイの活性表面と電気的に接触する複数の導電性の配線と、
を有することを特徴とする電子機器。 - 前記カプセル化材料における前記貫通ビアコネクションと電気的に接触する前記上部表面の上の第二のマイクロエレクトロニクスダイのパッケージを更に有する、
請求項7記載の電子機器。 - 前記第二のマイクロエレクトロニクスダイのパッケージは、システムメモリを有する、
請求項8記載の電子機器。 - 前記第二のマイクロエレクトロニクスダイのパッケージは、チップセットデバイスを有する、
請求項8記載の電子機器。 - 前記第二のマイクロエレクトロニクスダイのパッケージは、バンプレス・ビルド・アップ・レイヤのパッケージを有する、
請求項8記載の電子機器。 - 前記第二のマイクロエレクトロニクスダイのパッケージは、チップスケールのパッケージを有する、
請求項8記載の電子機器。 - 活性表面、該活性表面に平行な不活性表面及び少なくとも1つの側部を有するマイクロエレクトロニクスダイと、
少なくとも1つの前記マイクロエレクトロニクスダイに隣接するコア基板であって、前記マイクロエレクトロニクスダイの活性表面に対して実質的に平面である下部表面と前記マイクロエレクトロニクスダイの不活性表面に対して実質的に平面である上部表面とを含むコア基板と、
前記上部表面から前記下部表面に延びる前記コア基板における貫通ビアコネクションと、
前記マイクロエレクトロニクスダイの活性表面と前記コア基板の下部表面の少なくとも1部の上に配置される第一の絶縁材料層と、
前記第一の絶縁材料層の上に配置される複数のビルドアップレイヤと、
前記第一の絶縁材料層と前記ビルドアップレイヤの上に配置され、前記マイクロエレクトロニクスダイの活性表面と電気的に接触する複数の導電性の配線と、
を有することを特徴とする装置。 - 前記コア基板における前記貫通ビアコネクションと電気的に接触する前記上部表面の上の第二のマイクロエレクトロニクスダイのパッケージを更に有する、
請求項13記載の装置。 - 前記第二のマイクロエレクトロニクスダイのパッケージと前記マイクロエレクトロニクスダイの前記不活性表面との間の熱拡散器を更に有する、
請求項14記載の装置。 - 前記貫通ビアコネクションは、積層されたマイクロビアを有する、
請求項14記載の装置。 - 前記マイクロエレクトロニクスダイの活性表面と電気的に接触する前記貫通ビアコネクションを更に有する、
請求項14記載の装置。 - 前記ビルドアップレイヤ上に形成されるバンプと電気的に接触する前記貫通ビアコネクションを更に有する、
請求項14記載の装置。 - ネットワークコントローラと、
システムメモリと、
プロセッサとを有する電子機器であって、
前記プロセッサは、
活性表面、該活性表面に平行な不活性表面及び少なくとも1つの側部を有するマイクロエレクトロニクスダイと、
少なくとも1つの前記マイクロエレクトロニクスダイに隣接するコア基板であって、前記マイクロエレクトロニクスダイの活性表面に対して実質的に平面である下部表面と前記マイクロエレクトロニクスダイの不活性表面に対して実質的に平面である上部表面とを含むコア基板と、
前記上部表面から前記下部表面に延びる前記コア基板における貫通ビアコネクションと、
前記マイクロエレクトロニクスダイの活性表面と前記コア基板の下部表面の少なくとも1部の上に配置される第一の絶縁材料層と、
前記第一の絶縁材料層の上に配置される複数のビルドアップレイヤと、
前記第一の絶縁材料層と前記ビルドアップレイヤの上に配置され、前記マイクロエレクトロニクスダイの活性表面と電気的に接触する複数の導電性の配線と、
を有することを特徴とする電子機器。 - 前記コア基板における前記貫通ビアコネクションと電気的に接触する前記上部表面の上の第二のマイクロエレクトロニクスダイのパッケージを更に有する、
請求項19記載の電子機器。 - 前記第二のマイクロエレクトロニクスダイのパッケージは、システムメモリを有する、
請求項20記載の電子機器。 - 前記第二のマイクロエレクトロニクスダイのパッケージは、チップセットデバイスを有する、
請求項20記載の電子機器。 - 前記第二のマイクロエレクトロニクスダイのパッケージは、バンプレス・ビルド・アップ・レイヤのパッケージを有する、
請求項20記載の電子機器。 - 前記第二のマイクロエレクトロニクスダイのパッケージは、チップスケールのパッケージを有する、
請求項20記載の電子機器。
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PCT/US2009/045231 WO2009158098A2 (en) | 2008-06-03 | 2009-05-27 | Package on package using a bump-less build up layer (bbul) package |
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Also Published As
Publication number | Publication date |
---|---|
KR101222755B1 (ko) | 2013-01-16 |
KR20100119889A (ko) | 2010-11-11 |
TWI400780B (zh) | 2013-07-01 |
DE112009000383T5 (de) | 2011-04-21 |
CN101981691B (zh) | 2012-12-26 |
US20090294942A1 (en) | 2009-12-03 |
US8093704B2 (en) | 2012-01-10 |
CN101981691A (zh) | 2011-02-23 |
TW201017834A (en) | 2010-05-01 |
DE112009000383B4 (de) | 2020-10-08 |
WO2009158098A2 (en) | 2009-12-30 |
JP5587216B2 (ja) | 2014-09-10 |
WO2009158098A3 (en) | 2010-02-25 |
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