CN101981691B - 使用无凸块内置层(bbul)封装的封装上封装 - Google Patents

使用无凸块内置层(bbul)封装的封装上封装 Download PDF

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CN101981691B
CN101981691B CN2009801108218A CN200980110821A CN101981691B CN 101981691 B CN101981691 B CN 101981691B CN 2009801108218 A CN2009801108218 A CN 2009801108218A CN 200980110821 A CN200980110821 A CN 200980110821A CN 101981691 B CN101981691 B CN 101981691B
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microelectronic core
encapsulation
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active surface
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CN101981691A (zh
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E·C·帕尔默
J·S·居泽尔
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Intel Corp
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Abstract

在一些实施例中，介绍了使用无凸块内置层(BBUL)封装的封装上封装。就此而言，介绍了一种设备，包括：微电子管芯，所述微电子管芯具有有效表面、平行于所述有效表面的无效表面以及至少一个侧面；与所述至少一个微电子管芯的侧面相邻的包封材料，其中所述包封材料包括基本与所述微电子管芯的有效表面共面的底表面和基本与所述微电子管芯的无效表面共面的顶表面；所述包封材料中从所述顶表面延伸到所述底表面的通孔连接；设置于所述微电子管芯的有效表面和所述包封材料表面的至少一部分上的第一电介质材料层；设置于所述第一电介质材料层上的多个内置层；以及设置于所述第一电介质材料层和所述内置层上并与所述微电子管芯的有效表面电接触的多个导电迹线。此外，还公开了其他实施例，并要求保护其权益。

Description

使用无凸块内置层(BBUL)封装的封装上封装
技术领域
本发明的实施例总体涉及集成电路封装设计领域，更具体而言，涉及使用无凸块内置层(BBUL)封装的封装上封装。
背景技术
随着电子器件尺寸的减小和功能性的增加，集成电路器件封装将需要占据更少空间。节省空间的一种方式是在封装顶部上组合封装，不过这样可能会导致异常高的z高度，因为传统地，需要提升顶部封装以使底部封装管芯清晰可见。
附图说明
在附图的图示中通过举例而非限制的方式示出了本发明，在附图中，采用类似的附图标记表示类似的元件，其中：
图1是根据本发明的一个示范性实施例的无凸块内置层封装的截面图的图解说明；
图2是根据本发明的一个示范性实施例的另一无凸块内置层封装的截面图的图解说明；
图3是根据本发明的一个示范性实施例的使用无凸块内置层封装的封装上封装的截面图的图解说明；以及
图4是根据本发明的一个示范性实施例的使用无凸块内置层封装的另一封装上封装的截面图的图解说明；以及
图5是适于实现根据本发明的一个示范性实施例的使用BBUL封装的封装上封装的范例电子设备的方框图。
具体实施方式
在以下描述中，出于解释的目的，阐述了很多具体细节，以便提供对本发明的透彻理解。但是，对于本领域技术人员而言显而易见的是，能够在不需要这些具体的细节的情况下实践本发明的实施例。在其他情况下，通过方框图的形式对结构和器件进行了图示，以避免使本发明变得难以理解。
在整个本说明书中引用的“一个实施例”或“实施例”是指在本发明的至少一个实施例中包含了结合所述实施例描述的特定特征、结构或特性。因而，在整个本说明书的不同位置出现的词组“在一个实施例中”或“在实施例中”未必都是指同一实施例。此外，可以在一个或更多实施例中通过任何适当的方式结合所述特定特征、结构或特性。
图1是根据本发明的一个示范性实施例的无凸块内置层(BBUL)封装的截面图的图解说明。如图所示，集成电路封装100包括一个或多个微电子管芯102、微电子管芯有效表面104、微电子管芯无效表面106、微电子管芯侧面108、包封材料110、第一电介质材料层112、内置层113、导电迹线114、导电触点116、通孔连接118和互连120和122。
微电子管芯102意在代表任何类型的集成电路管芯。在一个实施例中，微电子管芯102为多核微处理器。微电子管芯102包括有效表面104和平行于有效表面104的无效表面106，有效表面104包含操作微电子管芯102所需的电连接。
通过包封材料110在至少一个侧面108上将微电子管芯102固定就位。包封材料110包括至少一个基本与有效表面104共面的表面和一个基本与无效表面106共面的表面。在一个实施例中，有效表面104被置于支撑板上，而包封材料110设置于微电子管芯102周围。在一个实施例中，包封材料110可以在无效表面106上延伸。
第一电介质材料层112设置于有效表面104和包封材料110的至少一部分上。接下来采用公知的处理方法将内置层113设置于第一电介质材料层112上。
导电迹线114设置于第一电介质材料层112和内置层113上并与有效表面104电接触。导电触点116与导电迹线114耦合，允许集成电路封装100例如通过插座连接电耦合到电路板。在一个实施例中，导电触点116包括焊料凸块。在另一实施例中，导电触点116包括焊盘。
通孔连接118代表基本平行于侧面108的穿过包封材料110的导电连接。在一个实施例中，通孔连接118表示通过穿过包封材料110钻孔，然后镀覆并填充而形成的镀覆通孔。互连120和122表示使通孔连接118分别与微电子管芯有效表面104或导电触点116电耦合的导电迹线。
图2是根据本发明的一个示范性实施例的另一无凸块内置层封装的截面图的图解说明。如图所示，集成电路封装200包括一个或多个微电子管芯202、微电子管芯有效表面204、微电子管芯无效表面206、微电子管芯侧面208、包封材料210、封装内核212、第一电介质材料层214、内置层215、导电迹线216、导电触点218、通孔连接220和互连222和224。
微电子管芯202意在代表任何类型的集成电路管芯。在一个实施例中，微电子管芯202为多核微处理器。微电子管芯202包括有效表面204和平行于有效表面204的无效表面206，有效表面包含操作微电子管芯202所需的电连接。
通过封装内核212在至少一个侧面208上将微电子管芯202固定就位。封装内核212包括至少一个基本与有效表面204共面的表面和一个基本与无效表面206共面的表面。在一个实施例中，封装内核212代表多层有机衬底。微电子封装内核212可以具有开口，其中设置有微电子管芯202。在一个实施例中，包封材料210设置于封装内核212和微电子管芯202之间，以提供改善的配合或附着。
第一电介质材料层214设置于有效表面204和包封材料210的至少一部分上。接下来使用公知的处理方法将内置层215设置于第一电介质材料层214上。
导电迹线216设置于第一电介质材料层214和内置层215上并与有效表面204电接触。导电触点218与导电迹线216耦合，允许集成电路封装200例如通过插座连接电耦合到电路板。在一个实施例中，导电触点218包括焊料凸块。在另一实施例中，导电触点218包括焊盘。
通孔连接220表示穿过封装内核212、基本平行于侧面208的导电连接。在一个实施例中，通孔连接220表示作为制造过程的一部分在封装内核212之内形成的一系列叠置的微通孔。互连222和224表示使通孔连接220分别与微电子管芯有效表面204或导电触点218电耦合的导电迹线。
图3是根据本发明的一个示范性实施例的使用无凸块内置层封装的封装上封装的截面图的图解说明。如图所示，封装上封装组件300包括与第二封装304耦合的集成电路封装100。尽管被示为包括两个封装，但可以包括任意数量。与通孔连接118耦合的电触点302将第二封装304与封装100电耦合。可以在封装100和第二封装304之间流入底填材料，例如环氧树脂。可以在封装100和第二封装304之间在无效表面106上包括热扩散器306，以辅助散热。在一个实施例中，第二封装304中的集成电路器件包括存储器件。在一个实施例中，第二封装304中的集成电路器件包括芯片组器件。在一个实施例中，第二封装204表示多器件芯片尺度封装。在一个实施例中，第二封装204表示另一个无凸块内置层封装。在一个实施例中，第二封装204表示传统的倒装片封装。
图4是根据本发明的一个示范性实施例的使用无凸块内置层封装的另一封装上封装的截面图的图解说明。如图所示，封装上封装组件400包括与第二封装404耦合的集成电路封装200。尽管被示为包括两个封装，但可以包括任意数量。与通孔连接220耦合的电触点402使第二封装404与封装200电耦合。可以在封装200和第二封装404之间流入底填材料，例如环氧树脂。可以在封装200和第二封装404之间在无效表面206上包括热扩散器406，以辅助散热。在一个实施例中，第二封装404中的集成电路器件包括存储器件。在一个实施例中，第二封装404中的集成电路器件包括芯片组器件。在一个实施例中，第二封装404表示多器件芯片尺度封装。在一个实施例中，第二封装404表示另一个无凸块内置层封装。在一个实施例中，第二封装404表示传统的倒装片封装。
图5是适于实现根据本发明的一个示范性实施例的集成电路封装的范例电子设备的方框图。电子设备500旨在代表各种各样的常规和非常规电子设备中的任何一种，例如，膝上电脑、台式电脑、蜂窝电话、无线通信用户单元、无线通信电话基础设施元件、个人数字助理、机顶盒或者任何将从本发明的教导中获益的电子设备。根据图示的示范性实施例，电子设备500可以包括如图5所示那样耦合的一个或多个处理器502、存储器控制器504、系统存储器506、输入/输出控制器508、网络控制器510和输入/输出器件512。电子设备500的处理器502或其他集成电路部件可以包括使用前文作为本发明实施例描述的BBUL封装的封装上封装。
处理器502可以代表各种各样的控制逻辑中的任何一种，包括但不限于一个或多个微处理器、可编程逻辑器件(PLD)、可编程逻辑阵列(PLA)、专用集成电路(ASIC)、微控制器等，但是本发明在该方面不受限制。在一个实施例中，处理器502为兼容处理器。处理器502可以具有含有多个可以被(例如)应用程序或操作系统调用的机器级指令的指令组。
存储器控制器504可以代表任何类型的芯片组或控制逻辑，其使系统存储器506与电子设备500的其他部件接口。在一个实施例中，处理器502和存储器控制器504之间的连接可以是点到点串行链路。在另一实施例中，可以将存储器控制器504称为北桥。
系统存储器506可以代表任何类型的存储器件，其用于存储处理器502已经使用的或者将被处理器502使用的数据和指令。典型地，尽管本发明在这一方面不受限制，系统存储器506将由动态随机存取存储器(DRAM)构成。在一个实施例中，系统存储器506可以由Rambus DRAM(RDRAM)构成。在另一实施例中，系统存储器506可以由双数据率同步DRAM(DDRSDRAM)构成。
输入/输出(I/O)控制器508可以代表任何类型的芯片组或控制逻辑，其使I/O器件512与电子设备500的其他部件接口。在一个实施例中，可以将I/O控制器508称为南桥。在另一实施例中，I/O控制器508可以符合2003年4月15日颁布的Peripheral Component Interconnect(PCI)ExpressTM Base Specification，Revision 1.0a，PCI Special InterestGroup。
网络控制器510可以代表任何类型的允许电子设备500与其他电子设备或器件通信的器件。在一个实施例中，网络控制器510可以符合电气和电子工程师学会(IEEE)802.11b标准(1999年9月16日批准，是1999版的ANSI/IEEE标准802.11的增补)。在另一实施例中，网络控制器510可以是以太网网络接口卡。
输入/输出(I/O)器件512可以代表向电子设备500提供输入或者处理来自电子设备500的输出的任何类型的器件、外围设备或部件。
在上述说明中，出于解释的目的，阐述了很多具体的细节，以提供对本发明的透彻的理解。但是，对于本领域技术人员而言显而易见的是，能够在不需要这些具体的细节中的一些细节的情况下实践本发明。在其他情况下，以方框图的形式示出了公知的结构和器件。
很多方法是以其最基本的形式描述的，但是在不背离本发明的基本范围的情况下，可以向所述方法中的任何一个添加操作，或者从其中删除操作，并且可以向所描述的信息中的任何一个添加信息，或者从其中删减信息。可以预计，对本发明构思的任何数量的变型均落在本发明的精神和范围内。就此而言，提供具体说明的示范性实施例的目的并非在于限制本发明，而是对本发明进行举例说明。因而，本发明的范围不由上文提供的具体例子决定，而仅由权利要求的明确语言决定。

Claims (18)

1.一种设备，包括：
微电子管芯，所述微电子管芯具有有效表面、平行于所述有效表而的无效表面以及至少一个侧面；
与所述至少一个微电子管芯的侧面相邻的包封材料，其中所述包封材料包括基本与所述微电子管芯的有效表面共面的底表面和基本与所述微电子管芯的无效表面共面的顶表面；
所述包封材料中从所述顶表面延伸到所述底表面的通孔连接；
设置于所述微电子管芯的有效表面和所述包封材料的底表面的至少一部分上的第一电介质材料层；
设置于所述第一电介质材料层上的多个内置层；设置于所述第一电介质材料层和所述内置层上并与所述微电子管芯的有效表面电接触的多个导电迹线；
所述顶表面上与所述包封材料中的所述通孔连接电接触的第二微电子管芯封装；以及
所述第二微电子管芯封装和所述微电子管芯的所述无效表面之间的热扩散器。
2.根据权利要求1所述的设备，其中，所述通孔连接包括镀覆通孔。
3.根据权利要求1所述的设备，还包括与所述微电子管芯的有效表面电接触的所述通孔连接。
4.根据权利要求1所述的设备，还包括与所述内置层上形成的凸块电接触的所述通孔连接。
5.一种电子设备，包括：
网络控制器；
系统存储器；以及
处理器，其中所述处理器包括：
微电子管芯，所述微电子管芯具有有效表面、平行于所述有效表面的无效表面以及至少一个侧面；
与所述至少一个微电子管芯的侧面相邻的包封材料，其中所述包封材料包括基本与所述微电子管芯的有效表面共面的底表面和基本与所述微电子管芯的无效表面共面的顶表面；
所述包封材料中从所述顶表面延伸到所述底表面的通孔连接；
设置于所述微电子管芯的有效表面和所述包封材料的底表面的至少一部分上的第一电介质材料层；
设置于所述第一电介质材料层上的多个内置层；
设置于所述第一电介质材料层和所述内置层上并与所述微电子管芯的有效表面电接触的多个导电迹线；
所述顶表面上与所述包封材料中的所述通孔连接电接触的第二微电子管芯封装；以及
所述第二微电子管芯封装和所述微电子管芯的所述无效表面之间的热扩散器。
6.根据权利要求5所述的电子设备，其中，所述第二微电子管芯封装包括所述系统存储器。
7.根据权利要求5所述的电子设备，其中，所述第二微电子管芯封装包括芯片组器件。
8.根据权利要求5所述的电子设备，其中所述第二微电子管芯封装包括无凸块内置层封装。
9.根据权利要求5所述的电子设备，其中所述第二微电子管芯封装包括芯片尺度封装。
10.一种设备，包括：
微电子管芯，所述微电子管芯具有有效表面、平行于所述有效表面的无效表面以及至少一个侧面；
与所述至少一个微电子管芯的侧面相邻的衬底内核，其中所述衬底内核包括基本与所述微电子管芯的有效表面共面的底表面和基本与所述微电子管芯的无效表面共面的顶表面；
所述衬底内核中从所述顶表面延伸到所述底表面的通孔连接；
设置于所述微电子管芯的有效表面和所述衬底内核的底表面的至少一部分上的第一电介质材料层；
设置于所述第一电介质材料层上的多个内置层；设置于所述第一电介质材料层和所述内置层上并与所述微电子管芯的有效表面电接触的多个导电迹线；
所述顶表面上与所述衬底内核中的所述通孔连接电接触的第二微电子管芯封装；以及
所述第二微电子管芯封装和所述微电子管芯的所述无效表面之间的热扩散器。
11.根据权利要求10所述的设备，其中所述通孔连接包括叠置的微通孔。
12.根据权利要求10所述的设备，还包括与所述微电子管芯的有效表面电接触的所述通孔连接。
13.根据权利要求10所述的设备，还包括与所述内置层上形成的凸块电接触的所述通孔连接。
14.一种电子设备，包括：
网络控制器；
系统存储器；以及
处理器，其中所述处理器包括：
微电子管芯，所述微电子管芯具有有效表面、平行于所述有效表面的无效表面以及至少一个侧面；
与所述至少一个微电子管芯的侧面相邻的衬底内核，其中所述衬底内核包括基本与所述微电子管芯的有效表面共面的底表面和基本与所述微电子管芯的无效表面共面的顶表面；
所述衬底内核中从所述顶表面延伸到所述底表面的通孔连接；
设置于所述微电子管芯的有效表面和所述衬底内核底表面的至少一部分上的第一电介质材料层；
设置于所述第一电介质材料层上的多个内置层；
设置于所述第一电介质材料层和所述内置层上并与所述微电子管芯的有效表面电接触的多个导电迹线；
所述顶表面上与所述衬底内核中的所述通孔连接电接触的第二微电子管芯封装；以及
所述第二微电子管芯封装和所述微电子管芯的所述无效表面之间的热扩散器。
15.根据权利要求14所述的电子设备，其中所述第二微电子管芯封装包括所述系统存储器。
16.根据权利要求14所述的电子设备，其中所述第二微电子管芯封装包括芯片组器件。
17.根据权利要求14所述的电子设备，其中所述第二微电子管芯封装包括无凸块内置层封装。
18.根据权利要求14所述的电子设备，其中所述第二微电子管芯封装包括芯片尺度封装。
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Families Citing this family (84)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8058101B2 (en) 2005-12-23 2011-11-15 Tessera, Inc. Microelectronic packages and methods therefor
US8035216B2 (en) * 2008-02-22 2011-10-11 Intel Corporation Integrated circuit package and method of manufacturing same
US8093704B2 (en) 2008-06-03 2012-01-10 Intel Corporation Package on package using a bump-less build up layer (BBUL) package
JP5188426B2 (ja) * 2009-03-13 2013-04-24 新光電気工業株式会社 半導体装置及びその製造方法、電子装置
US20110108999A1 (en) * 2009-11-06 2011-05-12 Nalla Ravi K Microelectronic package and method of manufacturing same
US8901724B2 (en) 2009-12-29 2014-12-02 Intel Corporation Semiconductor package with embedded die and its methods of fabrication
US8742561B2 (en) 2009-12-29 2014-06-03 Intel Corporation Recessed and embedded die coreless package
US8535989B2 (en) 2010-04-02 2013-09-17 Intel Corporation Embedded semiconductive chips in reconstituted wafers, and systems containing same
US8319318B2 (en) 2010-04-06 2012-11-27 Intel Corporation Forming metal filled die back-side film for electromagnetic interference shielding with coreless packages
US8618652B2 (en) 2010-04-16 2013-12-31 Intel Corporation Forming functionalized carrier structures with coreless packages
US8939347B2 (en) 2010-04-28 2015-01-27 Intel Corporation Magnetic intermetallic compound interconnect
US9847308B2 (en) 2010-04-28 2017-12-19 Intel Corporation Magnetic intermetallic compound interconnect
US8313958B2 (en) 2010-05-12 2012-11-20 Intel Corporation Magnetic microelectronic device attachment
US8434668B2 (en) 2010-05-12 2013-05-07 Intel Corporation Magnetic attachment structure
US8609532B2 (en) 2010-05-26 2013-12-17 Intel Corporation Magnetically sintered conductive via
US20120001339A1 (en) * 2010-06-30 2012-01-05 Pramod Malatkar Bumpless build-up layer package design with an interposer
US8372666B2 (en) 2010-07-06 2013-02-12 Intel Corporation Misalignment correction for embedded microelectronic die applications
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US8754516B2 (en) 2010-08-26 2014-06-17 Intel Corporation Bumpless build-up layer package with pre-stacked microelectronic devices
US8304913B2 (en) 2010-09-24 2012-11-06 Intel Corporation Methods of forming fully embedded bumpless build-up layer packages and structures formed thereby
KR20120031697A (ko) * 2010-09-27 2012-04-04 삼성전자주식회사 패키지 적층 구조 및 그 제조 방법
US20120139095A1 (en) * 2010-12-03 2012-06-07 Manusharow Mathew J Low-profile microelectronic package, method of manufacturing same, and electronic assembly containing same
US8508037B2 (en) 2010-12-07 2013-08-13 Intel Corporation Bumpless build-up layer and laminated core hybrid structures and methods of assembling same
US8643154B2 (en) * 2011-01-31 2014-02-04 Ibiden Co., Ltd. Semiconductor mounting device having multiple substrates connected via bumps
KR101236798B1 (ko) * 2011-02-16 2013-02-25 앰코 테크놀로지 코리아 주식회사 웨이퍼 레벨 적층형 반도체 패키지 제조 방법
KR101128063B1 (ko) 2011-05-03 2012-04-23 테세라, 인코포레이티드 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리
US8937382B2 (en) 2011-06-27 2015-01-20 Intel Corporation Secondary device integration into coreless microelectronic device packages
US8848380B2 (en) 2011-06-30 2014-09-30 Intel Corporation Bumpless build-up layer package warpage reduction
US9679863B2 (en) * 2011-09-23 2017-06-13 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming interconnect substrate for FO-WLCSP
US8653646B2 (en) 2011-10-03 2014-02-18 Invensas Corporation Stub minimization using duplicate sets of terminals for wirebond assemblies without windows
US8405207B1 (en) 2011-10-03 2013-03-26 Invensas Corporation Stub minimization for wirebond assemblies without windows
US9105483B2 (en) 2011-10-17 2015-08-11 Invensas Corporation Package-on-package assembly with wire bond vias
KR101632249B1 (ko) 2011-10-31 2016-07-01 인텔 코포레이션 멀티 다이 패키지 구조들
US9224674B2 (en) * 2011-12-15 2015-12-29 Intel Corporation Packaged semiconductor die with bumpless die-package interface for bumpless build-up layer (BBUL) packages
US20130157639A1 (en) * 2011-12-16 2013-06-20 SRC Computers, LLC Mobile electronic devices utilizing reconfigurable processing techniques to enable higher speed applications with lowered power consumption
US9601421B2 (en) * 2011-12-30 2017-03-21 Intel Corporation BBUL material integration in-plane with embedded die for warpage control
US9257368B2 (en) 2012-05-14 2016-02-09 Intel Corporation Microelectric package utilizing multiple bumpless build-up structures and through-silicon vias
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
DE112012006469B4 (de) 2012-06-08 2022-05-05 Intel Corporation Mikroelektronisches Gehäuse mit nicht komplanaren gekapselten mikroelektronischen Bauelementen und einer Aufbauschicht ohne Kontaktierhügel
US9200973B2 (en) * 2012-06-28 2015-12-01 Intel Corporation Semiconductor package with air pressure sensor
US8633551B1 (en) * 2012-06-29 2014-01-21 Intel Corporation Semiconductor package with mechanical fuse
US8742597B2 (en) * 2012-06-29 2014-06-03 Intel Corporation Package substrates with multiple dice
US9391008B2 (en) 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US8912670B2 (en) 2012-09-28 2014-12-16 Intel Corporation Bumpless build-up layer package including an integrated heat spreader
US9136236B2 (en) 2012-09-28 2015-09-15 Intel Corporation Localized high density substrate routing
US9496211B2 (en) 2012-11-21 2016-11-15 Intel Corporation Logic die and other components embedded in build-up layers
US9190380B2 (en) 2012-12-06 2015-11-17 Intel Corporation High density substrate routing in BBUL package
US9429427B2 (en) 2012-12-19 2016-08-30 Intel Corporation Inductive inertial sensor architecture and fabrication in packaging build-up layers
US9087765B2 (en) 2013-03-15 2015-07-21 Qualcomm Incorporated System-in-package with interposer pitch adapter
US8669140B1 (en) 2013-04-04 2014-03-11 Freescale Semiconductor, Inc. Method of forming stacked die package using redistributed chip packaging
US8772913B1 (en) 2013-04-04 2014-07-08 Freescale Semiconductor, Inc. Stiffened semiconductor die package
US8980691B2 (en) * 2013-06-28 2015-03-17 Stats Chippac, Ltd. Semiconductor device and method of forming low profile 3D fan-out package
KR102192356B1 (ko) 2013-07-29 2020-12-18 삼성전자주식회사 반도체 패키지
US9478498B2 (en) 2013-08-05 2016-10-25 Taiwan Semiconductor Manufacturing Company, Ltd. Through package via (TPV)
US9167710B2 (en) 2013-08-07 2015-10-20 Invensas Corporation Embedded packaging with preformed vias
US20150076714A1 (en) 2013-09-16 2015-03-19 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US9159690B2 (en) 2013-09-25 2015-10-13 Intel Corporation Tall solders for through-mold interconnect
US9349703B2 (en) 2013-09-25 2016-05-24 Intel Corporation Method for making high density substrate interconnect using inkjet printing
US9583456B2 (en) 2013-11-22 2017-02-28 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
KR102250997B1 (ko) 2014-05-02 2021-05-12 삼성전자주식회사 반도체 패키지
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US9839133B2 (en) 2014-06-04 2017-12-05 Apple Inc. Low-area overhead connectivity solutions to SIP module
US20150359099A1 (en) * 2014-06-04 2015-12-10 Apple Inc. Low area over-head connectivity solutions to sip module
US9502270B2 (en) * 2014-07-08 2016-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device packages, packaging methods, and packaged semiconductor devices
US10624214B2 (en) 2015-02-11 2020-04-14 Apple Inc. Low-profile space-efficient shielding for SIP module
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US10292258B2 (en) 2015-03-26 2019-05-14 Apple Inc. Vertical shielding and interconnect for SIP modules
US9502372B1 (en) 2015-04-30 2016-11-22 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US9490222B1 (en) 2015-10-12 2016-11-08 Invensas Corporation Wire bond wires for interference shielding
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US9911718B2 (en) 2015-11-17 2018-03-06 Invensas Corporation ‘RDL-First’ packaged microelectronic device for a package-on-package device
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US10373884B2 (en) * 2016-03-31 2019-08-06 Samsung Electronics Co., Ltd. Fan-out semiconductor package for packaging semiconductor chip and capacitors
KR102052899B1 (ko) 2016-03-31 2019-12-06 삼성전자주식회사 전자부품 패키지
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
US10638608B2 (en) 2017-09-08 2020-04-28 Apple Inc. Interconnect frames for SIP modules
US10334732B2 (en) 2017-09-22 2019-06-25 Apple Inc. Area-efficient connections to SIP modules
KR101942741B1 (ko) * 2017-10-20 2019-01-28 삼성전기 주식회사 반도체 패키지
KR20220075030A (ko) 2020-11-26 2022-06-07 삼성전자주식회사 반도체 패키지

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1808711A (zh) * 2005-12-09 2006-07-26 威盛电子股份有限公司 封装体及封装体模块
US7332823B2 (en) * 2005-12-15 2008-02-19 Intel Corporation Providing a metal layer in a semiconductor package

Family Cites Families (53)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6271469B1 (en) 1999-11-12 2001-08-07 Intel Corporation Direct build-up layer on an encapsulated die package
JP2001144218A (ja) * 1999-11-17 2001-05-25 Sony Corp 半導体装置及び半導体装置の製造方法
US6154366A (en) * 1999-11-23 2000-11-28 Intel Corporation Structures and processes for fabricating moisture resistant chip-on-flex packages
JP4251421B2 (ja) * 2000-01-13 2009-04-08 新光電気工業株式会社 半導体装置の製造方法
US6586836B1 (en) 2000-03-01 2003-07-01 Intel Corporation Process for forming microelectronic packages and intermediate structures formed therewith
US20020020898A1 (en) * 2000-08-16 2002-02-21 Vu Quat T. Microelectronic substrates with integrated devices
US6734534B1 (en) 2000-08-16 2004-05-11 Intel Corporation Microelectronic substrate with integrated devices
US6586822B1 (en) 2000-09-08 2003-07-01 Intel Corporation Integrated core microelectronic package
DE10044790C1 (de) * 2000-09-11 2002-04-04 Contact Gmbh Isolierkörper für einen Steckverbinder zur Übertragung optischer und elektrischer Signale
US6713859B1 (en) * 2000-09-13 2004-03-30 Intel Corporation Direct build-up layer on an encapsulated die package having a moisture barrier structure
US6489185B1 (en) 2000-09-13 2002-12-03 Intel Corporation Protective film for the fabrication of direct build-up layers on an encapsulated die package
US6617682B1 (en) 2000-09-28 2003-09-09 Intel Corporation Structure for reducing die corner and edge stresses in microelectronic packages
US6709898B1 (en) 2000-10-04 2004-03-23 Intel Corporation Die-in-heat spreader microelectronic package
US6423570B1 (en) 2000-10-18 2002-07-23 Intel Corporation Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby
JP2002158312A (ja) * 2000-11-17 2002-05-31 Oki Electric Ind Co Ltd ３次元実装用半導体パッケージ、その製造方法、および半導体装置
US6555906B2 (en) 2000-12-15 2003-04-29 Intel Corporation Microelectronic package having a bumpless laminated interconnection layer
US6706553B2 (en) 2001-03-26 2004-03-16 Intel Corporation Dispensing process for fabrication of microelectronic packages
JP2002314031A (ja) * 2001-04-13 2002-10-25 Fujitsu Ltd マルチチップモジュール
US6894399B2 (en) 2001-04-30 2005-05-17 Intel Corporation Microelectronic device having signal distribution functionality on an interfacial layer thereof
US6888240B2 (en) 2001-04-30 2005-05-03 Intel Corporation High performance, low cost microelectronic circuit package with interposer
US7071024B2 (en) 2001-05-21 2006-07-04 Intel Corporation Method for packaging a microelectronic device using on-die bond pad expansion
US6586276B2 (en) 2001-07-11 2003-07-01 Intel Corporation Method for fabricating a microelectronic device using wafer-level adhesion layer deposition
US7183658B2 (en) * 2001-09-05 2007-02-27 Intel Corporation Low cost microelectronic circuit package
TW550997B (en) * 2001-10-18 2003-09-01 Matsushita Electric Ind Co Ltd Module with built-in components and the manufacturing method thereof
JP2003163323A (ja) * 2001-11-27 2003-06-06 Sony Corp 回路モジュール及びその製造方法
US20050136640A1 (en) 2002-01-07 2005-06-23 Chuan Hu Die exhibiting an effective coefficient of thermal expansion equivalent to a substrate mounted thereon, and processes of making same
US6841413B2 (en) * 2002-01-07 2005-01-11 Intel Corporation Thinned die integrated circuit package
JP3853219B2 (ja) * 2002-01-18 2006-12-06 イビデン株式会社 半導体素子内蔵基板および多層回路基板
US6680529B2 (en) * 2002-02-15 2004-01-20 Advanced Semiconductor Engineering, Inc. Semiconductor build-up package
JP4489411B2 (ja) * 2003-01-23 2010-06-23 新光電気工業株式会社 電子部品実装構造の製造方法
JP4137659B2 (ja) * 2003-02-13 2008-08-20 新光電気工業株式会社 電子部品実装構造及びその製造方法
US6921975B2 (en) * 2003-04-18 2005-07-26 Freescale Semiconductor, Inc. Circuit device with at least partial packaging, exposed active surface and a voltage reference plane
JP4303563B2 (ja) * 2003-11-12 2009-07-29 大日本印刷株式会社 電子装置および電子装置の製造方法
JP4204989B2 (ja) * 2004-01-30 2009-01-07 新光電気工業株式会社 半導体装置及びその製造方法
JP3925809B2 (ja) * 2004-03-31 2007-06-06 カシオ計算機株式会社 半導体装置およびその製造方法
TWI237883B (en) * 2004-05-11 2005-08-11 Via Tech Inc Chip embedded package structure and process thereof
TWI263313B (en) * 2005-08-15 2006-10-01 Phoenix Prec Technology Corp Stack structure of semiconductor component embedded in supporting board
TWI295497B (en) * 2005-10-18 2008-04-01 Phoenix Prec Technology Corp Stack structure of semiconductor component embedded in supporting board and method for fabricating the same
JP2007123524A (ja) * 2005-10-27 2007-05-17 Shinko Electric Ind Co Ltd 電子部品内蔵基板
US7279795B2 (en) * 2005-12-29 2007-10-09 Intel Corporation Stacked die semiconductor package
JP2007201254A (ja) * 2006-01-27 2007-08-09 Ibiden Co Ltd 半導体素子内蔵基板、半導体素子内蔵型多層回路基板
JP5032205B2 (ja) * 2006-05-30 2012-09-26 三菱樹脂株式会社 キャビティー部を有する多層配線基板
TWI300978B (en) * 2006-08-07 2008-09-11 Phoenix Prec Technology Corp A plate having a chip embedded therein and the manufacturing method of the same
JP5267987B2 (ja) * 2006-11-06 2013-08-21 日本電気株式会社 半導体装置およびその製造方法
US8193034B2 (en) * 2006-11-10 2012-06-05 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect structure using stud bumps
KR100813625B1 (ko) * 2006-11-15 2008-03-14 삼성전자주식회사 반도체 소자 패키지
US7504283B2 (en) * 2006-12-18 2009-03-17 Texas Instruments Incorporated Stacked-flip-assembled semiconductor chips embedded in thin hybrid substrate
US20090072382A1 (en) 2007-09-18 2009-03-19 Guzek John S Microelectronic package and method of forming same
US20090079064A1 (en) 2007-09-25 2009-03-26 Jiamiao Tang Methods of forming a thin tim coreless high density bump-less package and structures formed thereby
US20090127686A1 (en) * 2007-11-21 2009-05-21 Advanced Chip Engineering Technology Inc. Stacking die package structure for semiconductor devices and method of the same
US20090170241A1 (en) * 2007-12-26 2009-07-02 Stats Chippac, Ltd. Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier
US8093704B2 (en) 2008-06-03 2012-01-10 Intel Corporation Package on package using a bump-less build up layer (BBUL) package
JP5193898B2 (ja) * 2009-02-12 2013-05-08 新光電気工業株式会社 半導体装置及び電子装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1808711A (zh) * 2005-12-09 2006-07-26 威盛电子股份有限公司 封装体及封装体模块
US7332823B2 (en) * 2005-12-15 2008-02-19 Intel Corporation Providing a metal layer in a semiconductor package

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