WO2022068467A1 - 封装结构、装置、板卡及布局集成电路的方法 - Google Patents

封装结构、装置、板卡及布局集成电路的方法 Download PDF

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Publication number
WO2022068467A1
WO2022068467A1 PCT/CN2021/114097 CN2021114097W WO2022068467A1 WO 2022068467 A1 WO2022068467 A1 WO 2022068467A1 CN 2021114097 W CN2021114097 W CN 2021114097W WO 2022068467 A1 WO2022068467 A1 WO 2022068467A1
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wafer
region
capacitors
package structure
chip
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PCT/CN2021/114097
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English (en)
French (fr)
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陈帅
邱志威
张峻玮
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中科寒武纪科技股份有限公司
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Priority to KR1020217042291A priority Critical patent/KR102629195B1/ko
Publication of WO2022068467A1 publication Critical patent/WO2022068467A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2113/00—Details relating to the application field
    • G06F2113/18—Chip packaging
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10152—Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body

Definitions

  • This disclosure generally relates to semiconductors. More particularly, the present disclosure relates to package structures, integrated circuit devices, boards, and methods of laying out integrated circuits on wafers of package structures.
  • CoWoS chip on wafer on substrate
  • the chip is connected to the silicon wafer through the CoW (chip on wafer) packaging process, and then the CoW chip is connected to the substrate (substrate) to integrate into CoWoS.
  • the substrate substrate
  • CoW chip on wafer
  • the power supply of CoWoS is provided by capacitor storage.
  • a common application is to package multiple chips with different functions in CoWoS, but when multiple capacitors are configured, the chip area is often increased, resulting in increased cost. Therefore, a solution to save area to accommodate capacitors is urgently needed. of.
  • the solutions of the present disclosure provide a package structure, an integrated circuit device, a board card, and a method for laying out an integrated circuit on a wafer of the package structure.
  • the present disclosure discloses a method of laying out integrated circuits on a wafer in a package structure, comprising: chip attaching a system on a chip in a system area on the wafer; chip attaching memory in a storage area on the wafer ; and chip-mounting a plurality of capacitors in capacitor regions on the wafer.
  • the capacitance region is a deformed zero region other than the system region and the storage region.
  • the present disclosure discloses a package structure including a system-on-chip, a memory, and a plurality of capacitors.
  • the system-on-chip is arranged in the system area on the wafer; the memory is arranged in the storage area on the wafer; a plurality of capacitors are arranged in the capacitance area on the wafer.
  • the capacitance region is the abnormal zero region other than the system region and the storage region.
  • the present disclosure discloses an integrated circuit device including the aforementioned package structure; and also discloses a board including the aforementioned integrated circuit device.
  • the layout of the capacitor is appropriately planned to save the area, which not only improves the capacitance value, but also saves the manufacturing cost.
  • FIG. 1 is a structural diagram illustrating a board according to an embodiment of the present disclosure
  • FIG. 2 is a block diagram illustrating an integrated circuit device of an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram showing the internal structure of a computing device according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram showing the internal structure of a processor core according to an embodiment of the present disclosure
  • FIG. 5 is a schematic layout diagram illustrating a packaging structure according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic layout diagram illustrating another packaging structure according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic layout diagram illustrating another packaging structure according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic layout diagram illustrating another packaging structure according to an embodiment of the present disclosure.
  • FIG. 9 is a diagram illustrating various spacing constraints associated with capacitors in embodiments of the present disclosure.
  • FIG. 10 is a flow diagram illustrating the layout of integrated circuits on a wafer according to another embodiment of the present disclosure.
  • FIG. 11 is a cross-sectional view illustrating a packaging process structure of CoW according to an embodiment of the present disclosure
  • FIG. 12 is a cross-sectional view illustrating a packaging process structure of CoWoS according to an embodiment of the present disclosure
  • Figure 13 is a flow chart illustrating the fabrication of a CoWoS structure on a wafer according to another embodiment of the present disclosure
  • FIG. 14A is a cross-sectional view of a package structure corresponding to each step of another embodiment of the present disclosure.
  • 14B is a cross-sectional view of a package structure corresponding to each step of another embodiment of the present disclosure.
  • FIG. 15A is a cross-sectional view of a package structure corresponding to each step of another embodiment of the present disclosure.
  • 15B is a cross-sectional view of a package structure corresponding to each step of another embodiment of the present disclosure.
  • 15C is a cross-sectional view of a package structure corresponding to each step of another embodiment of the present disclosure.
  • the term “if” may be contextually interpreted as “when” or “once” or “in response to determining” or “in response to detecting”.
  • the wafer is a circular sheet composed of pure silicon, which is generally divided into 6 inches, 8 inches, 12 inches and other specifications.
  • the wafer will be cut into One by one, this small piece is called a die.
  • Chips are attached to each wafer and wiring is arranged to perform specific electrical functions. Then, the chip is packaged into a particle.
  • the purpose of the package is to place, fix, seal, protect the chip and enhance the electrical and thermal performance.
  • the contacts of the chip are connected to the pins of the package shell with wires. The structure is complete.
  • One embodiment of the present disclosure is a CoWoS package structure formed on a wafer.
  • the chip mainly includes a memory and a system-on-chip, but the present disclosure is not limited to packaging only the aforementioned components.
  • the memory is used to temporarily store the operation data required by the on-chip system and the data exchanged with the external memory.
  • the memory may be a high bandwidth memory (HBM), which is a high-performance DRAM based on a 3D stacking process, suitable for applications requiring high memory bandwidth, such as graphics processors, Online switching and forwarding equipment (such as routers, switches), etc.
  • HBM high bandwidth memory
  • FIG. 1 shows a schematic structural diagram of a board 10 according to an embodiment of the present disclosure.
  • the board 10 includes a combined processing device 101, which is an artificial intelligence computing unit to support various deep learning and machine learning algorithms, and meet the requirements of computer vision, speech, natural language processing, data mining and other fields Intelligent processing requirements in complex scenarios.
  • a combined processing device 101 which is an artificial intelligence computing unit to support various deep learning and machine learning algorithms, and meet the requirements of computer vision, speech, natural language processing, data mining and other fields Intelligent processing requirements in complex scenarios.
  • deep learning technology is widely used in the field of cloud intelligence.
  • a notable feature of cloud intelligence applications is the large amount of input data, which has high requirements on the storage capacity and computing capacity of the platform.
  • the board 10 in this embodiment is suitable for cloud intelligence applications. applications, with huge off-chip storage, on-chip storage and massive computing power.
  • the combined processing device 101 is connected to the external device 103 through the external interface device 102 .
  • the external device 103 is, for example, a server, a computer, a camera, a monitor, a mouse, a keyboard, a network card or a wifi interface, and the like.
  • the data to be processed can be transmitted by the external device 103 to the combined processing device 101 through the external interface device 102 .
  • the calculation result of the combination processing device 101 can be transmitted back to the external device 103 via the external interface device 102 .
  • the external interface device 102 may have different interface forms, such as a PCIe interface and the like.
  • the board 10 also includes an external memory 104 for storing data, which includes one or more storage units 105 .
  • the external memory 104 is connected to the control device 106 and the combined processing device 101 through a bus and performs data transmission.
  • the control device 106 in the board 10 is configured to regulate the state of the combined processing device 101 .
  • the control device 106 may include a microcontroller (Micro Controller Unit, MCU).
  • FIG. 2 is a schematic diagram showing the combined processing apparatus 101 of this embodiment.
  • the combined processing device 101 includes a computing device 201 , an interface device 202 , a processing device 203 and a DRAM 204 .
  • the computing device 201 , the interface device 202 , and the processing device 203 are integrated into the aforementioned system-on-chip.
  • the computing device 201 itself is the aforementioned system-on-chip.
  • the computing device 201 is configured to perform operations specified by the user, and is mainly implemented as a single-core intelligent processor or a multi-core intelligent processor to perform deep learning or machine learning calculations, which can interact with the processing device 203 through the interface device 202 to Work together to complete a user-specified operation.
  • the interface device 202 is used to transmit data and control instructions between the computing device 201 and the processing device 203 .
  • the computing device 201 may obtain input data from the processing device 203 via the interface device 202 and write the input data into the storage device on-chip of the computing device 201 .
  • the computing device 201 can obtain the control instruction from the processing device 203 via the interface device 202 and write it into the control cache on the computing device 201 .
  • the interface device 202 can also read the data in the storage device of the computing device 201 and transmit it to the processing device 203 .
  • the processing device 203 performs basic control including but not limited to data transfer, starting and/or stopping the computing device 201, and the like.
  • the processing device 203 may be a central processing unit, a graphics processing unit, or one or more types of general-purpose and/or special-purpose processors, including but not limited to digital signal processors (digital signal processor, DSP), application specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc., and the number can be determined according to actual needs.
  • DSP digital signal processor
  • ASIC application specific integrated circuit
  • FPGA field-programmable gate array
  • the computing device 201 of the present disclosure can be regarded as having a single-core structure or a homogeneous multi-core structure. However, when the computing device 201 and the processing device 203 are considered together, the two are considered to form a heterogeneous multi-core structure.
  • the DRAM 204 is the aforementioned high-bandwidth memory, which is used to store the data to be processed, and the size is usually 16G or larger, and is used to save the data of the computing device 201 and/or the processing device 203.
  • FIG. 3 shows a schematic diagram of the internal structure of the computing device 201 .
  • the computing device 201 is used to process input data such as computer vision, speech, natural language, data mining, etc.
  • the computing device 201 in the figure is designed with a multi-core hierarchical structure, which includes an external memory controller 301, a peripheral communication module 302, and an on-chip interconnect module. 303 , a synchronization module 304 and multiple clusters 305 .
  • the peripheral communication module 302 is used for receiving a control signal from the processing device 203 through the interface device 202 to start the computing device 201 to perform tasks.
  • the on-chip interconnection module 303 connects the external storage controller 301 , the peripheral communication module 302 and the multiple clusters 305 to transmit data and control signals among the modules.
  • the synchronization module 304 is a global synchronization barrier controller (GBC), which is used to coordinate the work progress of each cluster and ensure the synchronization of information.
  • GBC global synchronization barrier controller
  • the plurality of clusters 305 are the computing cores of the computing device 201, and 4 are exemplarily shown in the figure. With the development of hardware, the computing device 201 of the present disclosure may also include 8, 16, 64, or even more. Cluster 305. Cluster 305 is used to efficiently execute deep learning algorithms.
  • Each cluster 305 includes a plurality of processor cores (IPU cores) 306 and a memory core (MEM core) 307 .
  • processor cores IPU cores
  • MEM core memory core
  • the processor cores 306 are exemplarily shown as four in the figure, and the present disclosure does not limit the number of the processor cores 306 . Its internal structure is shown in Figure 4. Each processor core 306 includes three modules: a control module 41 , an arithmetic module 42 and a storage module 43 .
  • the control module 41 is used to coordinate and control the work of the arithmetic module 42 and the storage module 43 to complete the task of deep learning, and it includes an instruction fetch unit (instruction fetch unit, IFU) 411 and an instruction decoding unit (instruction Decode unit, IDU) 412.
  • the instruction fetching unit 411 is used to acquire the instruction from the processing device 203 , and the instruction decoding unit 412 decodes the acquired instruction, and sends the decoding result to the operation module 42 and the storage module 43 as control information.
  • the operation module 42 includes a vector operation unit 421 and a matrix operation unit 422 .
  • the vector operation unit 421 is used to perform vector operations, and can support complex operations such as vector multiplication, addition, and nonlinear transformation;
  • the matrix operation unit 422 is responsible for the core calculation of the deep learning algorithm, that is, matrix multiplication and convolution.
  • the storage module 43 is used to store or transport related data, including a neuron storage unit (neuron RAM, NRAM) 431, a weight storage unit (weight RAM, WRAM) 432, an input/output direct memory access module (input/output direct memory access , IODMA) 433, move direct memory access module (move direct memory access, MVDMA) 434.
  • the NRAM 431 is used to store the input, output data and intermediate results calculated by the processor core 306;
  • the WRAM 432 is used to store the weights of the deep learning network;
  • the MVDMA 434 is used to control the memory access of the NRAM 431/WRAM 432 and the SRAM 308.
  • the storage core 307 is mainly used for storage and communication, that is, to store the shared data or intermediate results between the processor cores 306, and to execute the communication between the cluster 305 and the DRAM 204, the communication between the clusters 305, and the processor Communication among the cores 306, etc.
  • the memory core 307 has scalar operation capability for performing scalar operations.
  • the storage core 307 includes a shared storage unit (SRAM) 308, a broadcast bus 309, a cluster direct memory access (CDMA) 310 and a global direct memory access (GDMA) 311.
  • SRAM shared storage unit
  • CDMA cluster direct memory access
  • GDMA global direct memory access
  • the SRAM 308 assumes the role of a high-performance data transfer station.
  • the data multiplexed between different processor cores 306 in the same cluster 305 does not need to be obtained from the DRAM 204 through the processor cores 306, but is stored in the processor through the SRAM 308.
  • the storage core 307 only needs to quickly distribute the multiplexed data from the SRAM 308 to the multiple processor cores 306, so as to improve the communication efficiency between the cores and greatly reduce the on-chip and off-chip input/output accesses.
  • the broadcast bus 309, the CDMA 310 and the GDMA 311 are used to perform the communication between the processor cores 306, the communication between the clusters 305 and the data transmission between the clusters 305 and the DRAM 204, respectively. They will be explained separately below.
  • the broadcast bus 309 is used to complete high-speed communication among the processor cores 306 in the cluster 305.
  • the broadcast bus 309 in this embodiment supports inter-core communication methods including unicast, multicast and broadcast.
  • Unicast refers to point-to-point (ie, a single processor core to a single processor core) data transmission
  • multicast is a communication method that transmits a piece of data from SRAM 308 to specific processor cores 306, and broadcast is a communication method.
  • the communication method in which copies of data are transmitted from SRAM 308 to all processor cores 306 is a special case of multicast.
  • the CDMA 310 is used to control access to the SRAM 308 between different clusters 305 within the same computing device 201.
  • the GDMA 311 cooperates with the external memory controller 301 to control the memory access from the SRAM 308 of the cluster 305 to the DRAM 204, or to read data from the DRAM 204 to the SRAM 308.
  • FIG. 5 shows a schematic layout of a package structure of this embodiment.
  • the layout of the package structure is located in a molding compound area 50 of the wafer.
  • the molding compound area 50 includes a system area 51 and two storage areas 52, wherein The system area 51 is located in the center of the molding compound area 50 , and the storage areas 52 are located on both sides of the system area 51 , respectively.
  • the chip of the package structure includes a system-on-chip 501 and a plurality of memories 502, wherein the system-on-chip 501 is the aforementioned system-on-chip, which may only include the computing device 201 or include the computing device 201, the interface device 202, and the processing device 203.
  • the system-on-chip 501 is provided in the The system area 51 and the memory 502 are DRAMs 204. In this embodiment, there are a total of 6, which are arranged in the storage area 52 on average, and the storage area 52 on each side is provided with three memories 502.
  • the distorted zero area refers to the idle area other than the system area 51 and the storage area 52 in the molding compound area 50.
  • This embodiment The capacitors required for the CoWoS structure are placed in these null regions. As shown in FIG. 5 , in this chip layout, there are distorted regions on the top and bottom sides of the system area 51 , and the capacitors are arranged in these distorted regions.
  • the chip of the package structure further includes a plurality of capacitors 503, and the molding compound region 50 includes two capacitor regions 53, which are respectively located in the distorted zero region of the molding compound region 50, that is, the top side and the bottom side of the system region 51. These capacitors 503 are evenly distributed in the capacitor region 53 to make full use of the area of the molding compound region 50 .
  • the wafer also includes non-molding compound regions 54 on the top and bottom sides of the molding compound regions 50 for accommodating more capacitors.
  • This embodiment does not limit the position of the non-molding compound region 54 , basically, the surrounding area of the molding compound region 50 can be used as the non-molding compound region 54 , and its size depends on the number and size of the capacitors.
  • the capacitors are preferably arranged in the distorted zero region in the molding compound region 50, and if the space is insufficient, the capacitors are then considered to be arranged in the non-molding compound region 54.
  • This embodiment does not limit the specification of the capacitor. According to the specific requirements of the chip, any suitable capacitor on the market can be used, such as but not limited to the capacitor with the model GRM2165C1H333GA01 produced by Murata.
  • FIG. 6 shows a schematic layout of another package structure of this embodiment.
  • the molding compound region 50 includes four capacitor regions 53 , which are respectively located at four corners of the molding compound region 50 . These capacitors 503 are evenly distributed in the capacitance region 53 to make full use of the area of the molding compound region 50 . .
  • FIG. 7 shows a schematic layout diagram of another package structure of this embodiment.
  • the difference from the aforementioned layout is that four memories 502 are set at four corners of the molding compound area 50 , and the zero-distortion area appears between the two storage areas 52 on both sides of the system area 51 . Therefore, the molding compound region 50 includes two capacitor regions 53, which are located between the two storage regions 52 on both sides of the system region 51. These capacitors 503 are evenly distributed in the capacitor region 53 to make full use of the area of the molding compound region 50. .
  • FIG. 8 shows a schematic layout diagram of another package structure of this embodiment.
  • the difference from the previous layout is that the system area 51 is provided with two SoCs 501.
  • the zero-distortion area appears on the top and bottom sides of the system area 51, so the capacitors 503 are arranged in these areas. in the distorted zero area.
  • the capacitance area is located in the distorted zero area of the molding compound area 50, which may be between the system area 51 and the wafer edge, between the system area 51 and the storage area 52, between the storage area 52 and the wafer edge, between the storage area 52 and the storage area 52 rooms.
  • Figure 9 shows the various spacing constraints associated with capacitors in this embodiment.
  • the distance d1 between the capacitor 503 and the system area 51 needs to be greater than 0.5 mm
  • the distance d2 between the capacitor 503 and the storage area 52 needs to be greater than 1 mm
  • the distance d3 between the capacitor 503 and the wafer edge needs to be greater than 0.5 mm
  • the distance d 4 between the capacitors 503 needs to be greater than 0.5 mm.
  • moldless area 54 is not shown in the chip layouts of FIGS. 6-8, it does not mean that these chip layouts do not require the moldless area 54 to accommodate more capacitors. Based on the description of FIG. 5 , those skilled in the art can easily understand that in various chip layouts, non-molding compound regions 54 can be arranged around the molding compound region 50 to accommodate capacitors, so the description is omitted.
  • chips of the present disclosure may also include various integrated circuits, such as various passive and active microelectronic devices such as resistors, other capacitor types (eg, MIMCAP), inductors, diodes, Metal-oxide-semiconductor field-effect transistor (MOSFET), complementary metal-oxide-semiconductor (CMOS) transistor, bipolar junction transistor (BJT), laterally diffused metal-oxide-semiconductor (LDMOS) transistor, high-power metal-oxide-semiconductor transistor, or other types transistors, etc.
  • MIMCAP Metal-oxide-semiconductor field-effect transistor
  • CMOS complementary metal-oxide-semiconductor
  • BJT bipolar junction transistor
  • LDMOS laterally diffused metal-oxide-semiconductor
  • LDMOS laterally diffused metal-oxide-semiconductor
  • the distorted zero area other than the system area and the storage area is used as the capacitor area, which is used to lay out the capacitors required by the chip, so as to reduce the area of the chip.
  • the circle can accommodate more wafers, thereby achieving the technical effect of reducing manufacturing costs.
  • Another embodiment of the present disclosure is a method of laying out integrated circuits on a wafer, the flowchart of which is shown in FIG. 10 .
  • a system-on-a-chip is chip-attached in a system area on a wafer.
  • the chip layout is located in the molding compound area of the wafer, the molding compound area includes the system area and the storage area, and the chip of the package structure includes the SoC and the memory.
  • the chip mounting technology is used to set the SoC in the system area. .
  • An exemplary die attach technique is controlled collapse chip connection (C4).
  • the controllable collapse chip connection is to use high temperature solder, flux or solder paste to apply tinned electrodes on the substrate or transfer to the solder balls of the chip, and then place the chip on the substrate, and heat and reflow during the mounting process. Or batch reflow in a standard reflow oven.
  • step 1002 memory is chip mounted in a storage area on the wafer.
  • the memory of this embodiment may be a high-bandwidth memory, and the high-bandwidth memory is a stack of multiple layers of DRAM, and finally mounted in the storage area.
  • the high-bandwidth memory does not need such a high frequency on the basis of providing a relatively large video memory bit width.
  • the same 4GB capacity high-bandwidth memory can provide a video memory bit width of 4096 bits, compared to GDDR5 is several times higher.
  • the advent of high-bandwidth memory has expanded the layout of chips from 2D to 3D, helping to reduce die area.
  • a plurality of capacitors are die mounted in the capacitor area on the wafer.
  • the capacitance region of this embodiment is the distorted zero region other than the system region and the storage region.
  • the capacitors required by the CoWoS structure are arranged in these distorted zero regions, so as to make full use of the area of the molding compound region 50, thereby reducing the chip area.
  • the capacitive regions of this embodiment may be located between the system region and the wafer edge, between the system region and the storage region, between the storage region and the wafer edge, and between the storage region and the storage region. The limitation of the spacing related to the capacitors is shown in FIG. 9 and will not be repeated here.
  • FIG. 11 shows a cross-sectional view of the packaging process structure of the CoW of the foregoing embodiment.
  • the structure first generates a plurality of through silicon vias (TSVs) 1102 on the wafer 1101 , and the TSV technology is a high-density packaging technology.
  • TSVs through silicon vias
  • the TSV technology is a high-density packaging technology.
  • This technology reduces interconnection length through vertical interconnection, reduces signal delay and unnecessary capacitance/inductance, realizes low power consumption between chips, high-speed communication, increases bandwidth and realizes miniaturization of device integration.
  • micro bumps 1103 are formed to bond the chip 1104, the capacitor 1105 and the wafer 1101 together.
  • the chip 1104 in the figure exemplarily includes the aforementioned system-on-chip and a plurality of memories.
  • the CoWoS is based on the CoW process shown in FIG. 11 and then connected to the substrate.
  • FIG. 12 shows the packaging process structure of CoWoS. First, the chip 1104 is filled with underfill, then solder balls 1201 are placed, and bonded on the substrate (such as a printed circuit board) 1202, and finally The upper package 1203 is completed.
  • a plurality of capacitors are formed on the wafer 1101 to supply power to the chip.
  • large capacitance values are urgently needed.
  • the present disclosure proposes a method to provide a large capacitance value by arranging a capacitor in the abnormal zero region in the CoWoS process.
  • FIG. 13 Another embodiment of the present disclosure is a method of fabricating a CoWoS structure on a wafer, that is, first fabricating the CoW structure shown in FIG. 11 , and then fabricating the CoWoS structure shown in FIG. 12 .
  • the method of this embodiment is shown in FIG. 13 , and FIG. 14 and FIG. 15 are cross-sectional views of the package structure corresponding to each step of this embodiment.
  • this embodiment utilizes TSVs to form multiple redistribution layers on the first side of the wafer.
  • a plurality of TSV layers are formed on the first side of the wafer 1401 (ie, the wafer 1101) by means of photomask etching.
  • the first TSV layer 1402 is exemplarily shown with the The second through silicon via layer 1403 .
  • the thickness of the wafer 1401 is 775 microns
  • the depth of the TSV layer is 107 microns.
  • step 1302 a thermal wet oxidation process is used on the first side surface to generate water vapor, which chemically reacts with the silicon material of the wafer to generate a first dielectric layer 1404 on the first side surface.
  • the composition of the first dielectric layer 1404 is silicon nitride.
  • conductive layer 1409 is electroplated.
  • the material of the conductive layer 1409 is copper.
  • structures 142 are formed on the first side of wafer 1401 .
  • a plurality of redistribution layers 1405 are deposited.
  • CMP chemical mechanical polishing
  • the function of the redistribution layer 1405 is to electrically connect the TSV layer and the chip contacts. According to the actual requirements of the chip contact connection, these redistribution layers 1405 need to be specially planned so that the contacts can be electrically connected to the appropriate TSVs correctly. layer. Only a 2-layer redistribution redistribution layer 1405 is shown by way of example in FIG. 14A, with a dielectric deposited therebetween. After this step is completed, structures 143 are formed on the first side of wafer 1401 .
  • step 1305 a second dielectric layer 1406 is deposited. Through the mask layout, shielding is performed above the exit of each TSV layer, so that the redistribution layer 1405 above the exit of each TSV layer is exposed and not shielded by the second dielectric layer 1406 . After this step is complete, structures 144 are formed on the first side of wafer 1401.
  • a plurality of first wafer bumps are formed on the plurality of redistribution layers 1405 .
  • a C4 process is used to form a first wafer bump on each TSV layer, so that the first wafer bump is electrically connected to the TSV layer through the redistribution layer 1405 .
  • structures 145 are formed on the first side of wafer 1401.
  • the drawing exemplarily shows two first wafer bumps: a first wafer bump 1407 and a first wafer bump 1408, the first wafer bump 1407 is electrically connected to the first silicon via through the redistribution layer 1405
  • the via layer 1402 and the first wafer bumps 1408 are electrically connected to the second TSV layer 1403 through the redistribution layer 1405 .
  • the distance D1 between the two first wafer bumps is 60 micrometers, and the center-to-center distance D2 is 130, 150 or 180 micrometers.
  • step 1307 is performed to bond the plurality of first wafer bumps to the SoC and the memory.
  • the structure 151 shown in FIG. 15A is formed on the first side of the wafer 1401, wherein the chip 1501 includes the aforementioned system-on-chip and memory.
  • step 1308 underfill is filled in the system area and the storage area. Underfill materials can improve the impact of humidity protection, thermal shock and various mechanical shocks, its function is to provide higher reliability and longer life cycle.
  • the structure 152 shown in FIG. 15A is formed on the first side of the chip 1401, wherein the underfill 1502 protects the contacts of the chip 1501 and the first wafer bumps.
  • step 1309 a plurality of first wafer bumps and capacitors are bonded.
  • a structure 153 as shown in FIG. 15A is formed on the first side of the wafer 1401.
  • the structure 153 exemplarily shows 2 capacitors 1503 bonded on a plurality of first wafer bumps. These capacitors 1503 are It is set on the capacitance area, that is, the distortion zero area outside the system area and the storage area.
  • step 1310 the SoC, memory and multiple capacitors are molded to form a CoW structure. That is, the chip 1501 and the capacitor 1503 are encapsulated, and the structure 154 shown in FIG. 15B is formed on the first side of the wafer 1401, wherein the encapsulation plastic 1504 wraps the chip 1501 and the capacitor 1503 for placement, fixing, sealing and protection. And enhance the role of electrothermal performance. So far, the CoW structure of FIG. 11 has been realized.
  • the CoW structure is glass bonded.
  • the entire CoW structure is turned over so that the first side is facing down, and then the encapsulating plastic 1504 and the glass 1505 are bonded by mechanical or chemical methods to form a laminate.
  • the bonding methods that can be used are: anodic bonding method , Adhesive interlayer method, silicon (or glass) surface coating bonding method, etc.
  • a structure 155 is formed on the first side of the wafer 1401 as shown in FIG. 15B.
  • step 1312 the wafer is polished so that the surface of the other side of the TSV is flush with the surface of the second side of the wafer.
  • the surface of the second side of the wafer 1401 is polished by chemical mechanical polishing, and the surfaces of all the TSVs 1506 are flush with the second side surface, that is, the TSVs The surface of the hole 1506 is exposed on the second side.
  • a plurality of second wafer bumps are formed on the second side to connect the other side of the TSV.
  • a second wafer bump 1507 is formed at the opening of each through silicon via 1506 on the second side using a C4 process.
  • step 1314 the second wafer bumps are soldered to the substrate.
  • the second wafer bumps 1507 are soldered to the substrate 1508 .
  • the distance between the two second wafer bumps 1507 is 60 microns, and the center-to-center distance is 130, 150 or 180 microns. So far, the CoWoS package structure of FIG. 12 is completed.
  • this embodiment can also place the remaining capacitors outside the molding compound region 50 . In this case, this embodiment then in step 1315 solders the capacitors to the substrate. As shown in the structure 159 of FIG. 15 , an additional capacitor 1509 is soldered on the substrate 1508 , and the capacitor 1503 and the capacitor 1509 increase the capacitance value as a whole, greatly increasing the power supply stability.
  • the present disclosure uses the distorted zero area of the molding compound area as a capacitor area, which is used to layout the capacitors required by the chip to reduce the area of the chip.
  • the reduction in the size of the chip means that a single wafer can accommodate More wafers, thereby achieving the technical effect of reducing manufacturing costs.
  • a method of laying out an integrated circuit on a wafer of a package structure comprising: chip-mounting a system-on-a-chip in a system area on the wafer; chip-mounting memory in a storage area on the wafer; and The capacitor area on the wafer is chip-mounted with a plurality of capacitors; wherein, the capacitor area is a distorted zero area other than the system area and the storage area.
  • Clause A2 The method of clause A1, wherein the capacitive region is located between the system region and the wafer edge.
  • Clause A3 The method of Clause A1, wherein the capacitive region is located between the system region and the storage region.
  • Clause A4 The method of Clause A1, wherein the capacitive region is located between the storage region and the wafer edge.
  • Clause A5 The method of Clause A1, wherein the capacitive region is located between a plurality of the storage regions.
  • Clause A6 The method of clause Al, wherein the plurality of capacitors are greater than 0.5 millimeters from the system area.
  • Clause A7 The method of clause A1 , wherein the plurality of capacitors are greater than 1 millimeter away from the storage area.
  • Clause A8 The method of clause A1, wherein the plurality of capacitors are greater than 0.5 millimeters from the edge of the wafer.
  • Clause A9 The method of Clause A1, wherein a distance between the plurality of capacitors is greater than 0.5 mm.
  • Clause A10 The method of any one of clauses A1 to 9, further comprising: forming a plurality of redistribution layers on the first side of the wafer using through silicon vias; forming a plurality of first redistribution layers on the plurality of redistribution layers wafer bumps; and bonding the plurality of first wafer bumps with the system-on-chip, the memory and the plurality of capacitors.
  • Clause A11 The method according to Clause A10, further comprising: filling the system area and the storage area with underfill.
  • Clause A12 The method of Clause A11, further comprising: plastic encapsulating the system-on-chip, the memory, and the plurality of capacitors to form a CoW structure.
  • Clause A13 The method of Clause A12, further comprising: glass bonding the CoW structure; and polishing the wafer such that a surface of the other side of the TSV is the same as a surface of the second side of the wafer flush.
  • Clause A14 The method of Clause A13, further comprising: forming a plurality of second wafer bumps on the second side to connect the other side of the through silicon vias; and soldering the plurality of second wafers Round bump to substrate.
  • Item A15 The method of Item A14, wherein the steps of forming the plurality of first wafer bumps and the steps of forming the plurality of second wafer bumps employ a C4 process.
  • Clause A17 The method of Clause A10, wherein a center-to-center distance between the plurality of first wafer bumps and the plurality of second wafer bumps is 150 microns.
  • Clause A18 The method of Clause A1, wherein the memory is a high bandwidth memory.
  • Clause A19 The method of Clause A1, wherein the package structure is a CoWoS package structure.
  • a package structure comprising: a system-on-chip, a system area disposed on a wafer; a memory, a storage area disposed on the wafer; and a plurality of capacitors, a capacitor area disposed on the wafer; wherein, The capacitance region is a distorted zero region other than the system region and the storage region.
  • Clause A21 The package structure of Clause A20, wherein the capacitive area is located between the system area and the die edge.
  • Clause A22 The package structure of Clause A20, wherein the capacitor area is located between the system area and the storage area.
  • Clause A23 The package structure of Clause A20, wherein the capacitive region is located between the storage region and the die edge.
  • Item A24 The package structure of Item A20, wherein the capacitor region is located between a plurality of the storage regions.
  • Clause A25 The package structure of any one of clauses A20 to 24, wherein a distance of the plurality of capacitors from the system area is greater than 0.5 mm.
  • Clause A26 The package structure of any one of clauses A20 to 24, wherein a distance between the plurality of capacitors and the storage area is greater than 1 millimeter.
  • Clause A27 The package structure of any one of clauses A20 to 24, wherein a distance of the plurality of capacitors from the edge of the die is greater than 0.5 mm.
  • Clause A28 The package structure of any one of clauses A20 to 24, wherein a distance between the plurality of capacitors is greater than 0.5 mm.
  • Clause A29 The package structure of Clause A1, wherein the memory is a high-bandwidth memory.
  • Clause A30 The packaging structure of Clause A1, wherein the packaging structure is a CoWoS packaging structure.

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Abstract

一种封装结构、集成电路装置、板卡及在封装结构的晶片上布局集成电路的方法。在晶片上的系统区域（51）贴装片上系统（501）；在晶片上的存储区域（52）贴装内存（502）；在晶片上的电容区域（53）贴装多个电容器（503）。所述电容区域（53）为所述系统区域（51）及所述存储区域（52）以外的畸零区域。

Description

封装结构、装置、板卡及布局集成电路的方法
相关申请的交叉引用
本申请要求于2020年9月29日申请的，申请号为2020110533192，名称为“封装结构、装置、板卡及布局集成电路的方法”的中国专利申请的优先权。
技术领域
本披露一般地涉及半导体。更具体地，本披露涉及封装结构、集成电路装置、板卡及在封装结构的晶片上布局集成电路的方法。
背景技术
CoWoS(chip on wafer on substrate)是一种整合生产技术，先将芯片通过CoW(chip on wafer)的封装制程连接至硅晶圆，再把CoW芯片与基板(substrate)连接，整合成CoWoS。通过这种技术可以把多颗芯片封装到一起，平面上的裸芯片彼此通过硅中介层(silicon interposer)互联，达到了封装体积小、功耗低、引脚少的技术功效。CoWoS的电源是以电容器蓄电来提供。
一种常见的应用是将多个不同功能的芯片以CoWoS进行封装，但配置多个电容时，往往会额外增加芯片面积，导致成本提高，因此一种节省面积来容置电容器的方案是迫切需要的。
发明内容
为了至少部分地解决背景技术中提到的技术问题，本披露的方案提供了封装结构、集成电路装置、板卡及在封装结构的晶片上布局集成电路的方法。
在一个方面中，本披露揭示一种在封装结构的晶片上布局集成电路的方法，包括：在所述晶片上的系统区域芯片贴装片上系统；在所述晶片上的存储区域芯片贴装内存；以及在所述晶片上的电容区域芯片贴装多个电容器。其中，所述电容区域为所述系统区域及所述存储区域以外的畸零区域。
在另一个方面，本披露揭示一种封装结构，包括片上系统、内存及多个电容器。片上系统设置在晶片上的系统区域；内存设置在所述晶片上的存储区域；多个电容器设置在所述晶片上的电容区域。其中所述电容区域为所述系统区域及所述存储区域以外的畸零区域。
在另一个方面，本披露揭示一种集成电路装置，包括前述的封装结构；亦揭示一种板卡，包括前述的集成电路装置。
本披露的方案为了充分利用晶片的面积，适当地规划电容器的布局，以节省面积，不仅提升电容值，还可节省制造成本。
附图说明
通过参考附图阅读下文的详细描述，本披露示例性实施方式的上述以及其他目的、特征和优点将变得易于理解。在附图中，以示例性而非限制性的方式示出了本披露的若干实施方式，并且相同或对应的标号表示相同或对应的部分其中：
图1是示出本披露实施例的板卡的结构图；
图2是示出本披露实施例的集成电路装置的结构图；
图3是示出本披露实施例的计算装置的内部结构示意图；
图4是示出本披露实施例的处理器核的内部结构示意图；
图5是示出本披露实施例的一种封装结构的布局示意图；
图6是示出本披露实施例的另一种封装结构的布局示意图；
图7是示出本披露实施例的另一种封装结构的布局示意图；
图8是示出本披露实施例的另一种封装结构的布局示意图；
图9是示出本披露实施例中与电容器相关的各个间距的限制；
图10是示出本披露另一个实施例在晶片上布局集成电路的流程图；
图11是示出本披露实施例的CoW的封装制程结构剖面图；
图12是示出本披露实施例的CoWoS的封装制程结构剖面图；
图13是示出本披露另一个实施例在晶片上制成CoWoS结构的流程图；
图14A是示出本披露另一实施例的各步骤相应的封装结构剖面图；
图14B是示出本披露另一实施例的各步骤相应的封装结构剖面图；
图15A是示出本披露另一实施例的各步骤相应的封装结构剖面图；
图15B是示出本披露另一实施例的各步骤相应的封装结构剖面图；以及
图15C是示出本披露另一实施例的各步骤相应的封装结构剖面图。
具体实施方式
下面将结合本披露实施例中的附图，对本披露实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本披露一部分实施例，而不是全部的实施例。基于本披露中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本披露保护的范围。
应当理解，本披露的权利要求、说明书及附图中的术语“第一”、“第二”、“第三”和“第四”等是用于区别不同对象，而不是用于描述特定顺序。本披露的说明书和权利要求书中使用的术语“包括”和“包含”指示所描述特征、整体、步骤、操作、元素和/或组件的存在，但并不排除一个或多个其它特征、整体、步骤、操作、元素、组件和/或其集合的存在或添加。
还应当理解，在此本披露说明书中所使用的术语仅仅是出于描述特定实施例的目的，而并不意在限定本披露。如在本披露说明书和权利要求书中所使用的那样，除非上下文清楚地指明其它情况，否则单数形式的“一”、“一个”及“该”意在包括复数形式。还应当进一步理解，在本披露说明书和权利要求书中使用的术语“和/或”是指相关联列出的项中的一个或多个的任何组合以及所有可能组合，并且包括这些组合。
如在本说明书和权利要求书中所使用的那样，术语“如果”可以依据上下文被解释为“当...时”或“一旦”或“响应于确定”或“响应于检测到”。
下面结合附图来详细描述本披露的具体实施方式。
现今的半导体制程是从一块完整的晶圆(wafer)开始的，晶圆由纯硅构成的圆形薄片，一般分为6英寸、8英寸、12英寸等多种规格，晶圆会被切割成一个个的小块，这小块称为晶片(die)。每个晶片上会贴装有芯片(chip)，并布置好接线，以实现特定的电气功能。接着以晶片为单位封装成为一个颗粒，封装的目的是安放、固定、 密封、保护芯片和增强电热性能的作用，同时在芯片的触点上用导线连接到封装外壳的引脚上，一个芯片封装结构便完成了。
本披露的一个实施例是一种在晶片上形成的CoWoS封装结构，在此实施例中，芯片主要包括内存与片上系统，但本披露不限制仅能封装前述元件。
内存用于暂时存放片上系统所需的运算数据，以及与外部存储器交换的数据。在此实施例中，内存可以是高宽带内存(high bandwidth memory，HBM)，这是一种基于3D堆栈工艺制作的高性能DRAM，适用于高存储器带宽需求的应用场合，像是图形处理器、网上交换及转发设备(如路由器、交换器)等。
片上系统(SoC)指的是在单个芯片上集成一个完整的系统，对所有或部分必要的电子电路进行包分组的技术。在此实施例中，片上系统装配在板卡上。图1示出本披露实施例的一种板卡10的结构示意图。如图1所示，板卡10包括组合处理装置101，其是一种人工智能运算单元，用以支持各类深度学习和机器学习算法，满足计算机视觉、语音、自然语言处理、数据挖掘等领域复杂场景下的智能处理需求。特别是深度学习技术大量应用在云端智能领域，云端智能应用的一个显著特点是输入数据量大，对平台的存储能力和计算能力有很高的要求，此实施例的板卡10适用在云端智能应用，具有庞大的片外存储、片上存储和大量的计算能力。
组合处理装置101通过对外接口装置102与外部设备103相连接。外部设备103例如是服务器、计算机、摄像头、显示器、鼠标、键盘、网卡或wifi接口等。待处理的数据可以由外部设备103通过对外接口装置102传递至组合处理装置101。组合处理装置101的计算结果可以经由对外接口装置102传送回外部设备103。根据不同的应用场景，对外接口装置102可以具有不同的接口形式，例如PCIe接口等。
板卡10还包括用于存储数据的外部存储器104，其包括一个或多个存储单元105。外部存储器104通过总线与控制器件106和组合处理装置101进行连接和数据传输。板卡10中的控制器件106配置用于对组合处理装置101的状态进行调控。为此，在一个应用场景中，控制器件106可以包括单片机(Micro Controller Unit，MCU)。
图2是示出此实施例的组合处理装置101中的示意图。如图2中所示，组合处理装置101包括计算装置201、接口装置202、处理装置203和DRAM 204。在一种应用场景中，计算装置201、接口装置202、处理装置203整合成前述的片上系统。在另一种应用场景中，计算装置201本身即为前述的片上系统。
计算装置201配置成执行用户指定的操作，主要实现为单核智能处理器或者多核智能处理器，用以执行深度学习或机器学习的计算，其可以通过接口装置202与处理装置203进行交互，以共同完成用户指定的操作。
接口装置202用于在计算装置201与处理装置203间传输数据和控制指令。例如，计算装置201可以经由接口装置202从处理装置203中获取输入数据，写入计算装置201片上的存储装置。进一步，计算装置201可以经由接口装置202从处理装置203中获取控制指令，写入计算装置201片上的控制缓存中。替代地或可选地，接口装置202也可以读取计算装置201的存储装置中的数据并传输给处理装置203。
处理装置203作为通用的处理装置，执行包括但不限于数据搬运、对计算装置201的开启和/或停止等基本控制。根据实现方式的不同，处理装置203可以是中央处理器、图形处理器或其他通用和/或专用处理器中的一种或多种类型的处理器，这些处理器包 括但不限于数字信号处理器(digital signal processor，DSP)、专用集成电路(application specific integrated circuit，ASIC)、现场可编程门阵列(field-programmable gate array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等，并且其数目可以根据实际需要来确定。如前所述，仅就本披露的计算装置201而言，其可以视为具有单核结构或者同构多核结构。然而，当将计算装置201和处理装置203整合共同考虑时，二者视为形成异构多核结构。
DRAM 204即为前述的高宽带内存，用以存储待处理的数据，大小通常为16G或更大，用于保存计算装置201和/或处理装置203的数据。
图3示出了计算装置201的内部结构示意图。计算装置201用以处理计算机视觉、语音、自然语言、数据挖掘等输入数据，图中的计算装置201采用多核分层结构设计，其包括外部存储控制器301、外设通信模块302、片上互联模块303、同步模块304以及多个集群305。
外部存储控制器301可以有多个，在图中示例性地展示2个，其用以响应处理器核发出的访问请求，访问外部存储设备，例如图2中的DRAM 204，从而自片外读取数据或是将数据写入。外设通信模块302用以通过接口装置202接收来自处理装置203的控制信号，启动计算装置201执行任务。片上互联模块303将外部存储控制器301、外设通信模块302及多个集群305连接起来，用以在各个模块间传输数据和控制信号。同步模块304是一种全局同步屏障控制器(global barrier controller，GBC)，用以协调各集群的工作进度，确保信息的同步。多个集群305是计算装置201的计算核心，在图中示例性地展示4个，随着硬件的发展，本披露的计算装置201还可以包括8个、16个、64个、甚至更多的集群305。集群305用以高效地执行深度学习算法。
每个集群305包括多个处理器核(IPU core)306及一个存储核(MEM core)307。
处理器核306在图中示例性地展示4个，本披露不限制处理器核306的数量。其内部架构如图4所示。每个处理器核306包括三大模块：控制模块41、运算模块42及存储模块43。
控制模块41用以协调并控制运算模块42和存储模块43的工作，以完成深度学习的任务，其包括取指单元(instruction fetch unit，IFU)411及指令译码单元(instruction decode unit，IDU)412。取指单元411用以获取来自处理装置203的指令，指令译码单元412则将获取的指令进行译码，并将译码结果作为控制信息发送给运算模块42和存储模块43。
运算模块42包括向量运算单元421及矩阵运算单元422。向量运算单元421用以执行向量运算，可支持向量乘、加、非线性变换等复杂运算；矩阵运算单元422负责深度学习算法的核心计算，即矩阵乘及卷积。
存储模块43用来存储或搬运相关数据，包括神经元存储单元(neuron RAM，NRAM)431、权值存储单元(weight RAM，WRAM)432、输入/输出直接内存访问模块(input/output direct memory access，IODMA)433、搬运直接内存访问模块(move direct memory access，MVDMA)434。NRAM 431用以存储供处理器核306计算的输入、输出数据及中间结果；WRAM 432则用以存储深度学习网络的权值；IODMA 433通过广播总线309控制NRAM 431/WRAM 432与DRAM 204的访存；MVDMA 434则用以控制NRAM 431/WRAM 432与SRAM 308的访存。
回到图3，存储核307主要用以存储和通信，即存储处理器核306间的共享数据或中间结果、以及执行集群305与DRAM 204之间的通信、集群305间彼此的通信、处理器核306间彼此的通信等。在其他实施例中，存储核307具有标量运算的能力，用以执行标量运算。
存储核307包括共享存储单元(SRAM)308、广播总线309、集群直接内存访问模块(cluster direct memory access，CDMA)310及全局直接内存访问模块(global direct memory access，GDMA)311。SRAM 308承担高性能数据中转站的角色，在同一个集群305内不同处理器核306之间所复用的数据不需要通过处理器核306各自向DRAM 204获得，而是经SRAM 308在处理器核306间中转，存储核307只需要将复用的数据从SRAM 308迅速分发给多个处理器核306即可，以提高核间通讯效率，亦大大减少片上片外的输入/输出访问。
广播总线309、CDMA 310及GDMA 311则分别用来执行处理器核306间的通信、集群305间的通信和集群305与DRAM 204的数据传输。以下将分别说明。
广播总线309用以完成集群305内各处理器核306间的高速通信，此实施例的广播总线309支持核间通信方式包括单播、多播与广播。单播是指点对点(即单一处理器核至单一处理器核)的数据传输，多播是将一份数据从SRAM 308传输到特定几个处理器核306的通信方式，而广播则是将一份数据从SRAM 308传输到所有处理器核306的通信方式，属于多播的一种特例。
CDMA 310用以控制在同一个计算装置201内不同集群305间的SRAM 308的访存。GDMA 311与外部存储控制器301协同，用以控制集群305的SRAM 308到DRAM 204的访存，或是将数据自DRAM 204读取至SRAM 308中。
图5示出此实施例的一种封装结构的布局示意图，此封装结构的布局是位于晶片的模塑料(molding compound)区50，模塑料区50包括系统区域51及2个存储区域52，其中系统区域51位于模塑料区50的中央，存储区域52分别位于系统区域51的两侧。封装结构的芯片包括片上系统501及多个内存502，其中片上系统501为前述的片上系统，可以仅包括计算装置201或是包括计算装置201、接口装置202及处理装置203，片上系统501设置在系统区域51，而内存502为DRAM 204，在此实施例中共有6个，平均设置在存储区域52中，每一侧的存储区域52设置有3个内存502。
由于片上系统501与内存502的尺寸导致在针对这些芯片进行布局时会出现畸零区域，所述的畸零区域指的是模塑料区50中系统区域51及存储区域52以外的闲置面积，此实施例将CoWoS结构所需的电容器布局在这些畸零区域中。如图5所示，这种芯片布局会在系统区域51的顶侧及底侧出现畸零区域，电容器便布局在这些畸零区域中。更详细来说，封装结构的芯片还包括多个电容器503，模塑料区50包括2个电容区域53，分别位于模塑料区50的畸零区域，即系统区域51的顶侧及底侧，这些电容器503平均分布在所述的电容区域53中，以充分利用模塑料区50的面积。
如果电容区域53不够大到容置CoWoS结构所需的所有电容器，此实施例可以将剩余的电容器布局在模塑料区50外。如图5所示，晶片还包括非模塑料区54，位于模塑料区50的顶侧及底侧，用来容置更多的电容器。此实施例不限制非模塑料区54的位置，基本上模塑料区50四周都可以作为非模塑料区54，其大小视电容器的数量与尺寸而定。此实施例优先将电容器设置在模塑料区50内的畸零区域，如果空间不 足，再考虑将电容器设置在非模塑料区54。
此实施例不限制电容器的规格，根据芯片的具体需求，市面上任何合适的电容器均可采用，例如但不限于Murata公司所生产的型号为GRM2165C1H333GA01的电容器。
除了图5的芯片布局方式，图6示出此实施例的另一种封装结构的布局示意图。与前述布局方式不同处在于，畸零区域出现在模塑料区50的4个角落，电容器便布局在这些畸零区域中。更详细来说，模塑料区50包括4个电容区域53，分别位于模塑料区50的4个角落，这些电容器503平均分布在所述的电容区域53中，以充分利用模塑料区50的面积。
图7示出此实施例的另一种封装结构的布局示意图。与前述布局方式不同处在于，模塑料区50的4个角落设置了4个内存502，畸零区域出现在系统区域51两侧2个存储区域52间。因此模塑料区50包括2个电容区域53，分别位于在系统区域51两侧2个存储区域52间，这些电容器503平均分布在所述的电容区域53中，以充分利用模塑料区50的面积。
图8示出此实施例的另一种封装结构的布局示意图。与前述布局方式不同处在于，系统区域51设置了2个片上系统501，与图5的布局方式相同处为，畸零区域出现在系统区域51的顶侧及底侧，因此电容器503便布局在这些畸零区域中。
图5至图8所展示的几种芯片布局方式仅用以示例畸零区域可能出现的位置，即电容区域的位置。总的来说，电容区域位于模塑料区50的畸零区域，其可以是系统区域51与晶片边缘间、系统区域51与存储区域52间、存储区域52与晶片边缘间、存储区域52与存储区域52间。
由于半导体制程在工程上有极限，芯片与电容器的间距会有限制，以确保各元件能正常运作，不至于产生电气干扰。图9示出此实施例中与电容器相关的各个间距的限制。电容器503与系统区域51的距离d 1需大于0.5毫米，电容器503与存储区域52的距离d 2需大于1毫米，电容器503与晶片边缘(模塑料区50的边界901)的距离d 3需大于0.5毫米，电容器503彼此间的距离d 4需大于0.5毫米。
虽然图6至图8的芯片布局方式中未显示非模塑料区54，并不表示这些芯片布局方式不需要非模塑料区54来容置更多的电容器。本领域技术人员基于图5的说明，轻易地能够理解各种芯片布局方式都可以在模塑料区50四周配置非模塑料区54来容置电容器，故不赘述。
除了片上系统501及内存502，本披露的芯片还可以包括各种集成电路，例如各种无源和有源微电子器件，像是电阻器、其他电容器类型(例如MIMCAP)、电感器、二极管、金属氧化物半导体场效应晶体管(MOSFET)、互补金属氧化物半导体(CMOS)晶体管、双极结晶体管(BJT)、横向扩散金属氧化物半导体(LDMOS)晶体管、高功率金属氧化物半导体晶体管或其他类型的晶体管等。
此实施例将系统区域和存储区域以外的畸零区域作为电容区域，用来布局芯片所需的电容器，以减少晶片的面积，在晶圆大小不变的前提下，晶片的体积缩小意味着单一晶圆可以容置更多的晶片，进而达到降低制造成本的技术功效。
本披露的另一个实施例是一种在晶片上布局集成电路的方法，其流程图如图10所示。
在步骤1001中，在晶片上的系统区域芯片贴装片上系统。如前所述，芯片布局是位于晶片的模塑料区，模塑料区包括系统区域及存储区域，封装结构的芯片包括片上系统及内存，此实施例利用芯片贴装技术将片上系统设置在系统区域。
一种示例性的芯片贴装技术为可控塌陷芯片连接(controlled collapse chip connection，C4)。可控塌陷芯片连接是利用高温焊锡、助焊剂或锡膏施于基板上镀锡的电极或转印到芯片的锡球上，然后将芯片贴放于基板上，在贴装期间加热来回流连接或者在标准回流炉中批量回流。
在步骤1002中，在晶片上的存储区域芯片贴装内存。内存可以有多个，视实际需求而定。此实施例的内存可以是高宽带内存，高宽带内存是多层DRAM叠加在一块，最后贴装于存储区域中。高宽带内存通过打造高位宽低频率的显存，使得在提供比较大的显存位宽的基础上不需要那么高的频率，同样4GB容量下高宽带内存能提供的显存位宽为4096比特，比起GDDR5高出数倍。高宽带内存的出现使得芯片的布局从2D扩展到3D，有助于降低晶片的面积。
在步骤1003中，在晶片上的电容区域芯片贴装多个电容器。如前所述，此实施例的电容区域为系统区域及存储区域以外的畸零区域。此实施例将CoWoS结构所需的电容器布局在这些畸零区域中，以充分利用模塑料区50的面积，进而缩小晶片面积。此实施例的电容区域可以位于系统区域与晶片边缘间、系统区域与存储区域间、存储区域与晶片边缘间、存储区域与存储区域间。而与电容器相关的间距的限制如图9所示，不再赘述。
图11示出前述实施例的CoW的封装制程结构剖面图，所述结构首先在晶片1101上产生多个硅通孔(through silicon via，TSV)1102，硅通孔技术是一项高密度封装技术，用以取代引线键合技术，利用铜、钨、多晶硅等导电物质的填充，实现硅通孔的垂直电气互连。此技术通过垂直互连减少互联长度，降低信号延迟和不必要的电容/电感，实现芯片间的低功耗、高速通讯、增加宽带和实现器件集成的小型化。接着再利用微凸块制备技术(micro bump)，形成微凸块1103将芯片1104、电容器1105与晶片1101键合在一块。图中的芯片1104示例性地包括前述的片上系统及多个内存。
而CoWoS是在图11的CoW制程的基础上，再连接基板而成。图12示出CoWoS的封装制程结构，首先将芯片1104填上底部填充胶(underfill)，然后点上锡球(solder ball)1201，键合在基板(例如印制电路板)1202上，最后加上封装1203即完成。
本披露的实施例会在晶片1101上形成多个电容来供给芯片电源，生成的电容值越大，电源供给越稳定。对于耗电量高的深度学习芯片来说，大电容值是迫切需要的。本披露提出一种在CoWoS制程上，于畸零区域设置电容器，以提供大电容值。
本披露的另一个实施例是一种在晶片上制成CoWoS结构的方法，也就是先制成图11所示的CoW结构，再接着制成图12所示的CoWoS结构。此实施例的方法如图13所示，而图14及图15示出此实施例的各步骤相应的封装结构剖面图。
首先此实施例利用硅通孔在晶片的第一侧形成多个重布线层。更详细来说，在步骤1301中，在晶片1401(即晶片1101)的第一侧利用光罩蚀刻形成多个硅通孔层，在图14A中示例性地显示第一硅通孔层1402与第二硅通孔层1403。在此实施例中，如果晶片1401的厚度为775微米，则硅通孔层的深度为107微米。在步骤1302中，在第一侧表面利用热湿式氧化制程，生成水蒸气，与晶片的硅材质进行化学反应，在 第一侧表面生成第一介电层1404，第一介电层1404的成分为二氮化硅。在此步骤完成后，晶片1401的第一侧上形成结构141。
在步骤1303中，电镀导电层1409。导电层1409的材料为铜。在此步骤完成后，晶片1401的第一侧上形成结构142。
在步骤1304中，沉积多个重布线层1405。首先利用化学机械抛光(chemical mechanical polishing，CMP)将第一侧的表面打磨平整，将第一侧表面的导电层1409去掉，使得导电层1409只存在于硅通孔层中。重布线层1405的功用在于电性连接硅通孔层与芯片触点，根据芯片触点连接的实际需求，需要特别规划这些重布线层1405，使得触点正确地电性连接适当的硅通孔层。图14A中仅示例性地显示2层重布线的重布线层1405，其间沉积介电质。在此步骤完成后，晶片1401的第一侧上形成结构143。
在步骤1305中，沉积第二介电层1406。通过光罩布局，在各硅通孔层出口上方进行遮挡，使得各硅通孔层的出口上方的重布线层1405暴露未被第二介电层1406遮挡。在此步骤完成后，晶片1401的第一侧上形成结构144。
在步骤1306中，在多个重布线层1405上形成多个第一晶圆凸块。更详细来说，在每个硅通孔层上方采用C4制程形成第一晶圆凸块，使得第一晶圆凸块通过重布线层1405与硅通孔层电性连接。在此步骤完成后，晶片1401的第一侧上形成结构145。图纸示例性地显示2个第一晶圆凸块：第一晶圆凸块1407与第一晶圆凸块1408，第一晶圆凸块1407经过重布线层1405电性连接至第一硅通孔层1402，第一晶圆凸块1408经过重布线层1405电性连接至第二硅通孔层1403。两第一晶圆凸块的间距D1为60微米，中心距离D2为130、150或180微米。
接着执行步骤1307，键合多个第一晶圆凸块与片上系统、内存。在此步骤完成后，晶片1401的第一侧上形成如图15A所示的结构151，其中，芯片1501包括了前述的片上系统及内存。
在步骤1308中，在系统区域及存储区域填上底部填充胶。底部填充胶的材料可以提升对湿度保护、热冲击和各种机械冲击的影响，其功用在于提供更高的可靠性和更长的生命周期。在此步骤完成后，晶片1401的第一侧上形成如图15A所示的结构152，其中，底部填充胶1502保护芯片1501的触点及第一晶圆凸块。
在步骤1309中，键合多个第一晶圆凸块与电容器。在此步骤完成后，晶片1401的第一侧上形成如图15A所示的结构153，结构153示例性地显示2个电容器1503键合在多个第一晶圆凸块上，这些电容器1503是设置在电容区域上，也就是系统区域及存储区域以外的畸零区域。
在步骤1310中，塑封片上系统、内存及多个电容器，以形成CoW结构。也就是对芯片1501和电容器1503进行封装，在晶片1401的第一侧上形成如图15B所示的结构154，其中封装塑料1504包覆芯片1501和电容器1503，起到了安放、固定、密封、保护和增强电热性能的作用。至此实现了图11的CoW结构。
在步骤1311中，玻璃键合(glass bond)CoW结构。首先将整个CoW结构翻转过来，使得第一侧朝下，接着通过机械或化学方法将封装塑料1504与玻璃1505进行粘合后形成的层合材料，通常可以采用的粘合方法有：阳极键合法、黏着剂中间夹层法、硅(或玻璃)表面镀膜粘结法等。在此步骤完成后，晶片1401的第一侧上形成如图15B所示的结构155。
在步骤1312中，抛光晶片，使得硅通孔的另一侧的表面与晶片的第二侧的表面齐平。如图15B的结构156所示，此实施例利用化学机械抛光将晶片1401的第二侧的表面打磨平整，并让所有的硅通孔1506的表面与第二侧表面齐平，亦即硅通孔1506的表面暴露在第二侧。
在步骤1313中，在第二侧上形成多个第二晶圆凸块连接硅通孔的另一侧。如图15C的结构157所示，在第二侧上每个硅通孔1506的开口处采用C4制程形成第二晶圆凸块1507。
在步骤1314中，焊接第二晶圆凸块至基板。如图15C的结构158所示，首先去掉玻璃1505，再将晶片1401翻转过来，使得封装塑料1504朝上，先打磨封装塑料1504使得芯片1501的表面裸露在空气中，有助于散热，再将第二晶圆凸块1507焊接至基板1508上。其中，两第二晶圆凸块1507的间距为60微米，中心距离为130、150或180微米。至此完成了图12的CoWoS封装结构。
如果电容区域53不够大到容置CoWoS结构所需的所有电容器，此实施例亦可以将剩余的电容器布局在模塑料区50外。在这种情况下，此实施例接着在步骤1315中，焊接电容器至基板。如图15的结构159所示，将额外的电容器1509焊接在基板1508上，电容器1503搭配电容器1509整体提升电容值，大幅增加供电稳定性。
本披露将模塑料区的畸零区域作为电容区域，用来布局芯片所需的电容器，以减少晶片的面积，在晶圆大小不变的前提下，晶片的体积缩小意味着单一晶圆可以容置更多的晶片，进而达到降低制造成本的技术功效。
依据以下条款可更好地理解前述内容：
条款A1、一种在封装结构的晶片上布局集成电路的方法，包括：在所述晶片上的系统区域芯片贴装片上系统；在所述晶片上的存储区域芯片贴装内存；以及在所述晶片上的电容区域芯片贴装多个电容器；其中，所述电容区域为所述系统区域及所述存储区域以外的畸零区域。
条款A2、根据条款A1所述的方法，其中所述电容区域位于所述系统区域与所述晶片边缘间。
条款A3、根据条款A1所述的方法，其中所述电容区域位于所述系统区域与所述存储区域间。
条款A4、根据条款A1所述的方法，其中所述电容区域位于所述存储区域与所述晶片边缘间。
条款A5、根据条款A1所述的方法，其中所述电容区域位于多个所述存储区域间。
条款A6、根据条款A1所述的方法，其中所述多个电容器与所述系统区域的距离大于0.5毫米。
条款A7、根据条款A1所述的方法，其中所述多个电容器与所述存储区域的距离大于1毫米。
条款A8、根据条款A1所述的方法，其中所述多个电容器与所述晶片边缘的距离大于0.5毫米。
条款A9、根据条款A1所述的方法，其中所述多个电容器间的距离大于0.5毫米。
条款A10、根据条款A1至9任一项所述的方法，还包括：利用硅通孔在晶片的 第一侧形成多个重布线层；在所述多个重布线层上形成多个第一晶圆凸块；以及键合所述多个第一晶圆凸块与所述片上系统、所述内存及所述多个电容器。
条款A11、根据条款A10所述的方法，还包括：在所述系统区域及所述存储区域填上底部填充胶。
条款A12、根据条款A11所述的方法，还包括：塑封所述片上系统、所述内存及所述多个电容器，以形成CoW结构。
条款A13、根据条款A12所述的方法，还包括：玻璃键合所述CoW结构；以及抛光所述晶片，使得所述硅通孔的另一侧的表面与所述晶片的第二侧的表面齐平。
条款A14、根据条款A13所述的方法，还包括：在所述第二侧上形成多个第二晶圆凸块连接所述硅通孔的另一侧；以及焊接所述多个第二晶圆凸块至基板。
条款A15、根据条款A14所述的方法，其中所述形成多个第一晶圆凸块及所述形成多个第二晶圆凸块的步骤采用C4制程。
条款A16、根据条款A14所述的方法，其中所述多个第一晶圆凸块及所述多个第二晶圆凸块的间距为60微米。
条款A17、根据条款A10所述的方法，其中所述多个第一晶圆凸块及所述多个第二晶圆凸块间的中心距离为150微米。
条款A18、根据条款A1所述的方法，其中所述内存为高宽带内存。
条款A19、根据条款A1所述的方法，其中所述封装结构为CoWoS封装结构。
条款A20、一种封装结构，包括：片上系统，设置在晶片上的系统区域；内存，设置在所述晶片上的存储区域；以及多个电容器，设置在所述晶片上的电容区域；其中，所述电容区域为所述系统区域及所述存储区域以外的畸零区域。
条款A21、根据条款A20所述的封装结构，其中所述电容区域位于所述系统区域与所述晶片边缘间。
条款A22、根据条款A20所述的封装结构，其中所述电容区域位于所述系统区域与所述存储区域间。
条款A23、根据条款A20所述的封装结构，其中所述电容区域位于所述存储区域与所述晶片边缘间。
条款A24、根据条款A20所述的封装结构，其中所述电容区域位于多个所述存储区域间。
条款A25、根据条款A20至24任一项所述的封装结构，其中所述多个电容器与所述系统区域的距离大于0.5毫米。
条款A26、根据条款A20至24任一项所述的封装结构，其中所述多个电容器与所述存储区域的距离大于1毫米。
条款A27、根据条款A20至24任一项所述的封装结构，其中所述多个电容器与所述晶片边缘的距离大于0.5毫米。
条款A28、根据条款A20至24任一项所述的封装结构，其中所述多个电容器间的距离大于0.5毫米。
条款A29、根据条款A1所述的封装结构，其中所述内存为高宽带内存。
条款A30、根据条款A1所述的封装结构，其中所述封装结构为CoWoS封装结构。
条款A31、一种集成电路装置，包括根据条款A20-30的任意一项所述的封装结构。
条款A32、一种板卡，包括根据条款A31所述的集成电路装置。
以上对本披露实施例进行了详细介绍，本文中应用了具体个例对本披露的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本披露的方法及其核心思想；同时，对于本领域的一般技术人员，依据本披露的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本披露的限制。

Claims (32)

  1. 一种在封装结构的晶片上布局集成电路的方法，包括：
    在所述晶片上的系统区域芯片贴装片上系统；
    在所述晶片上的存储区域芯片贴装内存；以及
    在所述晶片上的电容区域芯片贴装多个电容器；
    其中，所述电容区域为所述系统区域及所述存储区域以外的畸零区域。
  2. 根据权利要求1所述的方法，其中所述电容区域位于所述系统区域与所述晶片边缘间。
  3. 根据权利要求1所述的方法，其中所述电容区域位于所述系统区域与所述存储区域间。
  4. 根据权利要求1所述的方法，其中所述电容区域位于所述存储区域与所述晶片边缘间。
  5. 根据权利要求1所述的方法，其中所述电容区域位于多个所述存储区域间。
  6. 根据权利要求1所述的方法，其中所述多个电容器与所述系统区域的距离大于0.5毫米。
  7. 根据权利要求1所述的方法，其中所述多个电容器与所述存储区域的距离大于1毫米。
  8. 根据权利要求1所述的方法，其中所述多个电容器与所述晶片边缘的距离大于0.5毫米。
  9. 根据权利要求1所述的方法，其中所述多个电容器间的距离大于0.5毫米。
  10. 根据权利要求1至9任一项所述的方法，还包括：
    利用硅通孔在晶片的第一侧形成多个重布线层；
    在所述多个重布线层上形成多个第一晶圆凸块；以及
    键合所述多个第一晶圆凸块与所述片上系统、所述内存及所述多个电容器。
  11. 根据权利要求10所述的方法，还包括：
    在所述系统区域及所述存储区域填上底部填充胶。
  12. 根据权利要求11所述的方法，还包括：
    塑封所述片上系统、所述内存及所述多个电容器，以形成CoW结构。
  13. 根据权利要求12所述的方法，还包括：
    玻璃键合所述CoW结构；以及
    抛光所述晶片，使得所述硅通孔的另一侧的表面与所述晶片的第二侧的表面齐平。
  14. 根据权利要求13所述的方法，还包括：
    在所述第二侧上形成多个第二晶圆凸块连接所述硅通孔的另一侧；以及
    焊接所述多个第二晶圆凸块至基板。
  15. 根据权利要求14所述的方法，其中所述形成多个第一晶圆凸块及所述形成多个第二晶圆凸块的步骤采用C4制程。
  16. 根据权利要求14所述的方法，其中所述多个第一晶圆凸块及所述多个第二晶圆凸块的间距为60微米。
  17. 根据权利要求10所述的方法，其中所述多个第一晶圆凸块及所述多个第二晶圆凸块间的中心距离为150微米。
  18. 根据权利要求1所述的方法，其中所述内存为高宽带内存。
  19. 根据权利要求1所述的方法，其中所述封装结构为CoWoS封装结构。
  20. 一种封装结构，包括：
    片上系统，设置在晶片上的系统区域；
    内存，设置在所述晶片上的存储区域；以及
    多个电容器，设置在所述晶片上的电容区域；
    其中，所述电容区域为所述系统区域及所述存储区域以外的畸零区域。
  21. 根据权利要求20所述的封装结构，其中所述电容区域位于所述系统区域与所述晶片边缘间。
  22. 根据权利要求20所述的封装结构，其中所述电容区域位于所述系统区域与所述存储区域间。
  23. 根据权利要求20所述的封装结构，其中所述电容区域位于所述存储区域与所述晶片边缘间。
  24. 根据权利要求20所述的封装结构，其中所述电容区域位于多个所述存储区域间。
  25. 根据权利要求20至24任一项所述的封装结构，其中所述多个电容器与所述系统区域的距离大于0.5毫米。
  26. 根据权利要求20至24任一项所述的封装结构，其中所述多个电容器与所述存储区域的距离大于1毫米。
  27. 根据权利要求20至24任一项所述的封装结构，其中所述多个电容器与所述晶片边缘的距离大于0.5毫米。
  28. 根据权利要求20至24任一项所述的封装结构，其中所述多个电容器间的距离大于0.5毫米。
  29. 根据权利要求1所述的封装结构，其中所述内存为高宽带内存。
  30. 根据权利要求1所述的封装结构，其中所述封装结构为CoWoS封装结构。
  31. 一种集成电路装置，包括根据权利要求20-30的任意一项所述的封装结构。
  32. 一种板卡，包括根据权利要求31所述的集成电路装置。
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